TWI719722B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, a buffer layer, a barrier layer, a dielectric layer and a source structure and a drain structure. The buffer layer is disposed on the substrate. The barrier layer is disposed on the buffer layer. The dielectric layer is disposed on the barrier layer. The passivation layer is disposed on the dielectric layer. The source structure and the drain structure is disposed on the passivation layer.

Description

Semiconductor structure and its forming method

The embodiment of the present invention relates to a semiconductor structure, and particularly relates to a high electron mobility transistor (HEMT).

High Electron Mobility Transistor (HEMT) is widely used in high-power semiconductor devices due to its advantages of high breakdown voltage and high output voltage.

Because GaN materials have a wide band gap and high-speed mobile electrons, GaN HEMTs are actively developed in radio frequency and power applications. The on-resistance of the GaN HEMT is mainly determined by the two-dimensional electron gas channel and the heterojunction between the source and drain and GaN. Due to the extremely high resistance of the source and drain with the heterojunction of GaN. Therefore, a heating process is usually used to diffuse part of the source and drain metal into the two-dimensional electron gas channel, thereby forming a good ohmic contact.

However, the source and drain materials will also diffuse to the oxide layer. Because silicon has a considerable degree of solid solubility (Solid Solubility) for some materials, such as aluminum, at about 400°C, during the process temperature above 400°C, aluminum will diffuse with the silicon surface. Will enter aluminum by diffusion effect, and aluminum will backfill the void left by silicon due to diffusion. Therefore, where aluminum and silicon are in contact, a so-called puncture phenomenon (Spiking) will be formed, causing the source and drain to interact with each other. The gate produces an undesirable electrical connection, resulting in a short circuit.

Although the existing high electron mobility transistors can generally improve the breakthrough phenomenon, they are not satisfactory in all aspects. Therefore, there is still a need for a new type of high electron mobility transistor to meet various requirements.

According to some embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure includes a substrate, a buffer layer, a barrier layer, a dielectric layer, a protective layer, and a source structure and a drain structure. The aforementioned buffer layer is provided on the substrate. The aforementioned barrier layer is provided on the buffer layer. The aforementioned dielectric layer is disposed on the barrier layer. The aforementioned protective layer is provided on the dielectric layer. The source structure and the drain structure are arranged on the protective layer.

According to some embodiments of the present invention, a method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a buffer layer on the substrate; forming a barrier layer on the buffer layer; forming a dielectric layer on the barrier layer; forming a protective layer on the dielectric layer; and forming a source structure and a drain structure on the On the protective layer.

Many different implementation methods or examples are disclosed below to implement the different features of the embodiments of the present invention. The following describes specific elements and their arrangement embodiments to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration, and should not be used to limit the scope of the embodiments of the present invention. For example, in the specification, it is mentioned that the first feature is formed on the second feature, which includes the embodiment in which the first feature and the second feature are in direct contact, and it also includes other embodiments between the first feature and the second feature. The embodiment of the feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or labels may be used in different embodiments. These repetitions are only used to describe the embodiments of the present invention simply and clearly, and do not represent a specific relationship between the different embodiments and/or structures discussed.

In addition, terms relative to space may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These spatial relative terms are used for ease of description The relationship between one element or feature(s) and another element(s) or feature in the illustration. These spatial relative terms include the different orientations of the device in use or operation, as well as the orientation described in the drawings. When the device is turned in different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position.

Here, the terms "about", "approximately", and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, without specifying "about", "approximately", "approximately", "about", "approximately" and "approximately" can still be implied. The meaning of "probably".

It can be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or parts, these elements, components, regions , Layers, and/or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and/or parts. Therefore, a first element, component, region, layer, and/or part discussed below may be referred to as a second element, component, region, layer, and/or without departing from the teachings of the present disclosure section.

Although the steps in some of the described embodiments are performed in a specific order, these steps can also be performed in other logical orders. In different embodiments, some of the steps described may be replaced or omitted, and some other operations may be performed before, during, and/or after the steps described in the embodiments of the present invention. Other features can be added to the high electron mobility transistor in the embodiment of the present invention. In different embodiments, some features may be replaced or omitted.

Unless otherwise specified, elements or layers with similar names can be formed by using similar materials or methods.

The embodiment of the present invention provides a semiconductor structure and a forming method thereof. By providing a protective layer arrangement between the source structure and the dielectric layer and between the drain structure and the dielectric layer, it is possible to avoid the problem of the source structure and the drain structure when the heating process is performed to form an ohmic contact. The conductive material diffuses into the dielectric layer, so as to avoid short circuit between the source structure and the drain structure and the gate structure.

FIGS. 1 to 5 are schematic cross-sectional views illustrating different stages of forming the semiconductor structure 100 according to some embodiments. As shown in FIG. 1, a substrate 102 is provided. In some embodiments, the substrate 102 may be an Al ₂ O ₃ (sapphire) substrate. In addition, the substrate 102 may also be a semiconductor substrate. The aforementioned semiconductor substrate may be an element semiconductor, including silicon or germanium; a compound semiconductor, including gallium nitride (GaN), silicon carbide, gallium arsenide, and phosphating Gallium (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide) and/or indium antimonide (indium antimonide); alloy semiconductors, including silicon germanium alloy (SiGe), phosphorous gallium arsenide alloy (GaAsP) , AlInAs, AlGaAs, GaInAs, GaInP, GaInP, and/or GaInAsP, or a combination of the above materials. In some embodiments, the substrate 102 may be a single crystal substrate, a multi-layer substrate, a gradient substrate, other suitable substrates, or a combination thereof. In addition, the substrate 102 may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a bottom plate, a buried oxide layer disposed on the bottom plate, or a buried oxide layer disposed on the bottom plate. Semiconductor layer.

Next, a buffer layer 104 is formed on the substrate 102. In some embodiments, the buffer layer 104 includes a III-V semiconductor, such as GaN. The buffer layer 104 may also include AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other appropriate III-V semiconductor materials, or a combination thereof. In some embodiments, molecular-beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metalorganic chemical vapor deposition (metalorganic chemical vapor deposition, MOCVD, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam deposition (molecular beam deposition, MBD), plasma enhanced chemical vapor deposition (CVD), other appropriate methods, or a combination of the above to form the buffer layer 104 on the substrate 102.

Next, a barrier layer 106 is formed on the buffer layer 104. In some embodiments, the barrier layer 106 includes a material different from the buffer layer 104. The barrier layer 106 may include a III-V semiconductor, such as Al _x Ga _1-x N, where 0>x>1. The barrier layer 106 may also include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other appropriate III-V group materials, or a combination of the foregoing. In some embodiments, molecular beam epitaxy, hydride vapor phase epitaxy, organic metal vapor deposition, chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam deposition The barrier layer 106 is formed on the buffer layer 104 by a method, a plasma enhanced chemical vapor deposition method, other suitable methods, or a combination of the above.

Since the materials of the buffer layer 104 and the barrier layer 106 are different, and their band gaps are different, a heterojunction is formed at the interface between the buffer layer 104 and the barrier layer 106. The energy band at the heterojunction is bent, and the conduction band (conduction band) is bent deep to form a quantum well, which confines the electrons generated by the piezoelectric effect (Piezoelectricity) in the quantum well. Therefore, the buffer layer 104 and the barrier Two-dimensional electron gas (2DEG) is formed at the interface of the layer 106, thereby forming a conduction current. As shown in FIG. 1, a channel region 108 is formed at the interface between the buffer layer 104 and the barrier layer 106, and the channel region 108 is where the two-dimensional electron gas forms a conduction current.

Next, referring to FIG. 2, a dielectric layer 110 is formed on the barrier layer 106. In some embodiments, the dielectric layer 110 includes SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , MgO, Sc ₂ O ₃ , HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO ₂ , ZnO ₂ , ZrO ₂ , AlSiN ₃ , SiC, or Ta ₂ O ₅ , other suitable dielectric materials, or a combination of the above. In some embodiments, molecular beam epitaxy, hydride vapor phase epitaxy, organometallic vapor deposition, chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam deposition The dielectric layer 110 is formed on the barrier layer 106 by a method, a plasma enhanced chemical vapor deposition method, other suitable methods, or a combination of the above.

Then, a protective layer 112 is formed on the dielectric layer 110. The protective layer 112 includes a high-temperature non-melting material, such as a material that does not melt at 550°C to 1000°C, a material that does not melt at 650°C to 1100°C, a material that does not melt at 750°C to 1200°C, or A material that does not melt at 850°C to 1300°C. For example, the material of the protective layer 112 includes TiN, SiN, the foregoing similar materials, or a combination of the foregoing. In some embodiments, molecular beam epitaxy, hydride vapor phase epitaxy, organic metal vapor deposition, chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam deposition A protective layer 112 is formed on the dielectric layer 110 by a method, a plasma enhanced chemical vapor deposition method, other appropriate methods, or a combination thereof. In some embodiments, the protective layer 112 may be a multilayer structure (not shown). For example, the protective layer 112 includes a high-temperature non-meltable material layer and a passivation layer on the high-temperature non-meltable material layer. Since the high-temperature non-melting material layer may be damaged by some subsequent processes, such as photoresist removal and surface cleaning processes, the passivation layer can prevent the high-temperature non-melting material layer from being damaged by some subsequent processes.

Next, referring to FIG. 3, an opening 114 passing through the protective layer 112, the dielectric layer 110, the barrier layer 106 and a portion of the buffer layer 104 is formed. In detail, by suitable processes such as spin coating or chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam deposition, plasma enhanced chemical vapor deposition, other appropriate methods or Other suitable deposition methods or a combination of the foregoing, the photoresist material is formed on the top surface of the protective layer 112, and then optical exposure, post-exposure baking and development are performed to remove part of the photoresist material to form a patterned light The resist layer, the patterned photoresist layer will serve as an etching mask for etching. Can perform double-layer or triple-layer photoresist. Then, use any acceptable etching process, such as reactive ion etching, neutral beam etching, similar etching or a combination of the foregoing, to etch through the protective layer 112, the dielectric layer 110, the barrier layer 106, and a portion of the buffer layer 104, To form an opening 114. It should be understood that the opening 114 may or may not pass through the passage area 108 according to actual needs. Although the cross-sectional shape of the opening is rectangular, it should be understood that the cross-sectional shape of the opening is only used for illustration and not for limiting the present invention.

Next, referring to FIG. 4, a conductive material layer 116 is formed on the protective layer 112. In some embodiments, the material of the conductive material layer 116 includes polysilicon, metal (such as tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, the like, or a combination thereof), metal alloy, metal nitride (such as Tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, the like, or a combination of the above), metal silicides (such as tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, etc.) Analogs, or a combination of the above), metal oxides (ruthenium oxide, indium tin oxide, its analogs, or a combination of the above), other suitable conductive materials, or a combination of the above. In a specific embodiment, the material of the conductive material layer 116 includes titanium, aluminum, or a combination of the foregoing. In some embodiments, molecular beam epitaxy, hydride vapor phase epitaxy, organic metal vapor deposition, chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam deposition The conductive material layer 116 is formed on the protective layer 112 by a method, a plasma enhanced chemical vapor deposition method, other suitable methods, or a combination of the above. In some embodiments, the conductive material layer 116 is a multilayer structure (not shown).

Next, referring to FIG. 5, the conductive material layer 116 and the protective layer 112 are patterned to form the source structure 116S, the drain structure 116D, and the protective layer 112'. In detail, by suitable processes such as spin coating or chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam deposition, plasma enhanced chemical vapor deposition, other appropriate methods or Other suitable deposition methods or a combination of the foregoing, the photoresist material is formed on the top surface of the conductive material layer 116, and then optical exposure, post-exposure baking and development are performed to remove part of the photoresist material to form a patterned The photoresist layer, the patterned photoresist layer will be used as an etching mask for etching. Can perform double-layer or triple-layer photoresist. Then, any acceptable etching process, such as reactive ion etching, neutral beam etching, similar etching, or a combination of the foregoing, is used to etch the exposed portions of the conductive material layer 116 and the protective layer 112.

The source structure 116S has an upper part outside the opening 114 and a lower part inside the opening 114. The upper portion of the source structure 116S has sidewalls flush with the sidewalls of the protective layer 112'. In some embodiments, the sidewalls of the protective layer 112' may extend beyond the sidewalls of the upper portion of the source structure 116S. The lower part of the source structure 116S is in direct contact with the buffer layer 104.

The drain structure 116D has an upper part outside the opening 114 and a lower part inside the opening 114. The upper portion of the drain structure 116D has sidewalls that are flush with the sidewalls of the protective layer 112'. In some embodiments, the sidewalls of the protective layer 112' may extend beyond the sidewalls of the upper portion of the drain structure 116D. The lower part of the drain structure 116D is in direct contact with the buffer layer 104.

Then, a heating process, such as a rapid thermal annealing process, is used to make the source structure 116S, the drain structure 116D, and the channel region 108 form an ohmic contact.

Since the protective layer is disposed between the upper part of the source structure and the dielectric layer and between the upper part of the drain structure and the dielectric layer, it can avoid the formation of ohmic contact (ohmic contact), the source structure and the drain The conductive material of the pole structure diffuses into the dielectric layer, so as to avoid short circuit between the source structure and the drain structure and other layer structures.

In addition, in order to form a good ohmic contact, the source structure and the drain structure usually have a fixed thickness ratio and a stacked structure of materials. The protective layer does not affect the stack structure of the source structure and the drain structure to maintain a fixed thickness ratio and material, and can prevent the conductive material of the source structure and the drain structure from diffusing into the dielectric layer, thereby increasing the process margin.

The semiconductor structure 100 may include other elements. For example, as shown in FIG. 6, the semiconductor structure 100 may include a gate structure 118 between the source structure 116S and the drain structure 116D, and a dielectric layer 120 between the protective layer 112' and the dielectric layer 110 and On the gate structure 118.

The gate structure 118 includes a gate 118a and a gate electrode layer 118b on the gate 118a. In some embodiments, the gate layer 118a may include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, MgGaN, other appropriately doped III-V materials, or a combination thereof. In a specific embodiment, the gate layer 118a includes MgGaN. In some embodiments, the gate electrode layer 118b may include polysilicon, metal (such as tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, the like, or a combination of the above), metal alloy, metal nitride (such as Tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, the like, or a combination of the above), metal silicides (such as tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, etc. Analogs, or a combination of the above), metal oxides (ruthenium oxide, indium tin oxide, its analogs, or a combination of the above), other suitable conductive materials, or a combination of the above. In a specific embodiment, the gate electrode layer 118b may include a metal nitride, such as titanium nitride (TiN). In some embodiments, the dielectric layer 120 includes SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , MgO, Sc ₂ O ₃ , HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO ₂ , ZnO ₂ , ZrO ₂ , AlSiN ₃ , SiC, or Ta ₂ O ₅ , other suitable dielectric materials, or a combination of the above.

Compared with the prior art, the semiconductor structure and its forming method provided by the embodiments of the present invention have at least the following advantages: (1) By providing a protective layer between the source structure and the dielectric layer, and between the drain structure and the dielectric layer, it is possible to avoid the source structure and the drain during the heating process to form an ohmic contact. The conductive material of the electrode structure diffuses into the dielectric layer, thereby avoiding short circuit between the source structure and the drain structure and the gate structure. (2) In order to form a good ohmic contact, the source structure and the drain structure usually have a fixed thickness ratio and a stacked structure of materials. The protective layer can not affect the stack structure of the source structure and the drain structure to maintain a fixed thickness ratio and material, and can prevent the conductive material of the source structure and the drain structure from diffusing into the dielectric layer, thereby increasing the process margin. (3) In addition, since the protective layer can also include a passivation layer, the high-temperature infusible material layer is prevented from being damaged by some subsequent processes, such as photoresist removal and surface cleaning processes.

Although the embodiments of the present invention and its advantages have been disclosed as above, it should be understood that any person with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of this disclosure is not limited to the manufacturing process, machinery, manufacturing, material composition, device, method, and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can disclose the content from this disclosure. It is understood that the current or future developed processes, machines, manufacturing, material composition, devices, methods, and steps can be used according to the present disclosure as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. Therefore, the protection scope of the present disclosure includes the above-mentioned manufacturing processes, machines, manufacturing, material composition, devices, methods, and steps. In addition, each patent application scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes each patent application scope and a combination of embodiments.

100: semiconductor structure 102: Base 104: buffer layer 106: barrier layer 108: Passage area 110: Dielectric layer 112, 112’: Protective layer 114: opening 116: conductive material layer 116S: source structure 116D: Drain structure 118: Gate structure 118a: Gate layer 118b: Gate electrode layer

The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, various features are not drawn to scale and are only used for illustration and illustration. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention. FIGS. 1 to 5 are cross-sectional views illustrating different stages of forming a semiconductor structure according to some embodiments. FIG. 6 is a cross-sectional view of a semiconductor structure according to some embodiments.

100: semiconductor structure

102: Base

104: buffer layer

106: barrier layer

108: Passage area

110: Dielectric layer

112’: Protective layer

116S: source structure

116D: Drain structure

Claims (12)

A semiconductor structure including: A base A buffer layer arranged on the substrate; A barrier layer is arranged on the buffer layer; A dielectric layer arranged on the barrier layer; A protective layer disposed on the dielectric layer; and A source structure and a drain structure are arranged on the protective layer. According to the semiconductor structure described in item 1 of the scope of patent application, the material of the protective layer includes TiN, SiN or a combination of the foregoing. The semiconductor structure described in item 1 of the scope of patent application, wherein the protective layer is a multilayer structure. The semiconductor structure described in item 3 of the scope of patent application, wherein the protective layer includes: A material layer, wherein the material layer includes TiN, SiN or a combination of the foregoing; and A passivation layer is arranged on the material layer. According to the semiconductor structure described in claim 1, wherein the source structure and the drain structure directly contact the buffer layer. The semiconductor structure described in item 1 of the scope of the patent application further includes a gate structure disposed between the source structure and the drain structure. A method for forming a semiconductor structure includes: Provide a base; Forming a buffer layer on the substrate; Forming a barrier layer on the buffer layer; Forming a dielectric layer on the barrier layer; Forming a protective layer on the dielectric layer; and A source structure and a drain structure are formed on the protective layer. According to the method for forming a semiconductor structure described in item 7 of the scope of the patent application, the material of the protective layer includes TiN, SiN or a combination of the foregoing. According to the method for forming a semiconductor structure described in item 7 of the scope of the patent application, the protective layer is a multilayer structure. According to the method for forming a semiconductor structure described in item 9 of the scope of patent application, the protective layer includes: A material layer, wherein the material layer includes TiN, SiN or a combination of the foregoing; and A passivation layer is arranged on the material layer. According to the method for forming a semiconductor structure described in item 7 of the scope of patent application, the source structure and the drain structure directly contact the buffer layer. The method for forming a semiconductor structure as described in item 7 of the scope of the patent application further includes forming a gate structure between the source structure and the drain structure.

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