JP7162833B2 - Semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly to a semiconductor device having a wide bandgap and high carrier mobility and a method of manufacturing the semiconductor device.

In recent years, the demand for high-power devices has increased rapidly, and they have already become key devices for hybrid cars and high-efficiency trains. High-power devices are positioned as key devices to support the future smart society. Therefore, it is believed that the demand for high-power devices will continue to increase in the future.

Wide bandgap semiconductors are needed to provide high power devices.
Among wide bandgap semiconductors, gallium oxide (Ga ₂ O ₃ ) is a semiconductor that has attracted particular attention in recent years because it has an extremely wide bandgap of 4.8 to 5.0 eV. For this reason, the development of semiconductor devices using Ga ₂ O ₃ has been vigorously pursued, and is disclosed, for example, in Japanese Unexamined Patent Application Publication No. 2002-200013. There, β-Ga ₂ O ₃ is used as a gallium oxide semiconductor.

Here, β-Ga ₂ O ₃ is a crystal with a stable structure, and has a crystal lattice of a=1.2214 nm, b=0.30371 nm, c=0.57981 nm, α=γ=90°, β=108. It is an 83° monoclinic crystal. Its bandgap is 4.8-4.9 eV and its critical electric field strength is estimated to be about 8 MV/cm.

JP 2016-51795 A

Since the β-Ga ₂ O ₃ semiconductor has a wide bandgap and a high withstand voltage, it is used in semiconductor devices for high power applications (for example, MISFET (Metal Insulator Semiconductor Field Effect Transistor) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor)). However, it has the problem of low carrier mobility, making it difficult to apply to high-frequency devices and high-speed logic.
A problem to be solved by the present invention is to provide a semiconductor device having a wide bandgap, excellent dielectric strength and high carrier mobility, and a method of manufacturing the same.

The configuration of the present invention is shown below.
(Configuration 1)
a semiconductor layer containing crystals of gallium oxide;
a gate electrode;
an insulator layer provided between the semiconductor layer and the gate electrode;
The semiconductor device, wherein the gallium oxide crystal has an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less.
(Configuration 2)
a semiconductor layer made of gallium oxide crystals;
a gate electrode;
an insulator layer provided between the semiconductor layer and the gate electrode;
The semiconductor device, wherein the gallium oxide crystal has an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less.
(Composition 3)
3. The semiconductor nanosheet according to Structure 1 or 2, wherein the gallium oxide crystal is at least either a hexagonal crystal or a cubic crystal.
(Composition 4)
3. The semiconductor device according to any one of Structures 1 to 3, wherein the semiconductor layer has a surface roughness of 0 nm or more and 0.5 nm or less.
(Composition 5)
3. The semiconductor device according to any one of Structures 1 to 3, wherein the semiconductor layer has a surface roughness of 0 nm or more and 0.2 nm or less.
(Composition 6)
The semiconductor device according to any one of configurations 1 to 5, wherein the semiconductor layer is an n-type semiconductor.
(Composition 7)
7. The semiconductor device according to any one of Structures 1 to 6, wherein the semiconductor layer contains at least one dopant selected from the group consisting of Si, Ge, Sn, F, and Cl.
(Composition 8)
The insulator layer is an oxide, nitride, or oxynitride of at least one element selected from the group of elements consisting of Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and rare earth elements. 8. The semiconductor device according to any one of structures 1 to 7, having
(Composition 9)
9. Structures 1 to 8, wherein the gate electrode comprises at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly-Si. 1. A semiconductor device according to any one of the above.
(Configuration 10)
A method for manufacturing a semiconductor device according to any one of configurations 1 to 9,
a substrate preparation step of preparing a gallium nitride crystal substrate containing a dopant;
a gallium oxide semiconductor layer forming step of forming a gallium oxide semiconductor layer on the gallium nitride crystal substrate;
an insulator layer forming step of forming an insulator layer on the gallium oxide semiconductor layer;
A method of manufacturing a semiconductor device, comprising a gate electrode forming step of forming a gate electrode on the insulator layer.
(Composition 11)
A method for manufacturing a semiconductor device according to any one of configurations 1 to 9,
a substrate preparation step of preparing a gallium nitride crystal substrate containing a dopant;
a first gallium oxide semiconductor layer forming step of forming a first gallium oxide semiconductor layer on the gallium nitride crystal substrate;
a gallium oxide forming step of epitaxially forming a gallium oxide layer on the first gallium oxide semiconductor layer;
a dopant implantation step of implanting a dopant into the gallium oxide to form a second gallium oxide semiconductor layer;
a substrate forming step of depositing and forming a rigid substrate on the second gallium oxide semiconductor layer;
a gallium nitride crystal substrate removing step of removing the gallium nitride crystal substrate;
an insulator layer forming step of forming an insulator layer on the first gallium oxide semiconductor layer;
A method of manufacturing a semiconductor device, comprising a gate electrode forming step of forming a gate electrode on the insulator layer.
(Composition 12)
12. The method of manufacturing a semiconductor device according to Structure 10 or 11, wherein the gallium nitride crystal substrate is a single crystal with a wurtzite structure.
(Composition 13)
In the step of forming the gallium oxide semiconductor layer and the first gallium oxide semiconductor layer, the gallium nitride crystal substrate is treated with sulfuric acid, hydrogen peroxide solution, ammonia, hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, and potassium hydroxide. 13. The method of manufacturing a semiconductor device according to any one of configurations 10 to 12, comprising a step of surface treatment using at least one selected from .
(Composition 14)
Configuration 10, wherein the step of forming the gallium oxide semiconductor layer and the first gallium oxide semiconductor layer includes the step of subjecting the gallium nitride crystal substrate to at least one of plasma oxidation and ozone oxidation at 500° C. or less. 13. The method of manufacturing a semiconductor device according to any one of 12 to 12.
(Composition 15)
The step of forming the gallium oxide semiconductor layer and the first gallium oxide semiconductor layer includes, on the gallium nitride crystal substrate, electron beam evaporation at 700° C. or lower, MBE at 700° C. or lower, CVD at 870° C. or lower, and CVD at 700° C. or lower. 13. The semiconductor device of any one of arrangements 10-12, comprising forming the oxide using at least one method selected from the group consisting of HVPE, ALD at 400° C. or less, and sputtering at 500° C. or less. Production method.

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a semiconductor device (MISFET, MOSFET, etc.) having a wide bandgap of a semiconductor layer, excellent withstand voltage, and high mobility, and a manufacturing method thereof.

FIG. 2 is a cross-sectional view showing the structure of the semiconductor device of the present invention; FIG. 2 is a structural diagram of a cubic crystal of gallium oxide viewed from the (100) plane. FIG. 2 is a structural diagram of a cubic crystal of gallium oxide viewed from the (111) plane. FIG. 2 is a structural diagram showing the arrangement of oxygen atoms at a cut end of cubic gallium oxide sliced along the (111) plane. FIG. 4 is a flow chart showing the manufacturing process of the first embodiment; FIG. 4 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the present invention; FIG. 4 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the present invention; The flowchart figure which shows the manufacturing process of 2nd Embodiment. FIG. 4 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the present invention; FIG. 4 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the present invention; FIG. 4 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the present invention; Cross-sectional TEM observation image and FFT diagram showing the structure of the film. FIG. 2 is an AFM measurement diagram of the surface roughness of the gallium oxide film produced.

The inventor intensively studied the reason why a semiconductor device using a semiconductor layer made of β-Ga ₂ O ₃ having excellent potential as described above does not have the expected high mobility.
As a result, it was found that the interface of the semiconductor layer made of β-Ga ₂ O ₃ was physically rough, and carrier scattering occurred there to prevent the mobility from increasing. That is, when the β-Ga ₂ O ₃ semiconductor layer is formed, the interface between the β-Ga ₂ O ₃ semiconductor layer is physically roughened to form a rough surface, which is one of the reasons why the mobility does not increase. I figured out what was going on.

Therefore, the inventor has made extensive research on a semiconductor device in which the interface of the semiconductor layer does not become rough, and the surface does not become rough, while making the most of the high potential of the gallium oxide semiconductor as a high-power semiconductor.

As a result, a semiconductor layer made of gallium oxide (gallium oxide semiconductor layer) is formed on a semiconductor layer made of gallium nitride (GaN) crystal, and the gallium oxide semiconductor layer has a lattice constant of 0.28 nm or more and 0.34 nm along the a-axis. It has been found that interfacial scattering of carriers can be suppressed and high mobility can be obtained by including the following Ga ₂ O ₃ crystals. In particular, if the gallium oxide semiconductor layer is made of a Ga ₂ O ₃ crystal having a lattice constant of 0.28 nm or more and 0.34 nm or less along the a-axis, interfacial scattering of carriers is greatly suppressed, and a very high mobility can be obtained. I found out that it can be done. With this configuration, in addition to mobility, the gallium oxide semiconductor layer has fewer crystal defects and fewer trap sites, so it is possible to provide a semiconductor device having excellent electrical characteristics including dielectric strength. .

<Embodiment 1>
EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated, referring drawings.
As shown in FIG. 1, the semiconductor device 1010 of Embodiment 1 has a GaN substrate 11, a gallium oxide semiconductor layer 12, an insulator layer (gate insulating film) 13, and a gate electrode 14 as basic components.

The GaN substrate 11 is single-crystal GaN (0001), and its crystal structure is preferably a wurtzite structure because of its high stability. The GaN substrate 11 is an n-type semiconductor substrate containing n-type impurities (dopants). At least one or more selected from the group consisting of silicon (Si), germanium (Ge), and oxygen (O) can be used as the dopant. The amount of dopant is preferably 5×10 ¹⁵ /cm ³ or more and 5×10 ¹⁹ /cm ³ or less. If the dopant amount is outside this range, it becomes difficult to form the gallium oxide semiconductor layer 12 formed on the GaN substrate 11 as an n-type semiconductor layer.

The gallium oxide semiconductor layer 12 is a film containing a crystal of gallium oxide having a lattice constant of 0.28 nm or more and 0.34 nm or less along the a-axis, in which the crystal lattice of single-crystal GaN and the in-plane lattice constant a are substantially matched. . It has been found that by doing so, the defects in the gallium oxide semiconductor layer 12 are reduced, the number of trap sites is reduced, and the surface roughness of the gallium oxide semiconductor layer 12 is extremely small.
The amount of gallium oxide crystals having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less in the gallium oxide semiconductor layer 12 is preferably 50% by volume or more, more preferably 70% by volume or more, and more preferably 100% by volume. Even more preferred.
Here, the gallium oxide semiconductor layer 12 preferably contains a large amount of gallium oxide crystals having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. As this amount increases, the number of defects in the gallium oxide semiconductor layer 12 decreases, the number of trap sites decreases, and the surface roughness of the gallium oxide semiconductor layer 12 decreases.

The gallium oxide semiconductor layer 12 is preferably made of hexagonal, cubic, or hexagonal and cubic gallium oxide with a lattice constant of 0.28 nm or more and 0.34 nm or less along the a-axis.
The crystal structure of wurtzite GaN is a hexagonal crystal with an a-axis lattice constant of 0.319 nm. The interface has extremely high smoothness and extremely suppressed roughness. As a result, the surface of the gallium oxide semiconductor layer 12 has extremely high smoothness and extremely suppressed roughness.

Here, the lattice constant of the a-axis in the present invention refers to the normal lattice constant of the a-axis in the case of a hexagonal crystal, and in the case of a cubic crystal, the crystal lattice at the cut end when sliced along the (111) plane. refers to the lattice constant of

FIG. 2 is a view of a cubic gallium oxide crystal, for example, a γ-Ga ₂ O ₃ crystal, viewed from the (100) plane. show. No hexagonal oxygen atom arrangement is observed in the (100) plane (in-plane), and lattice matching does not occur with the GaN semiconductor in contact with this plane.

FIG. 3 is a view of a cubic gallium oxide, eg, γ-Ga ₂ O ₃ crystal viewed from the (111) plane. Here, as in FIG. 2, 2001 in FIG. 3 represents oxygen atoms (O) and 2002 represents gallium atoms (Ga). When this crystal is sliced on the (111) plane and where the oxygen atoms 2001 are present, the arrangement of atoms located at the slice is shown in FIG. As can be seen from FIG. 4, the oxygen atoms 2001 at this cut (in this in-plane) have the same crystal arrangement (crystal lattice 2011) as the hexagonal crystal.
In the present invention, a ₁ indicated by 2021, a ₂ indicated by 2022, and a ₃ indicated by 2023 in FIG. The values of ₁ , a ₂ and a ₃ are approximately equal and are represented by the lattice constant a.

The inventor believes that the lattices of the GaN substrate 11 and the gallium oxide semiconductor layer 12 are matched when the gallium oxide semiconductor layer 12 is gallium oxide having a hexagonal crystal structure with an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. As a result, the gallium oxide semiconductor layer 12 has fewer crystal defects, fewer trap sites, and extremely small surface roughness. In addition, when the gallium oxide semiconductor layer 12 is cubic gallium oxide with the (111) plane, the inventors have found that when the lattice constant of the a-axis is 0.28 nm or more and 0.34 nm or less, the nitride of the wurtzite structure is a hexagonal structure. It was found that the gallium oxide semiconductor layer 12 has a sufficiently lattice-matched lattice, the crystal defects of the gallium oxide semiconductor layer 12 are small, the trap sites are few, and the surface roughness of the gallium oxide semiconductor layer 12 is extremely small. Furthermore, the inventors have found that the gallium oxide semiconductor layer 12 has a hexagonal structure and a cubic gallium oxide with a lattice constant of 0.28 nm or more and 0.34 nm or less on the a-axis, and a wurtzite structure having a hexagonal structure. The gallium nitride and the lattice are sufficiently matched, the crystal defects of the gallium oxide semiconductor layer 12 are reduced, the trap sites are reduced, and the surface roughness of the gallium oxide semiconductor layer 12 is also extremely small. .

The gallium oxide semiconductor layer 12 may be composed of ε-structured gallium oxide or γ-structured gallium oxide, or may be composed of a combination of ε-structured gallium oxide and γ-structured gallium oxide.
Here, the ε-structure gallium oxide is a hexagonal crystal, and its a-axis crystal lattice constant is 0.290 nm. The γ-structure gallium oxide is a cubic crystal, and the crystal lattice constant of the a-axis on the (111) plane is 0.291 nm.

The gallium oxide semiconductor layer 12 is preferably a gallium oxide film containing ε-Ga ₂ O ₃ in an amount of 50 volume % or more, preferably 70 volume % or more and 100 volume % or less.
Further, the gallium oxide semiconductor layer 12 may contain 70% by volume or more and 90% by volume or less of ε-Ga ₂ O ₃ and 10% by volume or more and 30% by volume or less of γ-Ga ₂ O ₃ .
The crystal plane of the gallium oxide semiconductor layer 12 is preferably aligned with the crystal plane of the single crystal GaN (0001) forming the GaN substrate 11 .

If the gallium oxide semiconductor layer 12 is not a gallium oxide film containing 50% by volume or more of gallium oxide crystals having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, the gallium oxide semiconductor layer 12 defects are increased, and the surface roughness of the gallium oxide semiconductor layer 12 is also increased.
Further, the gallium oxide semiconductor layer 12 is a gallium oxide film containing 50% by volume or more of at least one of hexagonal and cubic gallium oxide having a lattice constant of 0.28 nm to 0.34 nm along the a-axis. If the conditions are not satisfied, defects in the gallium oxide semiconductor layer 12 are increased, trap sites are generated in large numbers, and the surface roughness of the gallium oxide semiconductor layer 12 is increased.
Further, the gallium oxide crystal film 12 contains ε-Ga ₂ O ₃ or ε-Ga ₂ O ₃ and γ-Ga ₂ O ₃ and ε-Ga ₂ O ₃ or ε-Ga ₂ O ₃ and γ- If Ga ₂ O ₃ is contained in the ratio shown above, the defects in the gallium oxide semiconductor layer 12 are increased, a large number of trap sites are generated, and the surface roughness of the gallium oxide semiconductor layer 12 is also large. become a thing.

Here, the film thickness of the gallium oxide semiconductor layer 12 is preferably 2 nm or more and 30 nm or less, more preferably 5 nm or more and 30 nm or less. Note that ε-Ga ₂ O ₃ and γ-Ga ₂ O ₃ are crystal structures of gallium oxide films that are positioned as metastable gallium oxide films.

The surface roughness of the gallium oxide semiconductor layer 12 is preferably 0 nm or more and 0.5 nm or less, more preferably 0 nm or more and 0.2 nm or less, in terms of RMS (Root Mean Square). When the surface roughness of the gallium oxide semiconductor layer 12 is within this range, scattering of carriers is reduced and high carrier mobility can be obtained.

Since the gallium oxide semiconductor layer 12 is formed by inheriting the n-type dopant from the oxide formation layer of the GaN substrate 11 , the same kind of dopant as the GaN substrate 11 exists in the gallium oxide semiconductor layer 12 . Moreover, since it is active as a dopant, the gallium oxide semiconductor layer 12 functions as an n-type semiconductor. Further, the gallium oxide semiconductor layer 12 also takes in trace amounts of nitrogen (N) and carbon (C).
Here, the dopant amount may be adjusted by implanting an n-type dopant into the gallium oxide semiconductor layer 12 . At least one or more selected from the group consisting of silicon (Si), germanium (Ge), tin (Sn), fluorine (F), and chlorine (Cl) can be used as the dopant. Examples of the dopant implantation method include an ion implantation method and an impurity diffusion method.

Al ₂ O ₃ , SiO ₂ , SiN, SiON, Ta ₂ O ₃ , HfO ₂ , HfSiO _x or the like is used as the gate insulating film 13, and the formation method thereof is ALD, PE-ALD, sputtering, or CVD. etc. can be mentioned. Here, the gate insulating film 13 may be a single-layer film, a double-layer film, or a multilayer film.

The gate electrode 14 is an electrode provided on the gallium oxide semiconductor layer 12 via the gate insulating film 13, and its material is aluminum (Al), titanium (Ti), tungsten (W), platinum (Pt), Gold (Au), silver (Ag), ruthenium (Ru), rhodium (Rh), palladium (Pd), nickel (Ni), tin (Sn), zinc (Zn), polycrystalline silicon (poly-Si) To mention at least one selected from the group and alloys containing at least one selected from these groups, compounds such as nitrides, carbides, carbonitrides containing at least one selected from these groups can be done. A laminated film of these may also be used.
Examples of methods for depositing the electrode material include a vapor deposition method, a sputtering method, and a CVD method. Among these materials, the most suitable material is selected in consideration of work function, resistivity, heat resistance, contamination and workability in the manufacturing process steps for the gate electrode of MISFET.

Next, the manufacturing process of the semiconductor device according to the first embodiment will be described with reference to FIG. 5, which is a flow chart showing the manufacturing process, and FIGS.

First, a GaN substrate 11 containing an n-type dopant is prepared (step S11 in FIG. 5, FIG. 6(a)).
The GaN substrate 11 may be a substrate made of GaN, or a substrate made of GaN or an AlGaN substrate on which a semiconductor layer made of GaN single crystal is formed by an epitaxial growth method. When the GaN semiconductor layer is formed by an epitaxial formation method, the thickness of the GaN semiconductor layer can be set to 2 μm, for example.
The n-type dopant may be incorporated into the GaN substrate 11 when the GaN substrate 11 is formed, or may be incorporated by an ion implantation method or an impurity diffusion method after the GaN substrate 11 is manufactured. good.
At least one or more selected from the group of Si, Ge, and O can be used as the dopant. The amount of dopant is preferably 5×10 ¹⁵ /cm ³ or more and 5×10 ¹⁹ /cm ³ or less.

Next, a gallium oxide semiconductor layer 12 is formed on the main surface of the GaN substrate 11 (step S12, FIG. 6(b)).
Here, the gallium oxide semiconductor layer 12 is a film containing gallium oxide crystals having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, preferably a film having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. A film containing hexagonal, cubic, or hexagonal and cubic gallium oxide of 34 nm or less. The larger the amount of these gallium oxides, the better, and films made of these gallium oxides are preferred. As an example of a hexagonal crystal with a lattice constant of 0.28 nm or more and 0.34 nm or less on the a-axis, ε-Ga ₂ O ₃ is an example of a cubic crystal with a lattice constant of 0.28 nm or more and 0.34 nm or less on the a-axis. can include γ-Ga ₂ O ₃ .

In general, gallium oxide crystals have a β structure as a stable structure, and an ε structure and a γ structure as metastable structures. As a result, the semiconductor layer has few defects and trap sites, and has a smooth surface with little roughness. In addition, there is little change over time in the environment of normal use.

A first method for forming the gallium oxide semiconductor layer 12 is to expose the surface of the GaN substrate 11 to sulfuric acid, hydrogen peroxide, ammonia, hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, and potassium hydroxide. A method of oxidizing with at least one chemical solution.
As this oxidation method, SC1 (Standard Cleaning solution 1) (NH ₄ OH (ammonia water)-H ₂ O ₂ (hydrogen peroxide)-H ₂ O (water)), SC2 (Standard Cleaning solution 2) (HCl ( Hydrochloric acid)—H ₂ O ₂ —H ₂ O), SPM (Sulfuric acid hydrogen peroxide mixture) (H ₂ SO ₄ (sulfuric acid)—H ₂ O ₂ —H ₂ O), Buffered Hydrogen Fluoride: BHF) and other methods usually used for cleaning can be mentioned. A buffered hydrofluoric acid solution is generally known as a method for removing an oxide film, and the oxide film produced along with the removal is suitable as the gallium oxide semiconductor layer 12 .

According to this first method, the crystal plane of the gallium oxide semiconductor layer 12 (the crystal plane of gallium oxide) is aligned with the crystal plane of the surface of the GaN substrate 11 . For this reason, the first method is particularly preferable for forming a high-quality gallium oxide semiconductor layer 12 with few traps.

In this first method, light irradiation may be used together (Photo-Electrochemical Oxidation). For example, the GaN substrate 11 is immersed in a chemical solution of potassium hydroxide, phosphoric acid, glycol, or the like, and the surface of the GaN substrate 11 is exposed to ultraviolet (UV) light with a wavelength of 280 nm or more and less than 380 nm or far-sighted light (with a wavelength of 190 nm or more and less than 280 nm). DUV) may be applied to oxidize the surface of the GaN substrate 11 to form the gallium oxide semiconductor layer 12 .
In addition, the first method is characterized in that the heat load is less than that of the thermal oxidation treatment because the treatment is carried out at room temperature or at 280° C. or less even if heat treatment is added. When a large thermal load is applied, problems such as a change in dopant profile and generation of stress tend to occur.

A second method for forming the gallium oxide semiconductor layer 12 is to oxidize the surface of the GaN substrate 11 by plasma oxidation treatment in an atmosphere of 500° C. or less to form an oxide film. Alternatively, the surface of the GaN substrate 11 may be oxidized by ozone oxidation treatment in an atmosphere of 500° C. or less to form an oxide film.

A third method for forming the gallium oxide semiconductor layer 12 is to form an oxide film on the surface of the GaN substrate 11 in an atmosphere of 700° C. or less by electron beam evaporation and/or molecular beam epitaxy (MBE). It is a deposition method. Alternatively, an oxide film may be deposited on the surface of the GaN substrate 11 by chemical vapor deposition (CVD) in an atmosphere of 870° C. or less. Alternatively, an oxide film may be deposited on the surface of the GaN substrate 11 by Hydride Vapor Phase Epitaxy (HVPE) in an atmosphere of 700° C. or lower. Alternatively, an oxide film may be deposited on the surface of the GaN substrate 11 by atomic layer deposition (ALD) in an atmosphere of 500° C. or lower. Alternatively, gallium oxide may be deposited on the surface of the GaN substrate 11 by sputtering in an atmosphere of 500° C. or lower, and then annealing may be performed to deposit an oxide film.
At this time, it is preferable to implant an n-type dopant. At least one selected from the group consisting of Si, Ge, Sn, F, and Cl can be used as the n-type dopant. Examples of the dopant implantation method include a method of adding the dopant element during deposition, a method of ion implantation after deposition, a method of impurity diffusion, and a combination of these methods.

If the gallium oxide semiconductor layer 12 is formed under oxygen-rich conditions, ε-structured gallium oxide and/or γ-structured gallium oxide is formed.

A fourth method for forming the gallium oxide semiconductor layer 12 is to form gallium oxide on the surface of the GaN substrate 11 by heat treatment at 500° C. or higher and 750° C. or lower, and then etching to reduce the thickness of the gallium oxide to 10 nm. A method for forming the gallium oxide semiconductor layer 12 is described below.

After that, a gate insulating film 13a is formed (step S13, FIG. 6(c)).
Examples of the gate insulating film 13a include SiO _x , SiON, SOG, and polyimide. Examples of the forming method include a CVD method, a sputtering method, and a coating forming method. Here, the gate insulating film 13a may be a single layer film, a double layer film, or a multilayer film.

After that, the gate electrode 14 is formed on the gate insulating film 13a to obtain the semiconductor device 1010 in which the gate electrode is formed (step S14, FIG. 6(d)).
The gate electrode 14 is formed by depositing a gate material (metal) forming the gate electrode over the entire surface of the gate insulating film 13, forming a photoresist layer having a desired pattern by lithography, and using the photoresist layer as an etching mask. It is formed by etching the material. This method is characterized by high gate electrode processing accuracy.

The material of the gate electrode 14 is at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, poly-Si, and a group thereof. alloys containing at least one selected from, and compounds such as nitrides, carbides and carbonitrides containing at least one selected from these groups.
Here, the method of depositing the gate electrode 14 includes a sputtering method, a vapor deposition method using an electron beam, a vapor deposition method using heat, a CVD method, and the like.

After forming a photoresist layer for lift-off, a gate material is deposited by an electron beam vapor deposition method, a heat vapor deposition method, a sputtering method, a CVD method, or the like, and the photoresist layer is peeled off to form the gate electrode 14 . may be formed. This method is characterized in that the semiconductor device is not damaged by etching.
An interlayer film is formed on the gate insulating film 13 with openings corresponding to the locations where the gate electrodes 14 are to be formed. The gate electrode 14 may be formed by filling the opening of the interlayer film with an insulating material. This method is characterized in that even when an electrode material that is difficult to etch is used, it is possible to process the semiconductor device with sufficiently high precision, and the semiconductor device is less likely to be damaged by etching.

After that, the source electrode 16 and the drain electrode 17 are formed (step S15), and the semiconductor device 1011 is manufactured (step S16).

Methods for forming the source electrode 16 and the drain electrode 17 include the following methods.
First, after forming an insulating film 15a on the gate insulating film 13 and the gate electrode 14 (FIG. 7A), an insulating film having openings 18 for forming the source electrode 16 and the drain electrode 17 is formed by lithography and etching. The film 7 is used as a gate insulating film 13 (FIG. 7(b)). After that, a metal is formed in the opening to form a drain electrode 16 and a source electrode 17 to obtain a semiconductor device 1011 (FIG. 7(c)).

Here, examples of the insulating film 15a include a silicon oxide film, a TEOS (Tetra-ethoxy silane) film, an SOG (Spin on Glass) film, a phosphorus glass film, and a polyimide film.
Ohmic contact is preferable for the electrical contact between the source electrode 16 and the drain electrode 17 and the gallium oxide semiconductor layer 12 . The source electrode 16 and the drain electrode 17 may be a laminate of Ti (titanium) and Al (aluminum), but are not limited to this. As the source electrode 16 and the drain electrode 17, in addition to Al and Ti, at least one selected from the group consisting of W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly-Si. may be formed. In addition to these metals, alloys containing at least one selected from these groups, and compounds such as nitrides, carbides, and carbonitrides containing at least one selected from these groups may also be used.

Methods of depositing materials for the source electrode 16 and the drain electrode 17 include a sputtering method, a vapor deposition method using an electron beam, a vapor deposition method using heat, a CVD method, and the like. This method is characterized by high gate electrode processing accuracy.

Also, after forming a photoresist layer for lift-off, the source electrode 16 and drain electrode 17 materials are deposited by an electron beam vapor deposition method, a heat vapor deposition method, a sputtering method, a CVD method, or the like, and the photoresist layer is peeled off. By doing so, the source electrode 16 and the drain electrode 17 may be formed. This method is characterized in that the semiconductor device is not damaged by etching.

The semiconductor device (MISFET) 1011 according to the manufacturing method of the first embodiment is a semiconductor device with high mobility due to suppressed carrier scattering. In addition, the gallium oxide semiconductor layer 12 has a wide bandgap of 4.8 to 5.0 eV and excellent dielectric strength, and is suitable for high power applications. Furthermore, there are few defects in the semiconductor layer, and there are few trap levels.

<Embodiment 2>
In the second embodiment, a method of manufacturing a semiconductor device (MISFET) 1013 suitable for high frequency applications will be described with reference to FIG. will be explained.

First, similarly to Embodiment 1, a GaN substrate (gallium nitride crystal substrate) 11 having at least an n-type gallium nitride semiconductor layer on its surface is prepared (step S21 in FIG. 8, FIG. 9A). , the first gallium oxide semiconductor layer 12 is formed on the GaN substrate 11 (step S22, FIG. 9(b)).
As in Embodiment 1, the first gallium oxide semiconductor layer 12 contains an n-type dopant because it is formed by succeeding the n-type dopant in the oxidation formation layer of the GaN substrate 11, and the dopant is active. Therefore, it becomes an n-type semiconductor layer.
Here, at least one or more selected from the group consisting of Si, Ge, Sn, F, and Cl can be used as the n-type dopant.

The thickness of the first gallium oxide semiconductor layer 12 is preferably 2 nm or more and 30 nm or less, more preferably 5 nm or more and 30 nm or less. If the thickness exceeds 30 nm, the crystal tends to be disturbed and defects tend to occur. Also, if the thickness is less than 2 nm, the electrical characteristic function as a semiconductor layer of the MISFET tends to deteriorate.
When the main surface of the GaN substrate 11 is sufficiently smooth by polishing by CMP or the like, the roughness of the interface between the first gallium oxide semiconductor layer 12 and the GaN substrate 11 is sufficiently small, and the roughness is 0.2 nm (RSM). It becomes possible to

Next, an epitaxial Ga ₂ O ₃ film 21a (gallium oxide layer) is formed on the first gallium oxide semiconductor layer 12 by an epitaxial growth method such as HVPE (step S23, FIG. 9(c)). As an epitaxial formation method, the second and third methods described in the first embodiment may be used in addition to HVPE.
Here, the thickness of the epitaxial Ga ₂ O ₃ film 21a is preferably 3 nm or more and 200 nm or less. If the thickness is less than 3 nm, it becomes difficult to create a dopant concentration difference from the first gallium oxide semiconductor layer 12, as will be described later. If the thickness exceeds 200 nm, it is difficult to form a film with few defects. become difficult.

Thereafter, an n-type dopant is implanted into the epitaxial Ga ₂ O ₃ film 21a by ion implantation 22 or the like to change the Ga ₂ O ₃ film 21a into a doped Ga ₂ O ₃ film 21, which is the second gallium oxide semiconductor layer ( Step S24, FIG. 9(d)).
Here, at least one selected from the group consisting of Si, Ge, Sn, F, and Cl can be used as the implanted n-type dopant. This n-type dopant may be the same element as the dopant of the first gallium oxide semiconductor layer 12, or may be a different element.
The amount of dopant implanted into the epitaxial Ga ₂ O ₃ film 21 a is preferably different from the amount of dopant contained in the first gallium oxide semiconductor layer 12 .
Moreover, after implanting the dopant into the epitaxial Ga ₂ O ₃ film 21a, heat treatment is preferably performed to activate the dopant.

Thereafter, a rigid substrate 23 is formed on the doped Ga ₂ O ₃ film 21 (step S25, FIG. 10(a)). Examples of the method for forming the substrate 23 include a bonding method, a CVD method, a sputtering method, and the like.
Examples of the substrate 23 include Si substrates, GaAs substrates, GaN substrates, AlGaN substrates, InP substrates, sapphire substrates, glass substrates such as synthetic quartz glass, borosilicate glass, and soda lime glass, ceramic substrates such as alumina and silicon nitride, acrylic, Organic material substrates such as polystyrene (PS), polypropylene (PP), polyethylene terephthalate (PET) and polycarbonate (PC), and metal substrates such as aluminum, iron, stainless steel and copper can be used.

Subsequently, the GaN substrate 11 is removed (step S26, FIG. 10(b)). Examples of methods for removing the GaN substrate 11 include a polishing method such as CMP, a dry etching method, a wet etching method, and combinations thereof. During this removal, it is important not to roughen the exposed surface of the first gallium oxide semiconductor layer 12, so polishing or wet etching is preferably performed in the final stage of removal.

After that, a gate insulating film 13a is formed (step S27, FIG. 10(c)).
For example, SiO _x , SiON, SOG, and polyimide can be used for the gate insulating film 13a, as in the first embodiment. Examples of the forming method include a CVD method, a sputtering method, and a coating forming method. Here, the gate insulating film 13a may be a single layer film, a double layer film, or a multilayer film.

After that, a gate electrode 14 is formed on the gate insulating film 13a (step S28) to obtain a semiconductor device 1012 in which the gate electrode is formed (FIG. 10(d)).
The gate electrode 14 is formed by depositing a gate material (metal) forming the gate electrode over the entire surface of the gate insulating film 13, forming a photoresist layer having a desired pattern by lithography, and using the photoresist layer as an etching mask. It is formed by etching the material. This method is characterized by high gate electrode processing accuracy.

The material of the gate electrode 14 is at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, poly-Si, and a group thereof. alloys containing at least one selected from, and compounds such as nitrides, carbides and carbonitrides containing at least one selected from these groups.
Here, the method of depositing the gate electrode 14 includes a sputtering method, a vapor deposition method using an electron beam, a vapor deposition method using heat, a CVD method, and the like.

After forming a photoresist layer for lift-off, a gate material is deposited by an electron beam vapor deposition method, a heat vapor deposition method, a sputtering method, a CVD method, or the like, and the photoresist layer is peeled off to form the gate electrode 14 . may be formed. This method is characterized in that the semiconductor device is not damaged by etching.
An interlayer film is formed on the gate insulating film 13 with openings corresponding to the locations where the gate electrodes 14 are to be formed. The gate electrode 14 may be formed by filling the opening of the interlayer film with an insulating material. This method is characterized in that even when an electrode material that is difficult to etch is used, it is possible to process the semiconductor device with sufficiently high precision, and the semiconductor device is less likely to be damaged by etching.

After that, the source electrode 16 and the drain electrode 17 are formed (step S29), and the semiconductor device 1013 is manufactured.

Methods for forming the source electrode 16 and the drain electrode 17 include the following methods.
First, after forming an insulating film 15a on the gate insulating film 13 and the gate electrode 14 (FIG. 11(a)), an insulating film having openings 18 for forming the source electrode 16 and the drain electrode 17 is formed by lithography and etching. The film 7 is used as the gate insulating film 13 (FIG. 11(b)). After that, metal is formed in the opening to form the drain electrode 16 and the source electrode 17, thereby obtaining the semiconductor device 1013 (step S30, FIG. 11(c)).

Here, examples of the insulating film 15a include a silicon oxide film, a TEOS (Tetra-ethoxy silane) film, an SOG (Spin on Glass) film, a phosphorus glass film, and a polyimide film.
Ohmic contact is preferable for the electrical contact between the source electrode 16 and the drain electrode 17 and the first gallium oxide semiconductor layer 12 . The source electrode 16 and the drain electrode 17 may be a laminate of Ti (titanium) and Al (aluminum), but are not limited to this. As the source electrode 16 and the drain electrode 17, in addition to Al and Ti, at least one selected from the group consisting of W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly-Si. may be formed. In addition to these metals, alloys containing at least one selected from these groups, and compounds such as nitrides, carbides, and carbonitrides containing at least one selected from these groups may also be used.

Methods of depositing materials for the source electrode 16 and the drain electrode 17 include a sputtering method, a vapor deposition method using an electron beam, a vapor deposition method using heat, a CVD method, and the like. This method is characterized by high gate electrode processing accuracy.

Also, after forming a photoresist layer for lift-off, the source electrode 16 and drain electrode 17 materials are deposited by an electron beam vapor deposition method, a heat vapor deposition method, a sputtering method, a CVD method, or the like, and the photoresist layer is peeled off. By doing so, the source electrode 16 and the drain electrode 17 may be formed. This method is characterized in that the semiconductor device is not damaged by etching.

The semiconductor device (MISFET) 1013 according to the manufacturing method of the second embodiment has high smoothness at the interfaces of the semiconductor layers and little scattering of carriers, so that high mobility can be obtained. In particular, the interface of the first gallium oxide semiconductor layer 12, which is the semiconductor layer on the side of the gate electrode that mainly determines the carrier mobility characteristics, is extremely smooth and has little roughness, so high mobility can be obtained.
In addition, the first gallium oxide semiconductor layer 12, which is the semiconductor layer on the gate electrode side, has few defects and trap levels.
Furthermore, since the semiconductor layers of the semiconductor device 1013 are composed of the first gallium oxide semiconductor layer 12 and the doped Ga ₂ O ₃ film 21 which is the second gallium oxide semiconductor layer, the amount of dopant is varied in two stages in the thickness direction. It can be changed, and control of carrier movement and control of leakage current are facilitated.
In addition, the first gallium oxide semiconductor layer 12 and the second gallium oxide semiconductor layer 21 have a wide bandgap of 4.8 to 5.0 eV and an excellent dielectric breakdown voltage, and are therefore suitable for high power applications.
For these reasons, the semiconductor device 1013 of the second embodiment is suitable for high power applications and has high carrier mobility.

Examples of the present invention will be described below. Of course, the invention is not limited to this particular form, but the scope of the invention is defined by the appended claims.

(Example 1)
In Example 1, gallium oxide formed on a gallium nitride semiconductor substrate (GaN substrate) will be described.

First, a c-plane GaN (0001) substrate manufactured by the HVPE method was prepared, and the main surface of the GaN substrate was polished by CMP (Chemical Mechanical Polishing). The GaN substrate has a thickness of 330 μm, is free-standing, has a crystal dislocation density on the order of 10 ⁶ /cm ² and a carrier density of 1.4×10 ¹⁸ /cm ³ . Here, this GaN is a single crystal with a wurtzite structure.
Then, the GaN substrate was organically cleaned with acetone and ethanol in an ultrasonic bath, and then cleaned with a mixture of sulfuric acid and hydrogen peroxide at a volume ratio of 1:1. An oxide film was formed on the surface of the substrate.

Next, the state of the oxide film formed on the GaN (0001) substrate 1 after being left in a clean room at room temperature of 23° C. for one day was analyzed by cross-sectional TEM and FFT (Fast Fourier Transform) based on the data. investigated by analysis. FFT analysis examines the lattice match of the crystal. A JEM-ARM200F (manufactured by JEOL) was used as a cross-sectional TEM and observed at 200 kV.

FIG. 12 shows the results of cross-sectional observation under annular dark illumination. In the figure, (a) is a cross-sectional observation view in the [1-100] direction, and (b) is an image obtained by subjecting the cross-sectional TEM image of (a) to FFT signal analysis. In the figure, (c) is a cross-sectional observation view in the [1-210] direction, and (d) is an image obtained by subjecting the cross-sectional TEM image of (c) to FFT signal analysis. White lines in FIGS. 12(b) and (d) indicate diffraction patterns. When the white line is aligned, it means that the crystal lattice of the substrate and the crystal lattice of the film formed thereon are lattice-matched.
As a result of observation, the white lines were aligned, and the film formed on the GaN substrate matched the crystals of the GaN substrate in crystal lattice, and the crystal plane was aligned with the crystal plane of the GaN (0001) substrate. It was confirmed that
Here, the case where the film formed on the GaN substrate has a thickness of about 1 nm is exemplified. It has been confirmed that the plane is also aligned with the GaN (0001) substrate.
Next, slow ion scattering spectroscopy was performed to confirm that the film formed on the GaN substrate was gallium oxide with six-fold symmetry.

After that, the surface roughness of the gallium oxide film formed on the GaN substrate was measured by AFM (Atomic Force Microscope). Here, DNF L-trace (manufactured by SII) was used as the AFM, and an area of 1 μm×1 μm was measured.
The results are shown in FIG. It was confirmed that the surface roughness RMS (Root Mean Square) was as small as 0.087 nm.
For this reason, the gallium oxide semiconductor layer interface is extremely smooth, and carrier scattering there is small.

INDUSTRIAL APPLICABILITY As described above, the present invention provides a semiconductor device suitable for high-power devices, having a wide bandgap, excellent withstand voltage, and high carrier mobility, and a manufacturing method thereof.
Semiconductor devices with high withstand voltage and high carrier mobility open the way to high-frequency devices and logic devices under high power, and are expected to greatly contribute to the development of industry.

11: GaN substrate 12: semiconductor layer (first gallium oxide semiconductor layer)
13: Gate insulating film (insulator layer)
13a: Gate insulating film (insulator layer)
14: Gate electrode 15: Insulating film 15a: Insulating film 16: Source electrode 17: Drain electrode 18: Opening 21a: Epitaxial Ga ₂ O ₃ film (gallium oxide layer)
21: Doped Ga ₂ O ₃ film (second gallium oxide semiconductor layer)
22: Ion implantation 23: Substrate 1010: Semiconductor device 1011: Semiconductor device 1012: Semiconductor device 1013: Semiconductor device 2001: Oxygen atom (O)
2002: Gallium Atom (Ga)
2011: crystal lattice 2021: lattice constant a ₁
2022: lattice constant a ₂
2023: lattice constant a ₃

Claims (12)

The semiconductor device includes a semiconductor layer containing gallium oxide crystals, a gate electrode, and an insulator layer provided between the semiconductor layer and the gate electrode, wherein the gallium oxide crystals have a lattice constant of 0.0 on the a-axis. 28 nm or more and 0.34 nm or less A method for manufacturing a semiconductor device,
a substrate preparation step of preparing a gallium nitride crystal substrate containing a dopant;
a gallium oxide semiconductor layer forming step of forming a gallium oxide semiconductor layer on the gallium nitride crystal substrate;
an insulator layer forming step of forming an insulator layer on the gallium oxide semiconductor layer;
A method of manufacturing a semiconductor device, comprising a gate electrode forming step of forming a gate electrode on the insulator layer. The semiconductor device includes a semiconductor layer containing gallium oxide crystals, a gate electrode, and an insulating layer provided between the semiconductor layer and the gate electrode, wherein the gallium oxide crystals have a lattice constant of 0.00 in the a-axis. 28 nm or more and 0.34 nm or less A method for manufacturing a semiconductor device,
a substrate preparation step of preparing a gallium nitride crystal substrate containing a dopant;
a first gallium oxide semiconductor layer forming step of forming a first gallium oxide semiconductor layer on the gallium nitride crystal substrate;
a gallium oxide forming step of epitaxially forming a gallium oxide layer on the first gallium oxide semiconductor layer;
a dopant implantation step of implanting a dopant into the gallium oxide to form a second gallium oxide semiconductor layer;
a substrate forming step of depositing and forming a rigid substrate on the second gallium oxide semiconductor layer;
a gallium nitride crystal substrate removing step of removing the gallium nitride crystal substrate;
an insulator layer forming step of forming an insulator layer on the first gallium oxide semiconductor layer;
A method of manufacturing a semiconductor device, comprising a gate electrode forming step of forming a gate electrode on the insulator layer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said gallium nitride crystal substrate is a single crystal of wurtzite structure. In the step of forming the gallium oxide semiconductor layer and the first gallium oxide semiconductor layer, the gallium nitride crystal substrate is treated with sulfuric acid, hydrogen peroxide solution, ammonia, hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, and potassium hydroxide. 4. The method of manufacturing a semiconductor device according to any one of claims 1 to 3 , comprising a step of surface treatment using at least one selected from. 3. The step of forming the gallium oxide semiconductor layer and the first gallium oxide semiconductor layer includes the step of subjecting the gallium nitride crystal substrate to at least one of plasma oxidation and ozone oxidation at 500° C. or lower. 4. The method of manufacturing a semiconductor device according to any one of 1 to 3 . The step of forming the gallium oxide semiconductor layer and the first gallium oxide semiconductor layer includes, on the gallium nitride crystal substrate, electron beam evaporation at 700° C. or lower, MBE at 700° C. or lower, CVD at 870° C. or lower, and CVD at 700° C. or lower. 4. The semiconductor device of claim 1 , comprising forming the oxide using at least one method selected from the group consisting of HVPE, ALD at 400[deg.] C. or below, and sputtering at 500[deg.] C. or below. manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor layer has a surface roughness of 0 nm or more and 0.5 nm or less. 7. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor layer has a surface roughness of 0 nm or more and 0.2 nm or less. 9. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor layer is an n-type semiconductor. 10. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor layer contains at least one dopant selected from the group consisting of Si, Ge, Sn, F and Cl. The insulator layer is an oxide, nitride, or oxynitride of at least one element selected from the group of elements consisting of Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and rare earth elements. 11. The method of manufacturing a semiconductor device according to claim 1 , comprising: 12. The gate electrode comprises at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn and poly-Si. 2. A method of manufacturing a semiconductor device according to any one of 1.

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