JP2006253605A - Semiconductor substrate and semiconductor device, and manufacturing methods therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a semiconductor layer of good quality on a porous layer or a porous region. <P>SOLUTION: A manufacturing method for a semiconductor substrate includes steps of forming a 1st semiconductor layer 12 including a layer formed of a 2nd material having a grating constant different from the grating constant of a substrate 11 on the substrate 11 made of a 1st material, forming a porous layer 12" by making porous at least the surface of the 1st semiconductor layer 11, and forming a 2nd semiconductor layer 14 of the 1st material on the porous layer 12". <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor substrate having a plurality of layers, a semiconductor device, and a manufacturing method thereof.

  A technique of epitaxially growing a material different from the substrate on a single crystal substrate is known as a heteroepitaxial technique. In general, if the crystal structure of the substrate and the film to be grown thereon are similar and the lattice constants are close, heteroepitaxial growth on the substrate grows two-dimensionally. However, the larger the difference in lattice constant, the more the mode is such that a three-dimensional island is formed and grown from the beginning of heteroepitaxial growth.

  It is the energy stability of the system that dominates the change in the shape of the epitaxially grown film. Assuming that σs, σi, and σf are the substrate surface, substrate / growth layer interface, and growth layer energy (strain energy + surface energy + internal energy), if σs> σi + σf, the substrate is more adsorbed than the substrate is exposed. It means that it is more stable to cover the two-dimensional layer growth.

  On the other hand, if σs <σi + σf, it is more stable to expose the substrate and perform three-dimensional growth, and a three-dimensional island appears from the beginning of growth. In the three-dimensional layer growth mode, as the epitaxial growth proceeds, the three-dimensional islands gradually increase, and eventually the islands merge to generate dislocations inside the island and in the vicinity of the heterointerface. Therefore, in order to grow a crystal having no defect, it is generally important not to form a three-dimensional island.

In Patent Document 1, a silicon layer is epitaxially grown on a silicon substrate, a porous layer is formed by anodizing the silicon layer, a semiconductor thin film is formed on the porous layer, and then the semiconductor thin film is formed on the substrate. A technique for separating from the above is disclosed.
JP-A-11-195562

  When a semiconductor layer having a lattice constant different from that of the substrate is formed on the substrate, the lattice constant of the semiconductor layer is less than the critical thickness that causes defects. By following the above, distortion may occur in the semiconductor layer, but no defect is generated. However, defects occur when the thickness of the semiconductor layer to be grown exceeds the critical thickness.

  For example, in the manufacture of a strained silicon substrate, a technique for forming a semiconductor layer as a strain inducing layer (for example, a SiGe layer) for imparting strain on the surface silicon layer on the silicon substrate with low defects is important. If a porous layer is formed in the middle of forming a strain inducing layer on a silicon substrate, and further a strain inducing layer is formed thereon, the porous layer functions as a defect propagation block layer, and defects that may occur on the substrate side Propagation to the surface side can be prevented.

  However, when the strain-inducing layer is regrown on the defect propagation blocking layer to increase the thickness of the strain-inducing layer, the defect blocking layer is caused by the difference between the lattice constant of the substrate and the lattice constant of the strain-inducing layer to be regrown. A three-dimensional island is generated in the vicinity of the upper surface of the substrate, and defects formed thereby can propagate into the strain-inducing layer.

  The present invention has been made on the basis of recognition of the above-described problems. For example, an object of the present invention is to form a high-quality semiconductor layer on a porous layer or a porous region.

  The method for manufacturing a semiconductor substrate according to the first aspect of the present invention includes a first semiconductor layer including a layer made of a second material having a lattice constant different from the lattice constant of the substrate on the substrate made of the first material. Forming a porous layer by making the surface of at least the first semiconductor layer porous, and forming a second semiconductor layer made of the first material on the porous layer And a process.

  According to a preferred embodiment of the present invention, the layer made of the second material is preferably thinner than a film thickness at which a defect is generated due to a difference between a lattice constant of the substrate and a lattice constant of the second material. .

  According to a preferred embodiment of the present invention, the manufacturing method may further include forming a third semiconductor layer having a lattice constant different from that of the substrate on the second semiconductor layer.

  According to a preferred embodiment of the present invention, the manufacturing method may further include forming a fourth semiconductor layer having a lattice constant different from the lattice constant of the third semiconductor layer on the third semiconductor layer.

  According to a preferred embodiment of the present invention, the third semiconductor layer is, for example, a compound semiconductor layer.

  According to a preferred embodiment of the present invention, for example, the third semiconductor layer is a compound semiconductor layer, and the fourth semiconductor layer is a silicon layer.

  According to a preferred embodiment of the present invention, for example, the substrate is a silicon substrate, and the first semiconductor layer is a layer containing silicon and germanium, a layer containing gallium and arsenic, a layer containing gallium and phosphorus, and Any layer selected from the group consisting of layers containing gallium and nitrogen.

  A manufacturing method of a semiconductor device according to the second aspect of the present invention includes a step of forming a transistor on a semiconductor substrate manufactured by the above manufacturing method, for example, a fourth semiconductor layer thereof.

  A semiconductor substrate according to a third aspect of the present invention includes a substrate made of a first material, and a layer made of a second material disposed on the substrate and having a lattice constant different from the lattice constant of the substrate. A first semiconductor layer having a porous region that is configured and porous at least on a surface thereof, and a second semiconductor layer that is disposed on the porous region and is configured of the first material. .

  A semiconductor device according to a fourth aspect of the present invention includes the semiconductor substrate described above and a transistor formed on the semiconductor substrate, for example, a fourth semiconductor layer thereof.

  According to the present invention, for example, a high-quality semiconductor layer can be formed on a porous layer or a porous region.

  Hereinafter, preferred embodiments of the present invention will be described.

  In the method for manufacturing a semiconductor substrate according to a preferred embodiment of the present invention, silicon germanium (SiGe) or the like having a lattice constant different from that of the substrate is formed on a substrate made of a first material such as silicon (Si). A first semiconductor layer including a layer made of the second material is formed. The layer made of the second material can be formed by a heteroepitaxial growth method. Here, the layer made of the second material is preferably formed thinner than the film thickness (critical film thickness) at which defects due to the difference between the lattice constant of the substrate and the lattice constant of the first semiconductor layer occur.

  Next, at least the surface of the first semiconductor layer is made porous by anodizing to form a porous layer, and then a second semiconductor layer is formed from the first material on the porous layer. Thereby, the pores of the porous layer are sealed.

  Next, a third semiconductor layer is formed on the second semiconductor layer with silicon germanium (SiGe) having a lattice constant different from that of the substrate. The third semiconductor layer can be formed by heteroepitaxial growth. By forming the second semiconductor layer from the same first material as the substrate, lattice mismatch between the substrate and the second semiconductor layer is suppressed, and the second semiconductor layer is grown two-dimensionally on the porous layer. be able to. Further, the porous layer functions as a defect propagation block layer, and a third semiconductor layer can be formed on the second semiconductor layer with a low defect and sufficiently thick (thickness corresponding to complete relaxation; for example, 2 μm).

  Next, a fourth semiconductor layer such as a silicon layer having a lattice constant different from that of the third semiconductor layer is formed on the third semiconductor layer. In the fourth semiconductor layer, strain is induced by the third semiconductor layer due to a difference in lattice constant, and the fourth semiconductor layer can be used as a strained semiconductor layer.

  When the substrate is a silicon substrate, the first semiconductor layer includes a layer containing silicon (Si) and germanium (Ge), a layer containing gallium (Ga) and arsenic (As), gallium (Ga) and phosphorus (P). It is preferably any layer selected from the group consisting of a layer including and a layer including gallium (Ga) and nitrogen (N).

[First Embodiment]
A method of manufacturing a semiconductor substrate according to the first embodiment of the present invention will be described with reference to FIGS.

First, in the process shown in FIG. 1, a SiGe layer 12 as a first semiconductor layer made of silicon (Si) and germanium (Ge) as a second material is formed on a substrate 11 made of silicon (Si) as a first material. (SiGe: for example, Ge = 30%) is heteroepitaxially grown by a CVD method using lamp heating. This heteroepitaxial growth step can be performed using, for example, H ₂ as the carrier gas, 100% SiH ₄ as the first source gas, and 10% GeH ₄ as the second source gas.

The flow rate of H ₂ as the carrier gas is preferably 20 to 40 liters / minute, and typically 22 liters / minute. The flow rate of 100% SiH ₄ as the first source gas is preferably 20 to 100 sccm, and typically 50 sccm. The flow rate of 10% GeH ₄ as the second source gas is preferably 20 to 100 sccm, and typically 90 sccm.

  In this heteroepitaxial growth process, the chamber pressure is preferably 10 to 100 Torr, typically 30 Torr, the temperature is preferably 500 to 700 ° C., and typically 550 ° C. The rate is preferably 10 to 40 nm / min, typically 25 nm / min.

Further, it is preferable to dope impurities such as boron in the heteroepitaxial growth process. Boron doping can be done, for example, by supplying 0.1% B ₂ H ₆ / H ₂ to the chamber. Flow rate of _{0.1% B 2 H 6 / H} 2 is preferably 10-100 sccm, is typically 30 sccm. Doping impurities such as boron into the SiGe layer 12 increases the conductivity of the SiGe layer 12. Increasing the conductivity of the SiGe layer 12 facilitates making the SiGe layer 12 porous in subsequent anodization.

Subsequently, in the step shown in FIG. 2, at least the surface of the SiGe layer 12 is made porous by anodization to form a porous layer 12 ″. Typically, the anodization is performed in a conversion tank having a platinum electrode pair. A solution containing hydrogen fluoride (HF) is placed, the substrate 13 is placed between the electrode pairs, and an electric current is passed between the electrode pairs. % HF, 9.2% IPA and water can be used, current density = 1 mA / cm ² , treatment time = 30 seconds.

  By this anodization, a porous layer 12 ″ having a thickness of about 30 nm is formed. Here, in forming the porous layer, only a part of the surface side of the SiGe 12 may be made porous, or the entire SiGe 12 may be formed. The substrate may be made porous, or the substrate 11 may be made porous.

3, a plurality of semiconductor layers are formed on the porous layer 12 ″. First, a silicon layer made of the same material as the substrate 11 is formed on the porous layer 12 ″ as a second semiconductor layer. 14 is grown epitaxially. The silicon layer 14 seals the pores of the porous layer 12 ″. Accordingly, the silicon layer 14 functions as a hole sealing layer. The silicon layer (hole sealing layer) 14 is, for example, a source gas. 100% SiH ₄ can be used, where the flow rate of SiH ₄ is preferably 100-700 sccm, typically 500 sccm, and in forming the silicon layer 14, the chamber pressure is preferably Is 10-100 Torr, typically 30 Torr, the temperature is preferably 500-700 ° C., typically 620 ° C., and the growth rate is preferably 10-40 nm / min, Typically 15 nm / min.

When a strained silicon substrate is manufactured, a thick SiGe layer 15 (for example, Ge = 20%, 2 μm) is heteroepitaxially grown on the silicon layer 14 as a third semiconductor layer. This heteroepitaxial growth step can be performed using, for example, H ₂ as the carrier gas, 100% SiH ₄ as the first source gas, and 10% GeH ₄ as the second source gas.

The flow rate of H ₂ as the carrier gas is preferably 20 to 40 liters / minute, and typically 22 liters / minute. The flow rate of 100% SiH ₄ as the first source gas is preferably 20 to 100 sccm, and typically 50 sccm. The flow rate of 10% GeH ₄ as the second source gas is preferably 20 to 100 sccm, and typically 55 sccm.

  In this heteroepitaxial growth process, the chamber pressure is preferably 10 to 100 Torr, typically 30 Torr, the temperature is preferably 500 to 700 ° C., and typically 620 ° C. The rate is preferably 20-100 nm / min, typically 50 nm / min.

  Subsequently, a strained silicon substrate is obtained by epitaxially growing a silicon layer 16 as a fourth semiconductor layer on the SiGe layer 15. The silicon layer 16 and the SiGe layer 15 have different lattice constants, which causes distortion in the silicon layer 16. The growth conditions of the silicon layer 16 can be the same as the growth conditions of the silicon layer 14 as the hole sealing layer.

[Second Embodiment]
A method for manufacturing a semiconductor substrate according to a second embodiment of the present invention will be described with reference to FIGS.

First, in the process shown in FIG. 4, a first semiconductor layer including a SiGe layer 22 and a Si layer 23 is formed on a substrate 21 made of silicon (Si) as a first material. First, a SiGe layer 22 (SiGe: for example, Ge = 30%) made of silicon (Si) and germanium (Ge) as the second material is heteroepitaxially grown on the silicon substrate 21 by a CVD method using lamp heating. This condition is preferably as follows. This heteroepitaxial growth step can be performed using, for example, H ₂ as the carrier gas, 100% SiH ₄ as the first source gas, and 10% GeH ₄ as the second source gas.

The flow rate of H ₂ as the carrier gas is preferably 20 to 40 liters / minute, and typically 22 liters / minute. The flow rate of 100% SiH ₄ as the first source gas is preferably 20 to 100 sccm, and typically 50 sccm. The flow rate of 10% GeH ₄ as the second source gas is preferably 20 to 100 sccm, and typically 90 sccm.

  In this heteroepitaxial growth process, the chamber pressure is preferably 10 to 100 Torr, typically 30 Torr, the temperature is preferably 500 to 700 ° C., and typically 550 ° C. The rate is preferably 10 to 40 nm / min, typically 25 nm / min.

Further, it is preferable to dope impurities such as boron in the heteroepitaxial growth process. Boron doping can be done, for example, by supplying 0.1% B ₂ H ₆ / H ₂ to the chamber. Flow rate of _{0.1% B 2 H 6 / H} 2 is preferably 10-100 sccm, typically at 30 sccm. By doping impurities such as boron into the SiGe layer 22, the conductivity of the SiGe layer 22 is increased. Increasing the conductivity of the SiGe layer 22 facilitates making the SiGe layer 22 porous in subsequent anodization.

Subsequently, the Si layer 23 is heteroepitaxially grown on the SiGe layer 22. When the silicon layer 23 is formed on the outermost surface, structural change due to heat can be suppressed, and a process at a higher temperature becomes possible. This heteroepitaxial growth process can be performed using, for example, 100% SiH ₄ as a source gas. The flow rate of 100% SiH ₄ is preferably 100 to 700 sccm, and typically 500 sccm. In this heteroepitaxial growth process, the chamber pressure is preferably 10 to 100 Torr, typically 30 Torr, the temperature is preferably 500 to 700 ° C., and typically 550 ° C. The rate is preferably 1-10 nm / min, typically 2 nm / min.

Subsequently, in the step shown in FIG. 5, at least the surface side of the first semiconductor layer is made porous by anodization to form the porous layers 22 ″ and 23 ′. A solution containing hydrogen fluoride (HF) is placed in the chemical conversion tank, and the substrate 24 is disposed between the electrode pairs, and an electric current is allowed to flow between the electrode pairs. Using a mixture of 42.5% HF, 9.2% IPA and water, current density = 1 mA / cm ² , treatment time = 30 seconds.

  By this anodization, a porous of about 30 nm is formed. Here, in the formation of the porous layer, only a part of the surface side of the silicon layer 23 may be made porous, the whole silicon layer 23 may be made porous, or the SiGe layer 22 may be made porous. Part or the whole may be made porous, and further, the substrate 21 may be made porous.

Subsequently, in the step shown in FIG. 6, a plurality of semiconductor layers are formed on the porous layer 23 ′. First, a silicon layer 24 made of the same material as the substrate 21 is epitaxially grown as a second semiconductor layer on the porous layer 23 ′. The holes of the porous layer 22 ″ are sealed by the silicon layer 24. Accordingly, the silicon layer 24 functions as a hole sealing layer. The silicon layer (hole sealing layer) 24 is, for example, a source gas. 100% SiH ₄ can be used, where the flow rate of SiH ₄ is preferably 100-700 sccm, typically 500 sccm, and in forming the silicon layer 14, the chamber pressure is preferably Is 10-100 Torr, typically 30 Torr, the temperature is preferably 500-700 ° C., typically 620 ° C., and the growth rate is preferably 10-40 nm / min, Typically 15 nm / min.

  FIG. 7 (a) is an SEM image of a substrate in which the pores of the porous layer 23 ′ are sealed with SiGe as seen obliquely (comparative example), and FIG. 7 (b) is porous according to this embodiment. It is the SEM image which looked at the board | substrate after sealing the hole of layer 23 'with Si (Si layer 24) from the diagonal direction. When the porous layer 23 ′ is sealed with a SiGe sealing layer made of a material different from that of the silicon substrate 21 as the base substrate, the lattice mismatch between the silicon substrate 21 and the SiGe sealing layer causes the FIG. As shown in a), the SiGe sealing layer grows three-dimensionally. On the other hand, when the porous layer 23 ′ is sealed with the Si layer 24, which is the same material as the silicon substrate 21, no lattice mismatch occurs between the silicon substrate 21 and the Si layer 24. ), The Si sealing layer 24 grows two-dimensionally.

When a strained silicon substrate is manufactured, a thick SiGe layer 25 (for example, Ge = 20%, 2 μm) is heteroepitaxially grown as a third semiconductor layer on the silicon layer 24. This heteroepitaxial growth step can be performed using, for example, H ₂ as the carrier gas, 100% SiH ₄ as the first source gas, and 10% GeH ₄ as the second source gas.

The flow rate of H ₂ as the carrier gas is preferably 20 to 40 liters / minute, and typically 22 liters / minute. The flow rate of 100% SiH ₄ as the first source gas is preferably 20 to 100 sccm, and typically 50 sccm. The flow rate of 10% GeH ₄ as the second source gas is preferably 20 to 100 sccm, and typically 55 sccm.

  In this heteroepitaxial growth process, the chamber pressure is preferably 10 to 100 Torr, typically 30 Torr, the temperature is preferably 500 to 700 ° C., and typically 620 ° C. The rate is preferably 20-100 nm / min, typically 50 nm / min.

  Subsequently, a strained silicon substrate is obtained by epitaxially growing a silicon layer 26 as a fourth semiconductor layer on the SiGe layer 25. The silicon layer 12 and the SiGe layer 25 have different lattice constants, which causes distortion in the silicon layer 26. The growth conditions of the silicon layer 26 can be the same as the growth conditions of the silicon layer 24 as the hole sealing layer.

[Application example (semiconductor device)]
Hereinafter, as an application example of the semiconductor substrate that can be manufactured by the manufacturing method represented by the first embodiment and the second embodiment, a semiconductor device using the semiconductor substrate that can be manufactured by the manufacturing method of the first embodiment and a manufacturing method thereof Will be explained.

  8 to 11 are views schematically showing a method of manufacturing a semiconductor device using a semiconductor substrate that can be manufactured by the manufacturing method of the first embodiment. First, in the process shown in FIG. 8, the element isolation region 54 is formed in the region to be the inactive region of the semiconductor layer 16, and the gate insulating film 56 is formed in the region to be the active region of the semiconductor layer 16.

  Examples of the material of the gate insulating film 56 include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, titanium oxide, scandium oxide, yttrium oxide, gadolinium oxide, lanthanum oxide, zirconium oxide, and the like. The glass mixture is suitable. The gate insulating film 56 can be formed, for example, by oxidizing the surface of the semiconductor layer 16 or depositing a corresponding material on the surface of the semiconductor layer 16 by a CVD method or a PVD method.

  Next, a gate electrode 55 is formed on the gate insulating film 56. The gate electrode 55 is made of, for example, polycrystalline silicon doped with a P-type or N-type impurity, a metal such as tungsten, molybdenum, titanium, tantalum, aluminum, or copper, or an alloy containing at least one of these, molybdenum silicide, It can be composed of a metal silicide such as tungsten silicide or cobalt silicide, or a metal nitride such as titanium nitride, tungsten nitride, or tantalum nitride.

  The gate insulating film 56 may be formed by stacking a plurality of layers made of different materials, such as a polycide gate. The gate electrode 55 may be formed by, for example, a method called salicide (self-aligned silicide), a method called a damascene gate process, or another method. The structure shown in FIG. 8 is obtained through the above steps.

  Next, in the step shown in FIG. 9, relatively low concentration source / drain regions 58 are formed by introducing N-type impurities such as phosphorus, arsenic, and antimony or P-type impurities such as boron into the semiconductor layer 16. Impurities can be introduced, for example, by ion implantation and heat treatment.

  Next, after forming an insulating film so as to cover the gate electrode 55, the insulating film is etched back, thereby forming the sidewall 59 on the side portion of the gate electrode 59.

  Next, impurities of the same conductivity type as described above are again introduced into the semiconductor layer 16 to form relatively high concentration source / drain regions 57. The structure shown in FIG. 9 is obtained through the above steps.

  Next, in the step shown in FIG. 10, a metal silicide layer 60 is formed on the upper surface of the gate electrode 55 and the upper surfaces of the source and drain regions 57. As a material of the metal silicide layer 60, for example, nickel silicide, titanium silicide, cobalt silicide, molybdenum silicide, tungsten silicide and the like are suitable. These silicides are formed by depositing a metal so as to cover the upper surface of the gate electrode 55 and the upper surfaces of the source and drain regions 57, and then performing a heat treatment to react the metal with the underlying silicon. The unreacted portion of the metal can be removed with an etchant such as sulfuric acid. Here, if necessary, the surface of the silicide layer may be nitrided. The structure shown in FIG. 10 is obtained through the above steps.

  Next, in the step shown in FIG. 11, an insulating film 61 is formed so as to cover the upper surface of the silicided gate electrode and the upper surfaces of the source and drain regions. As a material of the insulating film 61, silicon oxide containing phosphorus and / or boron is preferable.

  Next, if necessary, a contact hole is formed in the insulating film 61 after planarizing the surface by CMP (chemical mechanical polishing). When a photolithographic technique using a KrF excimer laser, ArF excimer laser, F2 excimer laser, electron beam, X-ray or the like is applied, a rectangular contact hole with a side of less than 0.25 microns or a diameter of less than 0.25 microns A circular contact hole can be formed.

  Next, a conductor is filled in the contact hole. As a method for filling the conductor, after forming a film of a refractory metal serving as the barrier metal 62 or a nitride thereof on the inner wall of the contact hole, the conductor 63 such as tungsten alloy, aluminum, aluminum alloy, copper, or copper alloy is formed. A deposition method using a CVD method, a PVD (physical vapor deposition) method, a plating method, or the like is preferable. Here, the conductor deposited higher than the upper surface of the insulating film 61 may be removed by an etch back method or a CMP method. Prior to filling the conductor, the surface of the silicide layer in the source and drain regions exposed at the bottom of the contact hole may be nitrided. Through the above steps, a transistor (here, an insulated gate transistor) such as a field effect transistor (FET) can be formed on the substrate, and a semiconductor device having a transistor having the structure shown in FIG. 11 can be obtained.

  According to this embodiment, since the carrier mobility of the semiconductor layer can be improved by using the strained silicon layer 16, a device such as a transistor formed in the semiconductor layer can be driven at high speed.

  Even when a semiconductor substrate that can be manufactured by the manufacturing method of the second embodiment is used, a semiconductor device can be manufactured by the same process as described above.

  As described above, the semiconductor substrate that can be manufactured by the manufacturing method represented by the first and second embodiments is useful as a substrate for forming a circuit element such as an insulated gate transistor in the strained semiconductor layer.

It is a figure which shows typically the manufacturing method of the semiconductor substrate of 1st Embodiment. It is a figure which shows typically the manufacturing method of the semiconductor substrate of 1st Embodiment. It is a figure which shows typically the manufacturing method of the semiconductor substrate of 1st Embodiment. It is a figure which shows typically the manufacturing method of the semiconductor substrate of 2nd Embodiment. It is a figure which shows typically the manufacturing method of the semiconductor substrate of 2nd Embodiment. It is a figure which shows typically the manufacturing method of the semiconductor substrate of 2nd Embodiment. It is a SEM image of the board | substrate after sealing the hole of a porous layer. It is a figure which shows typically a semiconductor device and its manufacturing method. It is a figure which shows typically a semiconductor device and its manufacturing method. It is a figure which shows typically a semiconductor device and its manufacturing method. It is a figure which shows typically a semiconductor device and its manufacturing method.

Explanation of symbols

11 Silicon substrate 12 First semiconductor layer (heteroepitaxial growth layer)
12 'first semiconductor layer (heteroepitaxial growth layer)
12 "porous layer 14 second semiconductor layer (silicon layer)
15 Third semiconductor layer (heteroepitaxial growth layer)
16 Fourth semiconductor layer (strained silicon layer)
21 Silicon substrate 22 First semiconductor layer (heteroepitaxial growth layer)
22 'first layer of first semiconductor layer (heteroepitaxial growth layer)
22 "second layer of the first semiconductor layer (silicon layer)
23 'porous silicon layer 24 second semiconductor layer (silicon layer)
25 Third semiconductor layer (heteroepitaxial growth layer)
26 Fourth semiconductor layer (strained silicon layer)

Claims (10)

A method for manufacturing a semiconductor substrate, comprising:
Forming a first semiconductor layer including a layer made of a second material having a lattice constant different from that of the substrate on a substrate made of the first material;
Forming a porous layer by making the surface of at least the first semiconductor layer porous; and
Forming a second semiconductor layer composed of the first material on the porous layer;
A method for manufacturing a semiconductor substrate, comprising:   2. The semiconductor substrate manufacturing method according to claim 1, wherein the layer made of the second material is thinner than a film thickness at which a defect is generated due to a difference between a lattice constant of the substrate and a lattice constant of the second material. Method.   The method for manufacturing a semiconductor substrate according to claim 1, further comprising a step of forming a third semiconductor layer having a lattice constant different from the lattice constant of the substrate on the second semiconductor layer.   4. The method of manufacturing a semiconductor substrate according to claim 3, further comprising forming a fourth semiconductor layer having a lattice constant different from the lattice constant of the third semiconductor layer on the third semiconductor layer.   The method for manufacturing a semiconductor substrate according to claim 3, wherein the third semiconductor layer is a compound semiconductor layer. The third semiconductor layer is a compound semiconductor layer;
The fourth semiconductor layer is a silicon layer;
The method of manufacturing a semiconductor substrate according to claim 4. The substrate is a silicon substrate;
The first semiconductor layer is any layer selected from the group consisting of a layer containing silicon and germanium, a layer containing gallium and arsenic, a layer containing gallium and phosphorus, and a layer containing gallium and nitrogen;
The second semiconductor layer is a silicon layer;
The method for manufacturing a semiconductor substrate according to claim 1, wherein the method is a semiconductor substrate manufacturing method. A method for manufacturing a semiconductor device, comprising:
Forming a transistor on a semiconductor substrate manufactured by the manufacturing method according to claim 1;
A method of manufacturing a semiconductor substrate. A semiconductor substrate,
A substrate composed of a first material;
A first semiconductor layer having a porous region disposed on the substrate and including a layer made of a second material having a lattice constant different from the lattice constant of the substrate and having a porous region at least on the surface;
A second semiconductor layer disposed on the porous region and made of the first material;
A semiconductor substrate comprising: A semiconductor device,
A semiconductor substrate according to claim 9;
A transistor formed on the semiconductor substrate;
A semiconductor device comprising: