JP5396911B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  In recent years, a compound semiconductor device having a high withstand voltage and a high output has been actively developed using characteristics of a nitride compound semiconductor such as a high saturation electron velocity and a wide band gap. For example, field effect transistors such as a high electron mobility transistor (HEMT) have been developed. Among these, GaN-based HEMTs that include an AlGaN layer as an electron supply layer have attracted attention. In such a GaN-based HEMT, a strain caused by the difference in lattice constant between AlGaN and GaN is generated in the AlGaN layer, piezo-polarization occurs along with this strain, and a high-concentration two-dimensional electron gas is formed in the GaN under the AlGaN layer. Occurs near the top surface of the layer. For this reason, a high output can be obtained.

However, the compound semiconductor device has a problem that contact resistance between the metal constituting the electrode and the compound semiconductor is high. In particular, in the GaN-based HEMT as described above, an AlGaN layer is interposed between the GaN layer and the metal electrode, and the band gap of AlGaN is wider than that of GaN. For this reason, the AlGaN layer functions as a barrier, and the contact resistance is larger than 10 ⁻⁵ Ωcm ⁻² .

According to the inversion HEMT in which the surface of the electron transit layer and the electron supply layer has an N polarity (000-1) plane, the contact resistance can be reduced to 10 ⁻⁶ Ωcm ⁻² units. This is because the direction of piezo polarization and spontaneous polarization in the (000-1) plane is opposite to that in the (0001) plane, and a two-dimensional electron gas is generated near the lower surface of the GaN layer located on the AlGaN layer. is there. That is, it is not affected by the band gap of the AlGaN layer, and the distance between the two-dimensional electron gas and the metal electrode is reduced, so that the contact resistance is reduced.

  However, residual carriers are easily introduced into the GaN layer and the AlGaN layer whose surface is the (000-1) plane. For this reason, even if the contact resistance can be reduced, it is difficult to obtain a high output.

  Further, in the inverted HEMT, the gate leakage current becomes two orders of magnitude higher than in the HEMT in which a two-dimensional electron gas is generated under the AlGaN layer. This is because in the HEMT in which a two-dimensional electron gas is generated under the AlGaN layer, the AlGaN layer functions as a Schottky barrier, but in the inverted HEMT, the GaN layer in which the two-dimensional electron gas is generated and the gate electrode are in direct contact with each other. This is because the Schottky barrier is lowered. For example, when Ni is used for the gate electrode, the AlGaN Schottky barrier with an Al ratio of 0.23 is about 1.3 eV, whereas the GaN Schottky barrier is about 1.0 eV.

  Further, in the inverted HEMT, the two-dimensional electron gas is located close to the surface of the stacked body of compound semiconductor layers, so that a current fluctuation called current collapse caused by the surface level is likely to occur. Sufficient output cannot be obtained.

JP 2006-269534 A JP 2006-261179 A Japanese Patent No. 3848548

  An object of the present invention is to provide a compound semiconductor device capable of reducing contact resistance while suppressing an increase in gate leakage current and a decrease in output, and a method for manufacturing the same.

In one aspect of the compound semiconductor device, an electron transit layer, an electron supply layer formed above the electron transit layer, a gate electrode formed above the electron supply layer, and the gate electrode interposed therebetween A source electrode and a drain electrode for applying a voltage to the electron transit layer; a GaN first compound semiconductor layer located in a current path between the source electrode and the electron transit layer and in contact with the source electrode; A GaN second compound semiconductor layer located in a current path between the drain electrode and the electron transit layer and in contact with the drain electrode. Further, a third compound semiconductor layer formed below the first compound semiconductor layer, having a lattice constant smaller than that of the first compound semiconductor layer and causing tensile strain, and a second compound semiconductor layer And a fourth compound semiconductor layer formed below and having a lattice constant smaller than that of the second compound semiconductor layer and causing tensile strain. The surface of the electron transit layer is a (0001) plane, and the surfaces of the first compound semiconductor layer and the second compound semiconductor layer are (000-1) planes.

In one aspect of the method for manufacturing a compound semiconductor device, an electron supply layer is formed above the electron transit layer, a gate electrode is formed above the electron supply layer, and a source electrode and a drain electrode that apply a voltage to the electron transit layer are provided. The gate electrode is interposed therebetween. In addition, a GaN first compound semiconductor layer located in a current path between the source electrode and the electron transit layer and in contact with the source electrode is formed, and a current between the drain electrode and the electron transit layer is formed. A second compound semiconductor layer of GaN located in the path and in contact with the drain electrode is formed. Furthermore, a third compound semiconductor layer having a lattice constant smaller than that of the first compound semiconductor layer and causing tensile strain is formed below the first compound semiconductor layer, and the second compound semiconductor layer A fourth compound semiconductor layer having a lattice constant smaller than that of the second compound semiconductor layer and causing tensile strain is formed below. The surface of the electron transit layer is the (0001) plane, and the surfaces of the first compound semiconductor layer and the second compound semiconductor layer are the (000-1) plane.

  According to the above compound semiconductor device and the like, since the appropriate first and second compound semiconductor layers exist below the source electrode and the drain electrode, contact resistance is suppressed while suppressing an increase in gate leakage current and a decrease in output. Can be reduced.

It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 1st Embodiment. It is a figure which shows the layout of GaN-type HEMT which concerns on 1st Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 1st Embodiment. FIG. 3B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3A. FIG. 3B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3B. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 2nd Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 3rd Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 3rd Embodiment. FIG. 7B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7A. FIG. 7B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7B. 7C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7C. It is sectional drawing which shows the structure of the modification of 3rd Embodiment. It is sectional drawing which shows the structure of the modification of 1st Embodiment. It is sectional drawing which shows the structure of the other modification of 3rd Embodiment.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. FIG. 1 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the first embodiment. FIG. 2 is a diagram showing a layout of the GaN-based HEMT (semiconductor device) according to the first embodiment.

  In the first embodiment, as shown in FIG. 1, an AlN layer 2 is formed on a substrate 1 such as a sapphire substrate. The thickness of the AlN layer 2 is about 10 nm to 30 nm (for example, 10 nm). An opening 2b is formed in the AlN layer 2 so as to correspond to the source and drain, respectively. An undoped i-GaN layer 3a is formed on the AlN layer 2, and an undoped i-GaN layer 3b is formed on the substrate 1 exposed from the opening 2b. The surface of the i-GaN layer 3a is a Ga-polar (0001) plane, and the surface of the i-GaN layer 3b is an N-polar (000-1) plane. The i-GaN layer 3a and the i-GaN layer 3b have a thickness of about 0.5 μm to 5.0 μm (for example, 2 μm). Since the thickness of the AlN layer 2 is negligibly small compared to the thickness of the i-GaN layer 3a and the i-GaN layer 3b, the surfaces of the i-GaN layer 3a and the i-GaN layer 3b are almost flat. Yes.

  On the i-GaN layer 3a, a non-doped i-AlGaN layer 4a, an n-type n-AlGaN layer 5a, and an n-type n-GaN layer 6a are formed in this order. The surfaces of the i-AlGaN layer 4a, the n-AlGaN layer 5a, and the n-GaN layer 6a are Ga-polar (0001) surfaces, like the i-GaN layer 3a.

  On the i-GaN layer 3b, an undoped i-AlGaN layer 4b, an n-type n-AlGaN layer 5b, and an n-type n-GaN layer 6b are formed in this order. The surfaces of the i-AlGaN layer 4b, the n-AlGaN layer 5b, and the n-GaN layer 6b are N-polar (000-1) planes like the i-GaN layer 3b. In the present embodiment, the n-GaN layer 6b corresponds to the first and second compound semiconductor layers, and the stacked body of the n-AlGaN layer 5b and the i-AlGaN layer 4b corresponds to the third and fourth compound semiconductor layers. To do.

The thickness of the i-AlGaN layer 4a and the i-AlGaN layer 4b is about 2 nm to 10 nm (for example, 5 nm). The compositions of the i-AlGaN layer 4a and the i-AlGaN layer 4b are represented by, for example, Al _0.2 Ga _0.8 N.

The thicknesses of the n-AlGaN layer 5a and the n-AlGaN layer 5b are about 2 nm to 50 nm (for example, 30 nm). Moreover, the composition of the n-AlGaN layer 5a and the n-AlGaN layer 5b is represented by, for example, Al _0.2 Ga _0.8 N. As the n-type impurity, for example, Si is doped with about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 5 × 10 ¹⁸ cm ⁻³ ).

The thickness of the n-GaN layer 6a and the n-GaN layer 6b is about 2 nm to 10 nm (for example, 10 nm). Further, as the n-type impurity, for example, Si is doped with about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 5 × 10 ¹⁸ cm ⁻³ ).

  A source electrode 11s and a drain electrode 11d are formed on the n-GaN layer 6b. The source electrode 11s and the drain electrode 11d include, for example, a Ti layer and an Al layer formed thereon. Further, a passivation film 7 covering the source electrode 11s and the drain electrode 11d is formed on the entire surface. The passivation film 7 has a gate electrode opening 7g located between the source electrode 11s and the drain electrode 11d. The gate electrode 11g is formed on the n-GaN layer 6a exposed from the opening 7g. Has been. A passivation film 8 is formed on the passivation film 7 so as to cover the gate electrode 11g. For example, a silicon nitride film is formed as the passivation films 7 and 8.

  The layout viewed from the front side of the substrate 1 is, for example, as shown in FIG. That is, the planar shape of the gate electrode 11g, the source electrode 11s, and the drain electrode 11d is a comb shape, and the source electrodes 11s and the drain electrodes 11d are alternately arranged. A gate electrode 11g is disposed between them. By adopting such a multi-finger gate structure, the output can be improved. The cross-sectional view shown in FIG. 1 is a cross-sectional view taken along the line II in FIG. The active region 10 includes i-GaN layers 3a and 3b and i-AlGaN layers 4a and 4b. The periphery of the active region 10 is made an inactive region by ion implantation or mesa etching.

  In the first embodiment configured as described above, as shown in FIG. 1, two-dimensionally in the vicinity of the interface between the n-GaN layer 6b and the n-AlGaN layer 5b below the source electrode 11s and the drain electrode 11d. Electron gas is generated. This is because the surfaces of the i-GaN layer 3b, i-AlGaN layer 4b, n-AlGaN layer 5b and n-GaN layer 6b are N-polar (000-1) planes and are located below the n-GaN layer 6b. This is because the lattice constants of the n-AlGaN layer 5b and the i-AlGaN layer 4b are smaller than that of the n-GaN layer 6b, and tensile strain is generated in the n-AlGaN layer 5b. Since a two-dimensional electron gas is generated in the vicinity of the interface between the n-GaN layer 6b and the n-AlGaN layer 5b, the AlGaN functioning as a barrier between the source electrode 11s and the drain electrode 11d and the two-dimensional electron gas. There is no layer. Therefore, the contact resistance of the source electrode 11s and the drain electrode 11d, which are ohmic electrodes, is reduced to the same level as that of the conventional inversion HEMT.

  On the other hand, between the source electrode 11s and the drain electrode 11d, two-dimensional electron gas is generated in the vicinity of the interface between the i-GaN layer 3a and the i-AlGaN layer 4a. This is because the surfaces of the i-GaN layer 3a, i-AlGaN layer 4a, n-AlGaN layer 5a, and n-GaN layer 6a are Ga-polar (0001) planes. The i-AlGaN layer 4a and the n-AlGaN layer 5a function as an electron supply layer, and a part (surface layer part) of the i-GaN layer 3a functions as an electron transit layer. As a result, a current flows between the drain electrode 11d and the two-dimensional electron gas below the gate electrode 11g via the n-GaN layer 6b (second compound semiconductor layer), and the two-dimensional electron gas below the gate electrode 11g. A current flows between the source electrode 11s and the source electrode 11s via the n-GaN layer 6b (first compound semiconductor layer). Further, since a two-dimensional electron gas is generated in the vicinity of the interface between the i-GaN layer 3a and the i-AlGaN layer 4a, the n-AlGaN layer 5a and the i-AlGaN layer between the gate electrode 11g and the two-dimensional electron gas. 4a functions as a barrier. Therefore, gate leakage current is unlikely to occur. The two-dimensional electron gas is separated from the n-GaN layer 6a located on the surface of the compound semiconductor layer stack, and the (0001) plane i-GaN layer 3a and i-AlGaN layer 4a. The n-AlGaN layer 5a and the n-GaN layer 6a hardly generate residual carriers, so that a high output can be obtained.

  Thus, according to the first embodiment, it is possible to reduce the contact resistance of the source electrode 11s and the drain electrode 11d while suppressing the gate leakage current and ensuring a high output.

  Next, a method for manufacturing the GaN-based HEMT according to the first embodiment will be described. 3A to 3C are cross-sectional views showing a method of manufacturing the GaN-based HEMT according to the first embodiment in the order of steps.

In the first embodiment, first, as shown in FIG. 3A (a), an AlN layer 2 is formed on a substrate 1 by, for example, a sputtering method or the like. Next, the AlN layer 2 is etched using the resist pattern that exposes the region where the opening 2b is to be formed as a mask, thereby forming the opening 2b in the AlN layer 2 as shown in FIG. 3A (b). . Thereafter, a non-doped i-GaN layer is grown on the substrate 1 and the AlN layer 2 exposed from the opening 2b by, for example, a molecular beam epitaxy (MBE) method. At this time, for example, solid Ga and NH ₃ gas are used as raw materials. As a result, as shown in FIG. 3A (c), an i-GaN layer 3b having a surface of N polarity and a (000-1) plane is formed on the substrate 1 exposed from the opening 2b. On the layer 2, an i-GaN layer 3a having a Ga polarity and a (0001) plane is formed.

  There are steps on the lower surfaces of the i-GaN layer 3a and the i-GaN layer 3b depending on the presence or absence of the AlN layer 2, but the thickness of the AlN layer 2 compared to the thickness of the i-GaN layer 3a and the i-GaN layer 3b. Is small enough to be ignored. For this reason, the surfaces of the i-GaN layer 3a and the i-GaN layer 3b are almost flat.

  Subsequently, a non-doped i-AlGaN layer, an n-type n-AlGaN layer, and an n-type n-GaN layer are grown in this order on the i-GaN layer 3a and the i-GaN layer 3b by, for example, the MBE method. Let As a result, as shown in FIG. 3B (d), an i-AlGaN layer 4a, an n-AlGaN layer 5a, and an n-GaN layer 6a are formed in this order on the i-GaN layer 3a, and the i-GaN layer 3b. On top, the i-AlGaN layer 4b, the n-AlGaN layer 5b, and the n-GaN layer 6b are formed in this order.

  Next, as shown in FIG. 3B (e), a source electrode 11s and a drain electrode 11d are formed on the two n-GaN layers 6b sandwiching the n-GaN layer 6a, respectively. In forming the source electrode 11s and the drain electrode 11d, for example, a resist pattern that exposes the n-GaN layer 6b is formed on the n-GaN layer 6a, and then a Ti layer is formed by a vapor deposition method, and vapor deposition is performed thereon. An Al layer is formed by the method. Then, the resist pattern is removed. That is, in the formation of the source electrode 11s and the drain electrode 11d, for example, vapor deposition and lift-off techniques are used. Subsequently, heat treatment is performed at 600 ° C. in a nitrogen atmosphere to establish ohmic contact between the source electrode 11s and the drain electrode 11d.

  Next, as shown in FIG. 3B (f), the passivation film 7 covering the source electrode 11s and the drain electrode 11d is formed on the n-GaN layer 6a by, for example, plasma enhanced chemical vapor deposition (PECVD). Form on top.

  Thereafter, as shown in FIG. 3C (g), an opening 7g for a gate electrode is formed in the passivation film 7. In forming the opening 7g, for example, a resist pattern exposing a region where the opening 7g is to be formed is formed on the passivation film 7, and the passivation film 7 is etched using this resist pattern as a mask. After the opening 7g is formed, the gate electrode 11g is formed in the opening 7g. In forming the gate electrode 11g, for example, a resist pattern exposing the opening 7g is formed on the passivation film 7, an Ni layer is then formed by vapor deposition, and an Au layer is formed thereon by vapor deposition. Then, the resist pattern is removed. That is, even in the formation of the gate electrode 11g, for example, vapor deposition and lift-off techniques are used.

  Subsequently, as shown in FIG. 3C (h), a passivation film 8 covering the gate electrode 11g is formed on the passivation film 7, for example, by PECVD.

  Thereafter, wiring (not shown) or the like is formed as necessary to complete the GaN-based HEMT.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 4 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the second embodiment.

  In the first embodiment, a Schottky structure is employed for the gate electrode 11g, whereas in the second embodiment, a MIS (metal-insulator-semiconductor) structure is employed for the gate electrode 11g. Other configurations are the same as those of the first embodiment.

  According to the second embodiment, the gate leakage current can be further reduced as compared with the first embodiment. Note that the first embodiment is superior to the second embodiment in terms of high-speed operation.

  In manufacturing such a second embodiment, first, processing up to the formation of the passivation film 7 is performed in the same manner as in the first embodiment, and then, as shown in FIG. The gate electrode 11g is formed on the passivation film 7 without forming the film. Subsequently, the passivation film 8 may be formed as in the first embodiment.

(Third embodiment)
Next, a third embodiment will be described. FIG. 6 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the third embodiment.

  In the third embodiment, as shown in FIG. 6, an AlN layer 2 is formed on a substrate 1 such as a sapphire substrate. An undoped i-GaN layer 3a is formed on the AlN layer 2, and an undoped i-GaN layer 3b is formed on the substrate 1 exposed from the opening 2b. The surface of the i-GaN layer 3a is a Ga-polar (0001) plane, and the surface of the i-GaN layer 3b is an N-polar (000-1) plane.

  On the i-GaN layer 3a, a non-doped i-AlGaN layer 21a and a non-doped i-GaN layer 22a are formed in this order. The surfaces of the i-AlGaN layer 21a and the i-GaN layer 22a are Ga-polar (0001) planes like the i-GaN layer 3a.

  A non-doped i-AlGaN layer 21b and a non-doped i-GaN layer 22b are formed in this order on the i-GaN layer 3b. The surfaces of the i-AlGaN layer 21b and the i-GaN layer 22b are N-polar (000-1) planes like the i-GaN layer 3a. In the present embodiment, the i-GaN layer 22b corresponds to the first and second compound semiconductor layers, and the i-AlGaN layer 21b corresponds to the third and fourth compound semiconductor layers.

The thickness of the i-AlGaN layer 21a and the i-AlGaN layer 21b is about 10 nm to 100 nm (for example, 50 nm). The compositions of the i-AlGaN layer 21a and the i-AlGaN layer 21b are represented by, for example, Al _0.1 Ga _0.9 N.

  The i-GaN layer 22a and the i-GaN layer 22b have a thickness of about 20 nm to 100 nm (for example, 50 nm).

  An i-AlGaN layer 4a, an n-AlGaN layer 5a, and an n-GaN layer 6a are formed in this order on the i-GaN layer 22a. The surfaces of the i-AlGaN layer 4a, the n-AlGaN layer 5a, and the n-GaN layer 6a are Ga-polar (0001) surfaces, like the i-GaN layer 3a.

  In this embodiment, the i-AlGaN layer 4b, the n-AlGaN layer 5b, and the n-GaN layer 6b are not formed, and the i-AlGaN layer 4a, the n-AlGaN layer 5a, and the n-GaN layer 6a are i-- Openings 31s and 31d exposing the GaN layer 22b are formed. A source electrode 11s is formed in the opening 31s, and a drain electrode 11d is formed in the opening 31d. That is, the source electrode 11s and the drain electrode 11d are in contact with the i-GaN layer 22b.

  As in the first embodiment, a passivation film 7 covering the source electrode 11s and the drain electrode 11d is formed on the entire surface. The passivation film 7 has a gate electrode opening 7g located between the source electrode 11s and the drain electrode 11d. The gate electrode 11g is formed on the n-GaN layer 6a exposed from the opening 7g. Has been. A passivation film 8 is formed on the passivation film 7 so as to cover the gate electrode 11g.

  In the first embodiment configured as described above, as shown in FIG. 1, two-dimensionally in the vicinity of the interface between the i-GaN layer 22b and the i-AlGaN layer 21b below the source electrode 11s and the drain electrode 11d. Electron gas is generated. This is because the surfaces of the i-GaN layer 3b, i-AlGaN layer 21b, and i-GaN layer 22b are N-polar (000-1) planes. Since a two-dimensional electron gas is generated in the vicinity of the interface between the i-GaN layer 22b and the i-AlGaN layer 21b, the AlGaN functioning as a barrier between the source electrode 11s and the drain electrode 11d and the two-dimensional electron gas. There is no layer. Therefore, the contact resistance of the source electrode 11s and the drain electrode 11d, which are ohmic electrodes, is reduced to the same level as that of the conventional inversion HEMT.

  On the other hand, between the source electrode 11s and the drain electrode 11d, a two-dimensional electron gas is generated in the vicinity of the interface between the i-GaN layer 22a and the i-AlGaN layer 4a. This is because the surfaces of the i-GaN layer 3a, i-AlGaN layer 21a, i-GaN layer 22a, i-AlGaN layer 4a, n-AlGaN layer 5a and n-GaN layer 6a are Ga-polar (0001) planes. is there. The i-AlGaN layer 4a and the n-AlGaN layer 5a function as an electron supply layer, and a part (surface layer part) of the i-GaN layer 22a functions as an electron transit layer. Further, since a two-dimensional electron gas is generated in the vicinity of the interface between the i-GaN layer 22a and the i-AlGaN layer 4a, the n-AlGaN layer 5a and the i-AlGaN layer between the gate electrode 11g and the two-dimensional electron gas. 4a functions as a barrier. Therefore, gate leakage current is unlikely to occur. The two-dimensional electron gas is separated from the n-GaN layer 6a located on the surface of the compound semiconductor layer stack, and the (0001) plane i-GaN layer 3a and i-AlGaN layer 4a. The n-AlGaN layer 5a and the n-GaN layer 6a hardly generate residual carriers, so that a high output can be obtained.

  Furthermore, in this embodiment, as shown in FIG. 6, two-dimensionally between the i-GaN layer 22b in which a two-dimensional electron gas is generated below the source electrode 11s and the drain electrode 11d and the source electrode 11s and the drain electrode 11d. The i-GaN layer 22a that generates electron gas is adjacent to each other, and there is no AlGaN layer therebetween. For this reason, compared with 1st Embodiment, resistance between the source electrode 11s and the drain electrode 11d becomes low.

  Next, a method for manufacturing a GaN-based HEMT according to the third embodiment will be described. 7A to 7D are cross-sectional views showing a method of manufacturing the GaN-based HEMT according to the third embodiment in the order of steps.

  In the third embodiment, first, similarly to the first embodiment, the processes up to the formation of the i-GaN layer 3a and the i-GaN layer 3b are performed. Next, a non-doped i-AlGaN layer and a non-doped i-GaN layer are grown in this order on the i-GaN layer 3a and the i-GaN layer 3b by, for example, the MBE method. As a result, as shown in FIG. 7A (a), the i-AlGaN layer 21a and the i-GaN layer 22a are formed in this order on the i-GaN layer 3a, and the i-AlGaN layer 3b is formed on the i-GaN layer 3b. The layer 21b and the i-GaN layer 22b are formed in this order.

  Thereafter, as in the first embodiment, a non-doped i-AlGaN layer, an n-type n-AlGaN layer, and an n-type layer are formed on the i-GaN layer 22a and the i-GaN layer 22b by, for example, the MBE method. An n-GaN layer is grown in this order. As a result, as shown in FIG. 7B (b), the i-AlGaN layer 4a, the n-AlGaN layer 5a, and the n-GaN layer 6a are formed in this order on the i-GaN layer 22a, and the i-GaN layer 22b. On top, the i-AlGaN layer 4b, the n-AlGaN layer 5b, and the n-GaN layer 6b are formed in this order.

  Subsequently, by etching the i-AlGaN layer 4b, the n-AlGaN layer 5b, and the n-GaN layer 6b, as shown in FIG. 7B (c), the opening 31s for the source electrode 11s and the drain electrode 11d Opening 31d is formed. In this etching, for example, a resist pattern that exposes the regions for forming the openings 31s and 31d is formed on the n-GaN layer 6a, and dry etching using a chlorine-based gas is performed using the resist pattern as a mask. .

  Next, as shown in FIG. 7C (d), the source electrode 11s is formed in the opening 31s, and the drain electrode 11d is formed in the opening 31d. In the formation of the source electrode 11s and the drain electrode 11d, for example, vapor deposition and lift-off techniques are used as in the first embodiment. Thereafter, heat treatment is performed at 600 ° C. in a nitrogen atmosphere to establish ohmic contact between the source electrode 11s and the drain electrode 11d.

  Subsequently, as shown in FIG. 7C (e), a passivation film 7 covering the source electrode 11s and the drain electrode 11d is formed on the n-GaN layer 6a by, for example, PECVD.

  Next, as shown in FIG. 7D (f), an opening 7g for a gate electrode is formed in the passivation film 7, and a gate electrode 11g is formed in the opening 7g. Also in the formation of the gate electrode 11g, for example, vapor deposition and lift-off techniques are used as in the first embodiment.

  Subsequently, as shown in FIG. 7D (g), a passivation film 8 covering the gate electrode 11g is formed on the passivation film 7 by, for example, PECVD.

  Thereafter, wiring (not shown) or the like is formed as necessary to complete the GaN-based HEMT.

  Also in the third embodiment, as shown in FIG. 8, a MIS structure may be employed for the gate electrode 11g.

  In the third embodiment, similarly to the first embodiment, an i-AlGaN layer 4b, an n-AlGaN layer 5b, and an n-GaN layer 6b may be provided, and the i-AlGaN layer 21a may be provided. And 21b may not be provided.

  In any of the embodiments, the interface between the i-GaN layer 3a and the i-GaN layer 3b needs to coincide with the edge of the source electrode 11s and the drain electrode 11d on the gate electrode 11g side in plan view. Absent. For example, in the first embodiment, as shown in FIG. 9, the interface between the i-GaN layer 3a and the i-GaN layer 3b is more than the edge of the source electrode 11s and the drain electrode 11d on the gate electrode 11g side. It may be located on the gate electrode 11g side. The interface may be located farther from the gate electrode 11g than the edge, but is preferably located on the gate electrode 11g side. This is for effectively reducing the contact resistance of the source electrode 11s and the drain electrode 11d. The same applies to other embodiments.

  Further, in the third embodiment, as shown in FIG. 10, the edge of the opening 31s and the edge of the source electrode 11s do not need to coincide with each other in plan view. The edges of the drain electrode 11d do not have to coincide with each other. That is, for example, the passivation film 7 may enter between the edge of the opening 31s and the edge of the source electrode 11s and between the edge of the opening 31d and the edge of the drain electrode 11d.

  Note that these GaN-based HEMTs can be used for, for example, high-power amplifiers included in wireless communication base stations. Moreover, it can be used for a DC-DC converter, an AC-AC converter, an AC-DC converter, a high frequency power source, etc. as a power supply application. In power supply applications, it is possible to reduce the size of passive components and reduce the number of elements by increasing the frequency by utilizing the high breakdown voltage, low loss, and high-speed switching characteristics of GaN. It becomes possible. And by these, size reduction, weight reduction, and cost reduction of a power converter device are realizable.

  Moreover, the material of each compound semiconductor layer is not limited. For example, a nitride semiconductor such as GaN, AlN, or InN may be used alone, or a mixed crystal of two or more of these may be used. The substrate is preferably a sapphire substrate, but other substrates may be used.

  Further, the growth conditions of the compound semiconductor layer are not particularly limited. Various epitaxial lateral overgrowth (ELO) techniques have been developed for GaN-based compound semiconductor layers. For example, FIELO (facet-initiated ELO) technology based on the hydride vapor phase epitaxy (HVPE) method and FACELO (facet-controlled) based on the metal-organic vapor phase epitaxy (MOVPE) method. ELO) technology has been developed.

  Further, the semiconductor element formed over the compound semiconductor layer is not limited to HEMT. For example, an insulated gate bipolar transistor (IGBT) may be formed.

1: Substrate 2: AlN layer 2b: Opening 3a, 3b: i-GaN layer 4a, 4b: i-AlGaN layer 5a, 5b: n-AlGaN layer 6a, 6b: n-GaN layer 7, 8: Passivation film 8 : I-AlGaN layer 10: active region 11d: drain electrode 11g: gate electrode 11s: source electrode 21a, 21b: i-AlGaN layer 22a, 22b: i-GaN layer 31s, 31d: opening

Claims (6)

An electronic travel layer,
An electron supply layer formed above the electron transit layer;
A gate electrode formed above the electron supply layer;
A source electrode and a drain electrode which are formed with the gate electrode interposed therebetween and apply a voltage to the electron transit layer;
A first compound semiconductor layer of GaN located in a current path between the source electrode and the electron transit layer and in contact with the source electrode;
A second compound semiconductor layer of GaN located in a current path between the drain electrode and the electron transit layer and in contact with the drain electrode;
A third compound semiconductor layer formed below the first compound semiconductor layer, having a lattice constant smaller than that of the first compound semiconductor layer and causing tensile strain;
A fourth compound semiconductor layer formed below the second compound semiconductor layer, having a lattice constant smaller than that of the second compound semiconductor layer and causing tensile strain;
Have
The surface of the electron transit layer is a (0001) plane,
The compound semiconductor device characterized in that the surfaces of the first compound semiconductor layer and the second compound semiconductor layer are (000-1) planes.   2. The compound semiconductor device according to claim 1, wherein the electron transit layer, the electron supply layer, the first compound semiconductor layer, and the second compound semiconductor layer are made of a nitride semiconductor.   3. The compound semiconductor device according to claim 2, wherein the nitride semiconductor is made of one or more mixed crystals selected from the group consisting of GaN, AlN, and InN.   4. The compound semiconductor device according to claim 1, wherein the first compound semiconductor layer and the second compound semiconductor layer are in direct contact with the electron transit layer. 5. 5. The compound semiconductor device according to claim 1, wherein the third compound semiconductor layer and the fourth compound semiconductor layer are AlGaN layers . 6. Forming an electron supply layer above the electron transit layer;
Forming a gate electrode above the electron supply layer;
Forming a source electrode and a drain electrode for applying a voltage to the electron transit layer with the gate electrode interposed therebetween;
Forming a first compound semiconductor layer of GaN located in a current path between the source electrode and the electron transit layer and in contact with the source electrode;
Forming a second compound semiconductor layer of GaN located in a current path between the drain electrode and the electron transit layer and in contact with the drain electrode;
Forming a third compound semiconductor layer having a lattice constant smaller than that of the first compound semiconductor layer and causing tensile strain below the first compound semiconductor layer;
Forming a fourth compound semiconductor layer below the second compound semiconductor layer having a lattice constant smaller than that of the second compound semiconductor layer and causing tensile strain;
Have
The surface of the electron transit layer is a (0001) plane,
A method of manufacturing a compound semiconductor device, wherein surfaces of the first compound semiconductor layer and the second compound semiconductor layer are (000-1) planes.

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