JP5640325B2 - Compound semiconductor device - Google Patents

Description

The present invention relates to a compound semiconductor equipment.

  Conventionally, a semiconductor device using a silicon-based material has been used. In a semiconductor element such as a transistor constituting this semiconductor device, a p-type region and an n-type region are arranged in parallel to the surface of the substrate, and a pn junction formed between them is used. A semiconductor integrated circuit is configured by integrating such semiconductor elements.

  On the other hand, in recent years, compound semiconductor devices having a high breakdown voltage and a high output that make use of characteristics such as a high saturation electron velocity and a wide band gap of a nitride-based compound semiconductor have been actively developed. For example, field effect transistors such as a high electron mobility transistor (HEMT) have been developed. Among these, GaN-based HEMTs that include an AlGaN layer as an electron supply layer have attracted attention. In such a GaN-based HEMT, a strain caused by the difference in lattice constant between AlGaN and GaN is generated in the AlGaN layer, piezo-polarization occurs along with this strain, and a high-concentration two-dimensional electron gas is formed in the GaN under the AlGaN layer. Occurs near the top surface of the layer. For this reason, a high output can be obtained.

  However, in such a compound semiconductor device, it is possible to arrange the p-type region and the n-type region perpendicularly to the surface of the substrate, but partial doping by ion implantation or the like is difficult, and silicon-based material is used. It is difficult to integrate like the semiconductor device used.

  Research has also been conducted on a technique for arranging the p-type region and the n-type region in parallel with the surface of the substrate, but sufficient results have not been obtained so far. For example, a technique has been proposed in which a part of an Mg nitride semiconductor layer that is a p-type impurity is irradiated with an electron beam to activate the p-type impurity in that part. According to this technique, in theory, a region where the p-type impurity is activated becomes a p-type region, and a region where the p-type impurity is not activated becomes an n-type region. However, in reality, it is difficult to sufficiently activate Mg (p-type impurity), and the resistance tends to increase. In addition, since Mg (p-type impurity) is contained in the n-type region, carrier scattering is likely to occur, and the resistance tends to be high in this respect as well.

  In addition, in a conventional compound semiconductor device, it is difficult to realize a normally-off operation. For example, a GaN-based HEMT has been proposed in which a p-type layer containing Mg (p-type impurities) is provided between a gate electrode and an active region. According to this technique, theoretically, the two-dimensional electron gas directly under the gate is canceled and a normally-off operation is possible. However, in reality, it is difficult to sufficiently activate high-concentration Mg (p-type impurities).

  The activation of Mg can be performed by a heat treatment at a high temperature of 800 ° C. or higher. However, the partial activation is not possible with heat treatment. Further, when heat treatment is performed at a high temperature, nitrogen is desorbed from the nitride semiconductor layer, or the state of the interface between the nitride semiconductor layers is deteriorated.

JP 2000-40857 A JP 2007-19309 A

An object of the present invention is to provide a compound semiconductor equipment capable of reducing the on-resistance.

In one embodiment of the compound semiconductor device, a first compound semiconductor layer having a (0001) plane on the surface and a second compound semiconductor layer having a (000-1) plane on the surface are formed in contact with each other above the substrate. Is provided. A second compound semiconductor layer formed on the first compound semiconductor layer and having a lattice constant smaller than that of the first compound semiconductor layer; and the second compound semiconductor layer in contact with the third compound semiconductor layer. A fourth compound semiconductor layer formed on the compound semiconductor layer and having a lattice constant smaller than that of the second compound semiconductor layer is provided. Furthermore, the first electrode for applying a potential to the first compound semiconductor layer formed above the third compound semiconductor layer , and the first compound semiconductor layer formed above the fourth compound semiconductor layer . A second electrode for applying a potential to the two compound semiconductor layers is provided.

  According to the above compound semiconductor device and the like, since the appropriate first and second compound semiconductor layers exist below the source electrode and the drain electrode, contact resistance is suppressed while suppressing an increase in gate leakage current and a decrease in output. Can be reduced.

It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 1st Embodiment. FIG. 1B is a cross-sectional view illustrating the method for manufacturing the compound semiconductor device according to the first embodiment following FIG. 1A. It is a schematic diagram which shows distribution of the carrier in 1st Embodiment. It is a graph which shows the result of the simulation about a 1st embodiment. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 2nd Embodiment. FIG. 4D is a cross-sectional view illustrating the method for manufacturing the compound semiconductor device according to the second embodiment, following FIG. 4A. FIG. 4B is a cross-sectional view illustrating the method for manufacturing the compound semiconductor device according to the second embodiment following FIG. 4B. It is a schematic diagram which shows distribution of the carrier in 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, a method for manufacturing a diode (compound semiconductor device) according to the first embodiment will be described. 1A to 1B are cross-sectional views showing a method of manufacturing the compound semiconductor device according to the first embodiment in the order of steps.

In the first embodiment, first, as shown in FIG. 1A (a), an AlN layer 12 is formed on a substrate 11 such as a sapphire substrate by, for example, sputtering. The thickness of the AlN layer 12 is about 10 nm to 30 nm (for example, 10 nm). Next, the AlN layer 12 is etched using a resist pattern that opens a region where a p-type region (a region corresponding to the anode) is to be formed as a mask, as shown in FIG. 1A (b). An opening 12 b is formed in the layer 12. Thereafter, an undoped i-GaN layer is grown on the substrate 11 and the AlN layer 12 exposed from the opening 12b by, for example, a molecular beam epitaxy (MBE) method. At this time, for example, solid Ga and NH ₃ gas are used as raw materials. As a result, as shown in FIG. 1A (c), on the substrate 11 exposed from the opening 12b, the i-GaN layer 13a (second compound semiconductor layer) whose surface is N-polar and has a (000-1) plane. And an i-GaN layer 13b (first compound semiconductor layer) having a Ga polarity and a (0001) plane is formed on the AlN layer 12. The thicknesses of the i-GaN layer 13a and the i-GaN layer 13b are about 0.5 μm to 5.0 μm (for example, 2 μm). Since the thickness of the AlN layer 12 is negligibly small compared to the thickness of the i-GaN layer 13a and the i-GaN layer 13b, the surfaces of the i-GaN layer 13a and the i-GaN layer 13b are almost flat.

Next, a non-doped i-AlGaN layer is grown on the i-GaN layer 13a and the i-GaN layer 13b by, for example, the MBE method. As a result, as shown in FIG. 1A (d), an i-AlGaN layer 14a (fourth compound semiconductor layer) is formed on the i-GaN layer 13a, and an i-AlGaN layer 14b (on the i-GaN layer 13b). A third compound semiconductor layer) is formed. The i-AlGaN layer 14a has an N-polar (000-1) plane, similar to the i-GaN layer 13a, and the i-AlGaN layer 14b has a Ga-polar surface, similar to the i-GaN layer 13b. (0001) plane. The thickness of the i-AlGaN layer 14a and the i-AlGaN layer 14b is about 2 nm to 10 nm (for example, 5 nm). The compositions of the i-AlGaN layer 14a and the i-AlGaN layer 14b are represented by, for example, Al _0.2 Ga _0.8 N.

  Next, as shown in FIG. 1B (e), the anode electrode 15a is formed on the i-AlGaN layer 14a, and the cathode electrode 15c is formed on the i-AlGaN layer 14b. In forming the anode electrode 15a and the cathode electrode 15c, for example, a resist pattern exposing a part of the i-AlGaN layer 14a and a part of the i-AlGaN layer 14b is formed on the i-AlGaN layer 14a and the i-AlGaN layer 14b. Then, a Ti layer is formed by a vapor deposition method, and an Al layer is formed thereon by a vapor deposition method. Then, the resist pattern is removed. That is, in the formation of the anode electrode 15a and the cathode electrode 15c, for example, vapor deposition and lift-off techniques are used. Subsequently, heat treatment is performed at 600 ° C. in a nitrogen atmosphere to establish ohmic contact between the anode electrode 15a and the cathode electrode 15c.

  Next, as shown in FIG. 1B (f), the passivation film 16 covering the anode electrode 15a and the cathode electrode 15c is formed on the i-AlGaN layer 14a by, for example, plasma enhanced chemical vapor deposition (PECVD). And formed on the i-AlGaN layer 14b.

  Then, wiring (not shown) etc. are formed as needed and a diode is completed.

  Here, a general carrier distribution of the GaN-based semiconductor layer will be described. There can be two types of different polarities on the surface of the GaN-based semiconductor layer: Ga-aligned (0001) plane (Ga-polar plane) and N-arranged (000-1) plane (N-polar plane). . Then, between the Ga polarity and the N polarity, the directions of spontaneous polarization and piezo polarization are the same. That is, in a GaN-based semiconductor layer with a Ga-polar surface, negative spontaneous polarization occurs near the surface, and positive spontaneous polarization occurs in the vicinity of the bottom surface, whereas in a GaN-based semiconductor layer with N-polar surface, Positive spontaneous polarization occurs, and negative spontaneous polarization occurs near the bottom surface. In addition, since the lattice constant of AlGaN is smaller than that of GaN, tensile strain is generated in the AlGaN layer epitaxially grown on the GaN layer due to the difference in lattice constant from the GaN layer, and the piezoelectric polarization associated with this tensile strain is reduced. Arise. That is, in a GaN-based semiconductor layer having a Ga-polar surface, negative piezo-polarization occurs in the vicinity of the surface and positive piezo-polarization occurs in the vicinity of the bottom surface (interface with the GaN layer), whereas the GaN-based semiconductor surface has an N-polarity In the semiconductor layer, positive piezo polarization occurs near the surface, and negative piezo polarization occurs near the bottom surface (interface with the GaN layer). Therefore, in the GaN-based semiconductor layer having a Ga-polar surface, the electric field is generated from the bottom surface toward the surface, whereas in the GaN-based semiconductor layer having the N-polar surface, the electric field is generated from the surface toward the bottom surface. .

  When the AlGaN layer is formed on the GaN layer by epitaxial growth, the polarization opposite to the polarization induced in the AlGaN layer is caused in the vicinity of the interface between the GaN layer and the AlGaN layer by the action of the spontaneous polarization and the piezoelectric polarization as described above. A charge is induced. That is, electrons are induced in the GaN layer whose surface is the (0001) plane (Ga-polar plane), and holes are induced in the GaN layer whose surface is the (000-1) plane (N-polar plane). .

  In the present embodiment, as described above, the anode electrode 15a (second electrode) is formed above the i-GaN layer 13a and the i-AlGaN layer 14a having N-polar surfaces. Therefore, as shown in FIG. 2, positive polarization occurs near the surface of the i-AlGaN layer 14a (fourth compound semiconductor layer), negative polarization occurs near the bottom surface, and the i-GaN layer 13a (second Holes are induced in the vicinity of the surface of the compound semiconductor layer) (interface with the i-AlGaN layer 14a). The cathode electrode 15c (first electrode) is formed on the i-GaN layer 13b and the i-AlGaN layer 14b whose surfaces are Ga polar. Accordingly, as shown in FIG. 2, negative polarization occurs near the surface of the i-AlGaN layer 14b (third compound semiconductor layer), positive polarization occurs near the bottom surface, and the i-GaN layer 13b (first Electrons are induced in the vicinity of the surface of the compound semiconductor layer) (interface with the i-AlGaN layer 14b). These induced holes and electrons act as free carriers. For this reason, the i-GaN layer 13a functions as a p-type semiconductor layer, and the i-GaN layer 13b functions as an n-type semiconductor layer. In this embodiment, since the i-GaN layers 13a and 13b are in contact with each other, they function as a diode.

  In addition, since a region functioning as a p-type semiconductor layer and a region functioning as an n-type semiconductor layer are arranged in parallel to the surface of the substrate 11, it can be easily integrated in the same manner as a semiconductor device using a silicon-based material. It is possible.

  In this embodiment, since the high-concentration free carriers exist on the surfaces of the i-GaN layers 13a and 13b, the on-resistance can be reduced. Further, since doping of impurities is unnecessary for forming the p-type semiconductor layer and the n-type semiconductor layer, heat treatment under high temperature for sufficiently activating the impurities to reduce resistance is also unnecessary.

  Here, the simulation regarding the first embodiment performed by the inventor will be described. In this simulation, the carrier concentration distribution and the band shape in the vicinity of the surfaces of the i-GaN layers 13a and 13b of the diode having the structure shown in FIG. 1B (f) were calculated. The result is shown in FIG. FIG. 3A is a graph showing the carrier concentration distribution, and FIG. 3B is a graph showing the band shape. 3A and 3B indicate positions in a direction parallel to the surface of the substrate 11. In FIG. “0.5 μm” corresponds to a position immediately below the anode electrode 15a, “−0.5 μm” corresponds to a position immediately below the cathode electrode 15c, and “0 μm” corresponds to the center between the anode electrode 15a and the cathode electrode 15c. Corresponds to position.

  As shown in FIG. 3A, the result was that holes were induced near the surface of the i-GaN layer 13a and electrons were induced near the surface of the i-GaN layer 13b. Further, as shown in FIG. 3B, a result that a band shape similar to that of the pn junction was obtained was obtained. That is, the result of operating as a diode was obtained.

(Second Embodiment)
Next, a method for manufacturing a field effect transistor (compound semiconductor device) according to the second embodiment will be described. 2A to 2C are cross-sectional views illustrating the method of manufacturing the compound semiconductor device according to the second embodiment in the order of steps.

In the second embodiment, first, as shown in FIG. 4A (a), an AlN layer 22 is formed on a substrate 21 such as a sapphire substrate by, for example, sputtering. The thickness of the AlN layer 22 is about 10 nm to 30 nm (for example, 10 nm). Next, the AlN layer 22 is etched using a resist pattern opening a region where a p-type region (a region corresponding to a channel) is to be formed as a mask, as shown in FIG. 4A (b). An opening 22 b is formed in the layer 22. Thereafter, a non-doped i-GaN layer is grown on the substrate 21 and the AlN layer 22 exposed from the opening 22b by, for example, the MBE method. At this time, for example, solid Ga and NH ₃ gas are used as raw materials. As a result, as shown in FIG. 4A (c), an i-GaN layer 23a having a N-polar surface and a (000-1) plane is formed on the substrate 21 exposed from the opening 22b. On top of this, an i-GaN layer 23b having a Ga polarity and a (0001) plane is formed. The i-GaN layer 23a and the i-GaN layer 23b have a thickness of about 0.5 μm to 5.0 μm (for example, 2 μm). Since the thickness of the AlN layer 22 is negligibly small compared to the thickness of the i-GaN layer 23a and the i-GaN layer 23b, the surfaces of the i-GaN layer 23a and the i-GaN layer 23b are almost flat.

  Next, a non-doped i-AlGaN layer, an n-type n-AlGaN layer, and an n-type n-GaN layer are grown in this order on the i-GaN layer 23a and the i-GaN layer 23b, for example, by MBE. . As a result, as shown in FIG. 4B (d), the i-AlGaN layer 24a, the n-AlGaN layer 25a, and the n-GaN layer 26a are formed in this order on the i-GaN layer 23a, and the i-GaN layer 23b. On top, an i-AlGaN layer 24b, an n-AlGaN layer 25b, and an n-GaN layer 26b are formed in this order.

  The surfaces of the i-AlGaN layer 24a, the n-AlGaN layer 25a, and the n-GaN layer 26a are N-polar (000-1) planes like the i-GaN layer 23a, and the i-AlGaN layer 24b, n-AlGaN Similar to the i-GaN layer 23b, the surfaces of the layer 25b and the n-GaN layer 26b are Ga-polar (0001) planes.

The thickness of the i-AlGaN layer 24a and the i-AlGaN layer 24b is about 2 nm to 10 nm (for example, 5 nm). The compositions of the i-AlGaN layer 24a and the i-AlGaN layer 24b are represented by, for example, Al _0.2 Ga _0.8 N. The thicknesses of the n-AlGaN layer 25a and the n-AlGaN layer 25b are about 2 nm to 50 nm (for example, 30 nm). The composition of the n-AlGaN layer 25a and the n-AlGaN layer 25b is represented by, for example, Al _0.2 Ga _0.8 N. As the n-type impurity, for example, Si is doped with about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 5 × 10 ¹⁸ cm ⁻³ ). The thickness of the n-GaN layer 26a and the n-GaN layer 26b is about 2 nm to 10 nm (for example, 10 nm). As the n-type impurity, for example, Si is doped with about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (for example, 5 × 10 ¹⁸ cm ⁻³ ).

  Next, as shown in FIG. 4B (e), a source electrode 31s and a drain electrode 31d are formed on the two n-GaN layers 26b sandwiching the n-GaN layer 26a, respectively. In forming the source electrode 31s and the drain electrode 31d, for example, a resist pattern exposing a part of each n-GaN layer 26b is formed on the n-GaN layers 26a and 26b, and then a Ti layer is formed by vapor deposition. Then, an Al layer is formed thereon by vapor deposition. Then, the resist pattern is removed. That is, in the formation of the source electrode 31s and the drain electrode 31d, for example, vapor deposition and lift-off techniques are used. Subsequently, heat treatment is performed at 600 ° C. in a nitrogen atmosphere to establish ohmic contact between the source electrode 31s and the drain electrode 31d.

  Subsequently, as shown in FIG. 4B (f), a passivation film 27 covering the source electrode 31s and the drain electrode 31d is formed on the n-GaN layers 26a and 26b by, for example, PECVD.

  Next, as shown in FIG. 4C (g), an opening 27 g for the gate electrode is formed in the passivation film 27. In forming the opening 27g, for example, a resist pattern exposing a region for forming the opening 27g is formed on the passivation film 27, and the passivation film 27 is etched using this resist pattern as a mask. After the opening 27g is formed, the gate electrode 31g is formed in the opening 27g. In forming the gate electrode 31g, for example, a resist pattern that exposes the opening 27g is formed on the passivation film 27, then a Ni layer is formed by vapor deposition, and an Au layer is formed thereon by vapor deposition. Then, the resist pattern is removed. That is, for example, vapor deposition and lift-off techniques are used in forming the gate electrode 31g.

  Subsequently, as shown in FIG. 4C (h), a passivation film 28 covering the gate electrode 31g is formed on the passivation film 27 by, for example, PECVD.

  Thereafter, wiring (not shown) or the like is formed as necessary to complete the field effect transistor.

  In the field effect transistor manufactured by such a method, as described above, the gate electrode 31g (second electrode) has an i-GaN layer 23a, an i-AlGaN layer 24a, and an n-AlGaN layer whose surfaces have N polarity. 25a is formed above. Therefore, as shown in FIG. 5, positive polarization occurs near the surface of the AlGaN layer 29a (fourth compound semiconductor layer) including the i-AlGaN layer 24a and the n-AlGaN layer 25a, and negative polarization occurs near the bottom surface. As a result, holes are induced in the vicinity of the surface (interface with the AlGaN layer 29a) of the i-GaN layer 23a (second compound semiconductor layer). The source electrode 31s and the drain electrode 31d (first and third electrodes) are formed above the i-GaN layer 23b, i-AlGaN layer 24b, and n-AlGaN layer 25b whose surfaces are Ga polar. Therefore, as shown in FIG. 5, negative polarization occurs near the surface of the AlGaN layer 29b (third and sixth compound semiconductor layers) including the i-AlGaN layer 24b and the n-AlGaN layer 25b, and the positive polarity near the bottom surface. Is generated, and electrons are induced in the vicinity of the surface of the i-GaN layer 23b (fifth compound semiconductor layer) (interface with the AlGaN layer 29b). These induced holes and electrons act as free carriers. For this reason, the i-GaN layer 23a functions as a p-type semiconductor layer, and the i-GaN layer 23b functions as an n-type semiconductor layer. In the present embodiment, since the i-GaN layer 23a is in contact with the two i-GaN layers 23b sandwiching the i-GaN layer 23a, these function together as a normally-off type field effect transistor. That is, no current flows between the source electrode 31s and the drain electrode 31d while the gate electrode 31g is grounded.

  In addition, since a region functioning as a p-type semiconductor layer and a region functioning as an n-type semiconductor layer are arranged in parallel to the surface of the substrate 21, the semiconductor device can be easily integrated in the same manner as a semiconductor device using a silicon-based material. It is possible.

  Also in this embodiment, on-resistance can be reduced because high-concentration electrons are present on the surface of the i-GaN layer 23b. Further, since doping of impurities is unnecessary for forming the p-type semiconductor layer and the n-type semiconductor layer, heat treatment under high temperature for sufficiently activating the impurities to reduce resistance is also unnecessary.

  Note that the gate electrode 31g may be formed on the n-GaN layer 26a via an insulating film. That is, it may be a MIS (metal-insulator-semiconductor) type.

  In addition, the size between the source and the drain of the i-GaN layer 23a, i-AlGaN layer 24a, n-AlGaN layer 25a, and n-GaN layer 26a is not particularly limited, but is as narrow as possible within a range that can function as a field effect transistor. Is preferred. First, it is generally difficult to grow N-polar crystals, and the crystallinity of the i-GaN layer 23a tends to be lower than that of the i-GaN layer 23b. Secondly, the region functioning as a p-type semiconductor layer is narrowed to enable high-speed operation. Third, it is for facilitating control by the potential applied to the gate electrode 31g.

  Further, these compound semiconductor devices can be used for, for example, a high-power amplifier included in a base station for wireless communication. Moreover, it can be used for a DC-DC converter, an AC-AC converter, an AC-DC converter, a high frequency power source, etc. as a power supply application. In power supply applications, it is possible to reduce the size of passive components by increasing the frequency by utilizing the high breakdown voltage, low loss, and high-speed switching characteristics of GaN, and to reduce the size of the heat sink by reducing loss. And by these, size reduction, weight reduction, and cost reduction of a power converter device are realizable.

  Moreover, the material of each compound semiconductor layer is not limited. For example, a nitride semiconductor such as GaN, AlN, or InN may be used alone, or a mixed crystal thereof may be used. The substrate is preferably a sapphire substrate, but other substrates may be used.

  Further, the growth conditions of the compound semiconductor layer are not particularly limited. A metal-organic vapor phase epitaxy (MOVPE) method or the like may be used.

  Further, the semiconductor element formed over the compound semiconductor layer is not limited to the diode and the field effect transistor. For example, an insulated gate bipolar transistor (IGBT) may be formed.

DESCRIPTION OF SYMBOLS 11, 21: Board | substrate 12, 22: AlN layer 12b, 22b: Opening part 13a, 13b, 23a, 23b: i-GaN layer 14a, 14b, 24a, 24b: i-AlGaN layer 15a: Anode electrode 15c: Cathode electrode 16 27, 28: Passivation films 25a, 25b: n-AlGaN layers 26a, 26b: n-GaN layers 31d: drain electrodes 31g: gate electrodes 31s: source electrodes

Claims (7)

A first compound semiconductor layer having a (0001) plane on the surface and a second compound semiconductor layer having a (000-1) plane on the substrate;
A third compound semiconductor layer formed on the first compound semiconductor layer and having a lattice constant smaller than that of the first compound semiconductor layer, and the second compound semiconductor so as to be in contact with the third compound semiconductor layer A fourth compound semiconductor layer formed on the layer and having a lattice constant smaller than that of the second compound semiconductor layer;
A first electrode for applying a potential to the first compound semiconductor layer formed above the third compound semiconductor layer ; and a second electrode formed above the fourth compound semiconductor layer . A second electrode for applying a potential to the compound semiconductor layer;
A compound semiconductor device comprising: The compound semiconductor device according to claim 1 , further comprising an AlN layer between the first compound semiconductor layer and the substrate. Wherein said first compound semiconductor layer, the second compound semiconductor layer, the third compound semiconductor layer, and the fourth compound according to claim 1 semiconductor layer is characterized in that it is formed of a nitride semiconductor or 2. The compound semiconductor device according to 2. A first compound semiconductor layer and a fifth compound semiconductor layer which are formed above the substrate and have a (0001) plane surface;
Formed between the first compound semiconductor layer and the fifth compound semiconductor layer in a direction parallel to the substrate, in contact with the first compound semiconductor layer and the fifth compound semiconductor layer, and having a surface of (000 -1) a second compound semiconductor layer on the surface;
A third compound semiconductor layer formed on the first compound semiconductor layer and having a lattice constant smaller than that of the first compound semiconductor layer;
A fourth compound semiconductor layer formed on the second compound semiconductor layer so as to be in contact with the third compound semiconductor layer and having a lattice constant smaller than that of the second compound semiconductor layer;
A sixth compound semiconductor layer formed on the fifth compound semiconductor layer so as to be in contact with the fourth compound semiconductor layer and having a lattice constant smaller than that of the fifth compound semiconductor layer;
A source electrode for applying a potential to the first compound semiconductor layer, formed above the third compound semiconductor layer ;
A gate electrode for applying a potential to the second compound semiconductor layer, formed above the fourth compound semiconductor layer ;
A drain electrode for applying a potential to the fifth compound semiconductor layer, formed above the sixth compound semiconductor layer ;
A compound semiconductor device comprising: 5. The compound semiconductor device according to claim 4 , further comprising an AlN layer between the first compound semiconductor layer, the fifth compound semiconductor layer, and the substrate. The first compound semiconductor layer, the second compound semiconductor layer, the third compound semiconductor layer, the fourth compound semiconductor layer, the fifth compound semiconductor layer, and the sixth compound semiconductor layer are nitrided the compound semiconductor device according to claim 4 or 5, characterized in that it is formed from the object semiconductor. A substrate,
A first compound semiconductor layer formed above the substrate and having a (000-1) plane between the (0001) planes in a direction parallel to the substrate;
The first compound semiconductor layer is formed above the first compound semiconductor layer, the surface of the first compound semiconductor layer is above the (0001) plane, the surface is the (0001) plane, and the surface of the first compound semiconductor layer is (000 -1) a second compound semiconductor layer having a (000-1) plane above the plane and having a lattice constant smaller than that of the first compound semiconductor layer;
A gate electrode having a surface formed above the (000-1) plane in the second compound semiconductor layer; and a source electrode formed at a position sandwiching the gate electrode above the (0001) plane. A drain electrode;
Have
A compound semiconductor device, wherein a current flows between the source electrode and the drain electrode through the first compound semiconductor layer due to an electric field effect from the gate electrode.

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