JP2002329871A - Vertical short-channel insulated gate electrostatic induction transistor, and its manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vertical short-channel insulated gate electrostatic induction transistor and the manufacturing method thereof wherein the length of its short channel falls in the range of 1000 Å to 100 Å and it has a very high- speed uniform operational characteristic. SOLUTION: The vertical short-channel insulated gate electrostatic induction transistor has a drain layer 3 comprising an epitaxial single-crystal layer and formed on a principal surface 2 of a substrate 1, a channel layer 4 comprising an epitaxial single-crystal layer having a thickness not larger than 1000 Åand formed on the drain layer, a source layer 5 comprising an epitaxial single- crystal layer and formed on the channel layer, and insulation gates 6, 7 formed on the sidewalls of the drain, channel, and source layers. Further, the channel layer 4 is grown by using a molecular-layer epitaxial method. The gate oxide film of the transistor is formed by a low-temperature CVD using active oxygen. The insulation gate of the transistor is formed by an anisotropic etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a vertical short-channel insulated gate static induction transistor having a high operation speed and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, insulated gate static induction transistors have been used in high frequency amplifiers and integrated circuits that require high driving capability and high operating speed. The insulated gate static induction transistor is proposed by Junichi Nishizawa, one of the present inventors, and is disclosed in, for example, Japanese Patent Publication No. 58-5.
No. 6270 and Japanese Patent Publication No. 3-792. The insulated gate static induction transistor and the insulated gate transistor (for example, a MOS transistor) are equivalent in that they have a source, a channel, and a drain and control a current by a gate voltage, but have different operation principles. That is, the insulated gate static induction transistor forms a potential barrier by the gate voltage and controls the number of carriers traveling from the source to the drain, whereas the insulated gate transistor controls the semiconductor surface carrier at the gate insulating film interface by the gate voltage. It changes the density and controls the number of carriers traveling from the source to the drain.

[0003] Insulated gate static induction transistors are designed so that the effect of the drain electric field extends to the source.
Since a current flows not only at the semiconductor-insulating film interface but also in the substrate, it has excellent characteristics such as unsaturated current-voltage characteristics, large current driving capability, and high speed.
However, there is no limit to the improvement in the data processing speed, and there is a demand for a further increase in the speed of the insulated gate electrostatic induction transistor. To speed up the insulated gate static induction transistor and the insulated gate transistor,
It is effective to shorten the channel length. Currently, in the insulated gate transistor, a short channel insulated gate transistor having a channel length of 1000 ° or less is being put into practical use. The development of gate transistors is also active.

However, the short-channel insulated gate transistor has a limitation on the operation principle that the depletion layer of the source and the depletion layer of the drain approach or connect as the channel is shortened, and the current cannot be controlled by the gate voltage. is there. Further, in a method of manufacturing an insulated gate transistor in which a short channel is formed by using photolithography, a channel length that can be manufactured is determined by an optical wavelength used in photolithography. Requires a short wavelength light source, ie, X-rays. It is difficult to focus or bend the optical path of X-rays. Therefore, X-ray exposure apparatuses are large and expensive, and safety measures against radiation exposure of workers are indispensable.

As described above, shortening the channel of the insulated gate transistor is at a dead end. An electronic device based on a completely new principle of operation, for example, a device such as a single-electron transistor has also been proposed, but it has not been studied. Under these circumstances, the insulated gate static induction transistor forms a potential barrier by the gate voltage and controls the number of carriers traveling from the source to the drain, so that the source depletion layer and the drain depletion layer are connected. Therefore, the phenomenon that the current cannot be controlled does not occur, and there is no restriction on shortening the channel. Also, a molecular layer epitaxial growth method according to the invention of one of the present inventors, Junichi Nishizawa et al.
86), the channel length can be controlled and controlled with a precision of one molecular layer unit, so that a desired short channel length can be realized without requiring an X-ray exposure apparatus. As described above, the insulated gate static induction transistor is in the limelight as a next-generation ultra-high-speed electronic device.

Incidentally, a conventional insulated gate static induction transistor has a structure shown in FIG. FIG. 5 is a diagram showing a method of manufacturing a conventional insulated gate static induction transistor and its structure. The manufacturing steps are as follows. First,
As shown in FIG. 5A, an epitaxial growth layer 52 serving as a channel is grown on a semiconductor substrate 51, and a projection 52 is formed by anisotropic etching. As shown in FIG. 5B, a gate oxide film 54 is formed in the element formation region by masking with the field oxide film 53. Next, FIG.
As shown in (c), a polycrystalline semiconductor 5 serving as a gate electrode
Then, a gate electrode 55 is formed on the side wall of the protrusion 52 by anisotropic etching, and ions are implanted using the gate electrode 55 as a mask to form a drain 56 and a source 57. Then, as shown in FIG. 5D, a passivation film 58 is deposited, an electrode window is opened in the passivation film 58, a drain electrode 56 'and a source electrode 57' are formed, and finally, an impurity activation heat treatment is performed. Do.

In the insulated gate static induction transistor having the above-described structure, a high-temperature process for activating the ion-implanted impurities and a high-temperature process for forming the gate oxide film are indispensable. Are redistributed, and in particular, the impurity of the drain 56 diffuses into the channel 52, and the channel length is shortened. If the channel has a short channel length comparable to the diffusion length of the impurity, the channel length varies due to the impurity diffusion, and therefore,
There is a problem that operating characteristics vary from transistor to transistor.

Although the height of the projection 52 affects the length of the channel, the height of the anisotropic etching cannot correspond to the channel length of 1000 ° or less.
Another problem is that an insulated gate static induction transistor having a constant channel length cannot be manufactured with good reproducibility.

[0009]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention provides an ultra-high-speed vertical short-channel insulated gate static induction transistor having a short channel length from 1000 ° to 100 ° and uniform operating characteristics. It is another object of the present invention to provide a manufacturing method thereof.

[0010]

In order to solve the above-mentioned problems, a vertical short-channel insulated gate static induction transistor according to the present invention comprises a drain layer comprising an epitaxial single crystal layer on a main surface of a substrate; A channel layer formed of an epitaxial single crystal layer having a thickness of 1000 ° or less on the layer, and a source layer formed of an epitaxial single crystal layer on the channel; insulating layers are formed on sidewalls of the drain layer, the channel layer, and the source layer. It has a gate.

According to this structure, since the channel layer is composed of an epitaxial single crystal layer having a high precision in thickness, the precision of the channel length is high, so that the operating characteristics do not vary between transistors, and are uniform. Become. Further, since the channel layer has a thickness of 1000 ° or less, the carrier transit time between the source and the drain is short, and therefore, the operation speed is very high.

The substrate is a single crystal of Si, the main surface is a (100) -oriented plane, the channel layer is a p-type Si epitaxial single crystal, and the source and drain layers are an n-type Si epitaxial single crystal. , The insulating gate is SiO
₂ and Si polycrystal. Further, the substrate is a Si single crystal, the main surface is a (100) oriented plane, the channel layer is an n-type Si epitaxial single crystal, the source layer and the drain layer are a p-type Si epitaxial single crystal, Is characterized by comprising SiO ₂ and Si polycrystal. According to this configuration, a vertical short-channel insulated gate static induction transistor can be manufactured using the most widespread Si semiconductor technology.

In order to solve the above-mentioned problems, a manufacturing method according to the present invention comprises epitaxially growing a drain layer on a main surface of a semiconductor substrate having a specific plane orientation, and epitaxially growing a channel layer for each molecular layer on the drain layer. Then, a source layer is epitaxially grown on the channel layer, a passivation film is deposited on the source layer, and the passivation film is opened in a window to be perpendicular to the main surface, and
A U-shaped groove having a depth reaching the semiconductor substrate is formed.
Depositing a gate oxide layer in the U-shaped groove, depositing a gate electrode layer on the gate oxide film layer, leaving the gate oxide layer and the gate electrode layer on the side walls of the U-shaped groove and forming a gate oxide film; An insulating gate including a gate electrode is formed.

According to this structure, a vertical insulated gate static induction transistor having a gate length of 1000 ° or less can be manufactured accurately without using X-ray photolithography.

In the step of epitaxially growing the channel layer for each molecular layer, the surface of the semiconductor substrate disposed in the vacuum vessel is alternately exposed to a compound gas of a semiconductor element and a compound gas of a dopant element for a predetermined time and evacuated for a predetermined time, It is characterized in that epitaxial growth is performed by controlling growth for each monolayer. According to this configuration, the number of cycles of the step of alternately exposing to the compound gas of the semiconductor element and the compound gas of the dopant element for a predetermined time and evacuating for a predetermined time can be controlled to form a single-molecule layer at a precision of 1000 ° to 100 °. Can be easily and accurately formed. Further, since a single crystal film is grown, high-temperature heat treatment such as activation of impurities is not required.

Further, the step of forming the U-shaped groove is anisotropic plasma etching having a high etching rate in a direction perpendicular to the main surface. According to this configuration, the groove can be formed vertically, and the insulating gate can be arranged vertically in the channel layer.

The step of depositing the gate oxide film layer comprises:
It is characterized by low-temperature CVD in which a compound gas of a semiconductor element and an active oxygen gas are reacted and deposited on the surface of a semiconductor substrate. According to this configuration, since the impurities in the channel layer, the source layer, and the drain layer do not redistribute, the channel length can be formed as designed.

The step of depositing the gate electrode layer uses a low-temperature CVD method in which a compound gas of a semiconductor element is decomposed on the surface of the semiconductor substrate to deposit a semiconductor polycrystal, and is also deposited on the side wall of the U-shaped groove. It is characterized by doing. According to this configuration, a gate electrode layer having a sufficient thickness can be deposited also on the side wall of the U-shaped groove.

Further, the gate oxide film layer and the gate electrode layer
In the step of leaving on the side wall of the U-shaped groove, use an anisotropic plasma etching method in which the etching rate is large in the direction perpendicular to the main surface, and leave on the side wall of the U-shaped groove by utilizing the difference in the thickness of the gate electrode layer. It is characterized by. According to this configuration, since the thickness of the gate electrode deposited on the side wall of the U-shaped groove in the direction perpendicular to the main surface is large, the gate electrode and the gate oxide film are left only on the side wall by controlling the etching time. be able to.

The compound gas of the semiconductor element is Si ₂
H ₆ (disilane). The compound gas of the dopant element is P when the n-type dopant is used.
H ₃ (phosphine), B ₂ H for p-type dopant
₆ (diborane). According to this configuration, p-type, n-type, and i-type channels can be formed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a vertical short-channel insulated gate static induction transistor and a method of manufacturing the same according to the present invention will be described below in detail with reference to FIGS. Note that substantially the same members will be described with the same reference numerals. FIG. 1 is a diagram showing a configuration of a vertical short-channel insulated gate static induction transistor of the present invention, and is a cross-sectional view of a vertical short-channel insulated gate static induction transistor of the present invention. Referring to FIG. 1, a vertical short channel insulated gate static induction transistor according to the present invention includes a semiconductor substrate 1, a drain layer 3 which is an epitaxial single crystal layer on a main surface 2 of the semiconductor substrate 1, and a 1000Å Channel layer 4 which is an epitaxial single crystal layer having the following specific thickness
A source layer 5 which is an epitaxial single crystal layer on the channel layer 4, and a gate oxide film 6 and a gate electrode 7 on the side walls of the drain layer 3, the channel layer 4 and the source layer 5. Has a drain electrode 3 ′ and a source electrode 5 ′ directly above the source layer 5, respectively, and has an insulating protective film 8 that insulates and holds these electrodes.

Further, for example, the semiconductor substrate 1 is a Si single crystal, the main surface 2 is a (100) plane or a plane equivalent thereto, the channel layer 4 is a p-type Si epitaxial single crystal layer, The drain layer 3 and the source layer 5 are n-type Si epitaxial single crystal layers, and the gate oxide film 6 and the gate electrode 7 are made of SiO ₂ and Si polycrystal, respectively. Further, the channel layer 4 may be an n-type Si epitaxial single crystal layer, and the drain layer 3 and the source layer 5 may be a p-type Si epitaxial single crystal layer.

Since the vertical short-channel insulated gate static induction transistor of the present invention having the above-described structure has a very short channel length, the traveling time of carriers traveling in the channel layer 4 can be extremely short. Further, since the channel length is determined by the thickness of the epitaxial single crystal layer, the accuracy of the channel length is extremely high.

Next, a method of manufacturing a vertical short channel insulated gate static induction transistor according to the present invention will be described with reference to a first embodiment. FIG. 2 is a diagram showing a method of manufacturing a vertical short-channel insulated gate static induction transistor according to the present invention. FIG.
As shown in (a), a drain layer 3 is epitaxially grown on a main surface 2 of a Si substrate 1 having a Si (100) plane orientation. The drain layer 3 may be formed by introducing impurities into the Si substrate 1 by thermal diffusion of impurities or ion implantation.
Next, a channel layer 4 is epitaxially grown on the drain layer 3. In order to accurately realize a channel length of 1000 ° to 100 °, the epitaxial growth of the channel layer 4 uses a molecular layer epitaxial growth method.

In the molecular layer epitaxial growth, when the Si substrate 1 on which the drain layer 3 is formed is placed in a vacuum vessel, for example, when the channel layer 4 having an n-type impurity concentration n = 3 × 10 ¹⁹ cm ⁻³ is formed. , crystal growth temperature 510 ° C., exposed for 30 sec the substrate in Si ₂ H ₆ atmosphere at a pressure 4 × 10 ^-2 Pa by introducing Si ₂ H ₆ gas into the vacuum chamber, the Si ₂ H ₆ 2 seconds Exhaust, PH _{3 in} vacuum chamber
PH of 5 × 10 ^-6 Pa by introducing gas
₃ Expose to atmosphere for 10 seconds and evacuate PH ₃ for 2 seconds. By repeating the above process as one cycle, an n-type impurity concentration n = 3 × 10
^A channel layer 4 made of ¹⁹ cm ^-3 Si single crystal is grown.

The thickness of the film grown in one cycle is 1.15 ° on the silicon (001) plane or an equivalent plane.
This film thickness corresponds to a thickness of 85% of one atomic layer. A 1.15 ° thick silicon single crystal layer can be grown for each cycle. That is, when a channel length of 100 ° is formed, the above cycle is repeated about 85 times.

Further, for example, a p-type impurity concentration p = 1 × 1
In the case of forming the channel layer 4 of 0 ²⁰ cm ^-3 , at a crystal growth temperature of 510 ° C., a Si ₂ H ₆ gas is introduced into a vacuum vessel so that the substrate is pressed at a pressure of 4 × 10 ⁻² Pa.
Exposure to a ₂ H ₆ atmosphere for 30 seconds, evacuation of Si ₂ H ₆ for 2 seconds, and introduction of a B ₂ H ₆ gas into a vacuum vessel, exposure to a B ₂ H ₆ atmosphere at a pressure of 5 × 10 ⁻⁵ Pa for 10 seconds. ,
B ₂ H ₆ is evacuated for 2 seconds. By repeating the above steps as one cycle, a channel layer 4 made of a Si single crystal having a desired film thickness and a p-type impurity concentration p = 1 × 10 ²⁰ cm ⁻³ is grown.

To grow non-doped single-crystal Si, the substrate is exposed to a Si ₂ H ₆ atmosphere at a pressure of 4 × 10 ⁻² Pa for 30 seconds by introducing Si ₂ H ₆ gas into a vacuum vessel. , Si ₂ H ₆ is evacuated for 2 seconds. By repeating the above steps as one cycle, a non-doped single-crystal Si layer having a desired film thickness is grown.

Next, the source layer 5 is epitaxially grown. Of course, the epitaxial growth of the drain layer 3 and the source layer 5 may be molecular layer epitaxial growth or normal epitaxial growth. The impurity concentration of the source layer 5 and the drain layer 3 is about 10 ¹⁸ to 10 ²¹ cm ⁻³ . Of course, the conductivity type may be p-type or n-type, 5 is a drain,
3 may be the source.

The channel layer 4 has an impurity concentration of 10 ¹⁶ -1.
0 ²¹ is about cm ^-3, its conductivity type is a conductivity type opposite to the conductivity type of the source 5 and drain 3. Further, the channel layer 4 may have a multilayer structure such as ipi sandwiching the p layer with the non-doped i layer. The channel has a multi-layer structure of ip ⁺ -i, and the thickness of each is 40 °, 20 °, 40 °.
A vertical short-channel insulated gate static induction transistor having a total channel length of 100 ° has also been prototyped, and good characteristics have been confirmed.

As shown in FIG. 2B, a passivation film 8 is deposited, the passivation film 8 is partially removed, a window is opened in an element formation region, and the Si substrate 1 is formed by anisotropic plasma etching or the like. Is etched in a direction perpendicular to the main surface 2 to form a U-shaped groove 10 having a side wall 9 perpendicular to the main surface 2 including the passivation film 8, the source layer 5, the channel layer 4, and the drain layer 3. In the drawings, only half of the U-shaped groove 10 is shown. For the anisotropic plasma etching, for example, plasma etching using PCl ₃ (phosphorus trichloride) is used. The depth of the U-shaped groove 10 only needs to reach the drain layer 3 and may reach the inside of the drain layer 3.

Next, a gate oxide film layer 6 is deposited on the substrate on which the U-shaped groove 10 has been formed. In order to lower the temperature at the time of forming the gate oxide film, the gate oxide film layer 6 is formed by Si ₂ H ₆
20 to 1 using plasma low-temperature CVD with active oxygen
Deposit SiO ₂ to a thickness of 00 °. An example of the deposition conditions is that the substrate temperature is 470 ° C., the Si ₂ H ₆ pressure is 7 × 10 ⁻² P
a, active oxygen pressure is about 10 ^-1 Pa, and high frequency power is 200W.

As shown in FIG. 2C, a polycrystalline silicon layer 7 serving as a gate electrode is formed on the substrate on which the gate oxide film layer 6 is deposited.
Is deposited. The polycrystalline Si layer 7 is deposited at a low temperature of 500 to 5000 ° C. by using a low-temperature plasma CVD method using Si ₂ H _6.
Deposit to a degree.

Next, the deposited Si polycrystalline layer 7 and oxide film layer 6 are etched using anisotropic plasma etching to form a gate oxide film 6 and a gate electrode 7. Anisotropic plasma etching is performed with a PCl pressure of 3 to 30 Pa.
₃ Performed by plasma etching. This anisotropic plasma etching has a large etching rate in a direction perpendicular to the main surface 2 of the Si substrate 1. Since the film thickness in the direction perpendicular to the main surface 2 in the side wall 9 portion of the Si polycrystalline layer 7 is larger than the deposited film thickness by the thickness of the passivation film 8, the anisotropic etching rate in the direction perpendicular to the main surface 2 is large. When the etching is performed by controlling the etching time, the gate oxide film layer 6 and the polycrystalline silicon layer 7 can be left only on the side wall 9, and an insulated gate composed of the gate oxide film 6 and the gate electrode 7 can be formed. .

Next, as shown in FIG. 2D, a passivation film 8 'is deposited on the substrate on which the insulated gate is formed, and a contact hole is opened to form a source electrode 5' and a drain electrode 3 '. Complete.

According to this manufacturing method, a vertical short-channel insulated gate static induction transistor can be manufactured by the most widely used Si semiconductor technology. Further, a vertical short-channel insulated gate static induction transistor having a gate length of 1000 ° or less can be manufactured accurately without using X-ray photolithography. Further, since the U-shaped groove having the vertical side wall is formed, the insulating gate can be formed vertically in the channel layer. Further, since the channel is formed by the molecular layer epitaxial growth method, a channel having a length of 1000 ° to 100 ° can be easily and accurately formed.

A low-temperature CV for depositing a gate oxide film layer
In the step D, since the temperature is low, the channel, source and drain impurities are not redistributed, and the channel length can be formed as designed. Further, since the step of depositing the gate electrode layer is a low-temperature CVD method, impurities do not redistribute and the channel length does not change. Also, since the etching of the gate electrode is a self-aligned anisotropic etching,
The gate electrode and the gate oxide film can be left on the side wall.

Next, a second embodiment will be described. FIG.
A low power consumption vertical short formed using the manufacturing method of the present invention.
Method for manufacturing channel insulated gate static induction transistor and
It is a figure showing the composition. Example 1 is different from Example 1 in FIG.
As shown, a sidewall is formed immediately before the gate oxide film layer 6 is deposited.
The only difference is that the wall channel layer 31 is deposited. Sa
The wall channel layer 31 is formed of a molecular layer epitaxial layer.
Using a growth method, an impurity concentration of 10¹²-10 ¹⁶cm^-3No
Doped silicon epitaxial single crystal layer from 20 to 10
Grow 0 °. Low power vertical short channel insulated gate
The static induction transistor has a sidewall channel 31.
And appropriate adjustment of the impurity concentration of the channel layer 4 on the bulk side and
With the shortening of the channel without lowering the operating speed
The off-state leakage current can be reduced,
The power can be reduced.

Next, a third embodiment will be described. FIG.
It is a figure which shows the manufacturing method and structure of the vertical short channel insulated gate static induction transistor formed on the SOI substrate using the manufacturing method of this invention. SOI (Silicon o
n Insulator) is formed on the Si substrate 41 by SiO.
_This is a substrate having a Si single crystal layer 43 via _two layers 42. The first embodiment is different from the first embodiment only in that the Si single crystal layer 43 of the SOI substrate is used for the drain layer as shown in FIG. The vertical short channel insulated gate static induction transistor formed on the SOI substrate has good electrical isolation between the substrate and the device layer, so that the parasitic capacitance of the gate is reduced and the operation speed is further improved. In addition, it has the effect of improving the withstand voltage and radiation resistance of the device, and can be used for integrated circuits and the like that require high environmental reliability.

[0040]

As can be understood from the above description, according to the vertical short-channel insulated gate static induction transistor of the present invention and the method of manufacturing the same, an ultra-high-speed vertical short-channel insulated gate having uniform operating characteristics. An electrostatic induction transistor can be realized. According to the present invention, the present invention is extremely useful if used as a next-generation ultra-high-speed electronic device in an ultra-high-speed amplifier circuit, an integrated circuit, or the like.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a vertical short-channel insulated gate electrostatic induction transistor of the present invention.

FIG. 2 is a diagram illustrating a method for manufacturing a vertical short-channel insulated gate static induction transistor according to the present invention.

FIG. 3 is a diagram showing a method of manufacturing a low power consumption vertical short channel insulated gate static induction transistor formed by using the manufacturing method of the present invention and its configuration.

FIG. 4 is a diagram showing a method of manufacturing a vertical short-channel insulated gate static induction transistor formed on an SOI substrate by using the manufacturing method of the present invention, and a configuration thereof.

FIG. 5 is a diagram showing a method and a structure of a conventional insulated gate static induction transistor.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 main surface 3 drain layer 3 'drain electrode 4 channel layer 5 source layer 5' source electrode 6 gate oxide film 7 gate electrode 8 passivation film 8 'passivation film 9 side wall 31 side wall channel 41 Si substrate of SOI substrate 42 SOI Substrate SiO ₂ 43 SOI substrate Si single crystal layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 H01L 29/78 626A // H01L 21/205 658E (72) Inventor Toru Kurabayashi Minato-ku, Tokyo No. 31-19, Shiba 2--19, Communication and Broadcasting Corporation (72) Inventor Toru Oizumi No. 31-19, Shiba 2-chome, Minato-ku, Tokyo (72) Kyozo Kanemoto, Inventor Kyozo Kanamoto 2-Chome, Minato-ku, Tokyo 31-19 Inside the Communications and Broadcasting Corporation (72) Inventor Junichi Nishizawa 2-31-13 Shiba, Minato-ku, Tokyo F-Term inside the Communications and Broadcasting Organization (Reference) 5F045 AA00 AA15 AB02 AB03 AB32 AC01 AC19 AD08 AD09 AE13 AF03 BB16 CA00 DA51 HA13 5F102 FB01 GB04 GC09 GD10 GJ03 GJ10 GR01 HC01 HC07 HC16 5F110 AA01 CC09 DD05 DD13 EE09 EE22 EE45 FF02 FF30 GG02 GG12 GG25 GG32 GG34 GG42 HJ04 HJ11 HJ13 HJ15 QHK32 HK13 HK09 HK13 HK09 HK13 HK13

Claims (11)

[Claims] A drain layer comprising an epitaxial single crystal layer on a main surface of a substrate;
A channel layer comprising an epitaxial single crystal layer having a thickness of not more than Å, and a source layer comprising an epitaxial single crystal layer on the channel layer, and an insulated gate on the sidewalls of the drain layer, the channel layer and the source layer. A vertical short channel insulated gate static induction transistor characterized by having: 2. The substrate is a single crystal of Si, and a main surface is a (100) plane or a plane equivalent to the (100) plane.
The channel layer is a p-type Si epitaxial single crystal layer,
_2. The vertical short channel insulated gate static induction transistor according to claim 1, wherein the source layer and the drain layer are n-type Si epitaxial single crystal layers, and the insulated gate is made of SiO ₂ and polycrystalline Si. 3. The substrate is a single crystal of Si, and a main surface is a (100) plane or a plane equivalent to the (100) plane,
The channel layer is an n-type Si epitaxial single crystal layer,
The vertical short channel insulated gate static induction transistor according to claim 1, wherein the source layer and the drain layer are p-type Si epitaxial single crystal layers, and the insulated gate is made of SiO ₂ and polycrystalline Si. 4. A drain layer is epitaxially grown on a main surface of a semiconductor substrate having a specific plane orientation, a channel layer is epitaxially grown for each molecular layer on the drain layer, and a source layer is epitaxially grown on the channel layer. A passivation film is deposited on the source layer, and a window is formed in the passivation film to form a U-shaped groove perpendicular to the main surface and to a depth reaching the semiconductor substrate. A gate oxide layer is deposited, a gate electrode layer is deposited on the gate oxide layer, and the gate oxide layer and the gate electrode layer are separated from each other by leaving the gate oxide layer and the gate electrode layer on the side walls of the U-shaped groove. A method of manufacturing a vertical short-channel insulated gate static induction transistor, comprising forming an insulated gate. 5. The step of epitaxially growing each molecular layer of the channel layer, wherein the surface of the semiconductor substrate disposed in a vacuum vessel is alternately exposed to a compound gas of a semiconductor element and a compound gas of a dopant element for a predetermined time and evacuated for a predetermined time. And
The method for manufacturing a vertical short-channel insulated gate static induction transistor according to claim 4, wherein the epitaxial growth is performed while controlling the growth for each monolayer. 6. The method according to claim 4, wherein the step of forming the U-shaped groove is an anisotropic plasma etching having a large etching rate in a direction perpendicular to the main surface. A method for manufacturing a channel insulated gate static induction transistor. 7. The step of depositing the gate oxide layer comprises:
5. The vertical short-channel insulated gate static induction transistor according to claim 4, wherein the low-temperature CVD is performed by reacting a compound gas of a semiconductor element and a gas of active oxygen on the surface of the semiconductor substrate to deposit. Production method. 8. The step of depositing the gate electrode layer uses a low-temperature CVD method in which a compound gas of a semiconductor element is decomposed on the surface of the semiconductor substrate to deposit a semiconductor polycrystal, and the side wall of the U-shaped groove is formed. 5. The method according to claim 4, wherein the step of depositing the vertical short-channel insulated gate static induction transistor is performed. 9. The method according to claim 1, wherein the gate oxide film layer and the gate electrode layer are formed of U
The step of leaving on the side wall of the U-shaped groove uses an anisotropic plasma etching method in which an etching rate is large in a direction perpendicular to the main surface, and leaves on the side wall of the U-shaped groove due to a difference in thickness of the gate electrode layer. The method of manufacturing a vertical short-channel insulated gate static induction transistor according to claim 4, characterized in that: 10. The compound gas of the semiconductor element is Si
9. The method for manufacturing a vertical short-channel insulated gate static induction transistor according to claim 5, wherein the transistor is ₂ H ₆ (disilane). 11. The compound gas of the dopant element,
_6. The vertical short channel insulated gate static induction transistor of claim 5, wherein the n-type dopant is PH ₃ (phosphine) and the p-type dopant is B ₂ H ₆ (diborane). Production method.