WO2007122800A1 - Field effect transistor - Google Patents

Abstract

Disclosed is an HJFET (110) comprising a channel layer (12) made of InyGa1-yN (0 ≤ y ≤ 1), a carrier supply layer (13) made of AlxGa1-xN (0 ≤ x ≤ 1) which is formed on the channel layer (12) and includes at least one p-type layer, a source electrode (15S) so formed on the carrier supply layer (13) as to be opposite to the channel layer (12) across the p-type layer, a drain electrode (15D) and a gate electrode (17). The Al composition ratio x of the carrier supply layer (13), the thickness t of the p-type layer, the concentration NA of the impurities and the activation rate η satisfy the following relation. 5.6 × 1011x < NA × η × t [cm-2] < 5.6 × 1013x

Description

 Specification

 Field effect transistor

 Technical field

 TECHNICAL FIELD [0001] The present invention relates to a field effect transistor, and more particularly, to a heterojunction field effect transistor (HJ FET) including an I I I group nitride semiconductor as a material.

 Background art

 Conventional Hetero Junction Field Effect Transistors (HJ FETs) are conventionally described in Non-Patent Document 1 and Patent Document 1.

 FIG. 15 is a cross-sectional view showing the configuration of the H J FET described in Non-Patent Document 1.

 In the HJFET shown in FIG. 15, on the sapphire substrate 200, a buffer layer 201, a channel layer 202 made of gallium nitride (G a N), a carrier supply layer made of aluminum nitride gallium (AIG a N) 203 are stacked in this order.

 [0004] Further, in this HJFET, due to the piezoelectric polarization effect and the spontaneous polarization effect caused by the difference in lattice constant between G a N and AIG a N, the channel layer 202 is located near the interface with the carrier supply layer 203. A two-dimensional electron gas 204 is formed.

 In addition, a source electrode 205 S and a drain electrode 205 D are formed on the carrier supply layer 203 and are in ohmic contact. A gate electrode 207 is formed in a region sandwiched between the source electrode 205 S and the drain electrode 205 D on the AIG a N carrier supply layer 203, and Schottky contact is made at the interface 203 A with the carrier supply layer 203. It has been.

 [0006] On the carrier supply layer 203 and the gate electrode 207, a surface protective film 208 made of silicon nitride (SiN) is provided.

[0007] Further, Patent Document 1 describes a normal system having a channel layer made of a non-doped G a N layer and a barrier layer made of AIG a N provided in contact with the channel layer. HJFETs are listed. In addition, it describes that a P-type semiconductor layer containing a p-type impurity is provided in a barrier layer under a gate electrode in order to realize normally-off in HJFFT, which is normally normally on.

 Non-Patent Document 1: Y. Ando et al., Technical Digest of Ob-International Electron Device Meeting (Technique Ic ID Igestof International Electron Device Meeting, pp. 3 8 1 2001 Patent Document 1: Japanese Patent Application Laid-Open No. 2004-273486

 Disclosure of the invention

 Problems to be solved by the invention

 [0008] By the way, at the Schottky interface of Group III nitride semiconductors such as G a N and AIG a N, the influence of Fermi level pinning is small, so the barrier height is the work function of the metal and the electron affinity of the semiconductor. It is known to be determined by the difference. For this reason, for example, the height of the Schottky barrier in A I G a N having an A I composition ratio of 0.2 is relatively low, about 0.8 to 1. O e V, although it slightly depends on the electrode metal. As a result, as in the HJFET described above with reference to FIG. 15, the group II nitride HJFET using AI 03 1 \ 1 as the carrier supply layer has a high gate leakage current density and a high operating drain voltage. There was a problem of being restricted.

 [0009] In addition, in Patent Document 1 described above in the background art section, since the normally-off structure, that is, the threshold voltage is positive, if the p-type semiconductor layer is formed in a region other than the region immediately below the gate electrode, The channel concentration in the formation region was reduced, and current was difficult to flow.

 [0010] Further, since the p-type impurity is introduced only in the vicinity of the region directly under the gate electrode, the manufacturing process is complicated.

 Means for solving the problem

 [0011] According to the present invention,

A channel layer consisting of I n _y G a, _ _y N (0≤ y≤ 1), Provided on the channel layer, and _{AI X G ai. X N (} 0≤x≤ 1) a carrier supplying layer comprising at least one layer of p-type layer,

 A source electrode, a drain electrode and a gate electrode which are opposed to the channel layer through the P-type layer and are provided on the carrier supply layer;

 Have

The AI composition ratio x of the carrier supply layer, the thickness t of the p-type layer, the impurity concentration N _A and the activation rate 77 are:

[0012] [Equation 1]

5.6xlO ⁿ x <N _A 7 xt [cm- ² ] <5.6xl0 ¹³

[0013] A field effect transistor satisfying the above is provided.

[0014] Further, according to the present invention,

A channel layer consisting of I n _y G a, _ _y N (0≤ y≤ 1),

A carrier supply layer formed of AI _X G a, _ _x N (0≤x≤ 1) including at least one p-type layer provided on the channel layer;

 A source electrode, a drain electrode and a gate electrode which are opposed to the channel layer through the P-type layer and are provided on the carrier supply layer;

 Have

 A two-dimensional electron gas is generated in the channel layer;

And AI composition ratio _X1 in the interface between the AI composition ratio X _a and before SL channel layer at an interface between the gate electrode of the Kyaria supply layer,

 X a, X 1

 And

The AI composition ratio x _a , the thickness t of the p-type layer, the impurity concentration NA, and the activation rate 77 are:

[001 6] を満たす電界効果トランジスタが提供される。 [0015] [Equation 2]

A field effect transistor is provided that satisfies [001 6].

 [001 7] In the present invention, the potential barrier against electrons under the gate electrode is increased, and the gate leakage current can be reduced. In addition, the decrease in the maximum drain current is suppressed within the specified value compared to the case where no p-type impurity is driven.

 [001 8] In the present invention, as described later, the threshold voltage of the field effect transistor is negative. In contrast to the HJFET described in Patent Document 1 described above in the Background Art section where the threshold voltage is positive, according to the present invention, even when the source electrode and the drain electrode are provided on the p-type layer, Two-dimensional electron gas is efficiently generated in the entire carrier supply layer, and current can be supplied stably.

 [001 9] Furthermore, in the present invention, a p-type layer exists between the source and the gate and between the gate and drain, which are easily affected by the surface charge. For this reason, the effect of the surface charge can be partially shielded by the p-type layer, and the current-voltage characteristic is stable with respect to the surface state. For example, the phenomenon that the drain current amplitude decreases when a large amplitude voltage is input to the gate electrode, the so-called current collab phenomenon, is suppressed.

 In the present invention, a part of the gate electrode may be embedded in the carrier supply layer. In the present invention, a buried gate structure in which a part of the p-type layer is removed by etching may be used. In this case as well, the same effect can be obtained by adopting a configuration in which the sheet impurity concentration of the P-type layer existing between the recess portion in contact with the gate electrode and the channel layer satisfies the above-described relationship.

 [0021] That is, according to the present invention,

A channel layer consisting of I n _y G a _{y y} (0≤ y≤ 1),

Provided on the channel layer, and _{AI X G ai. X N (} 0≤x≤ 1) a carrier supplying layer comprising at least one layer of p-type layer,

A source electrode, a drain electrode, and a gate electrode that face the channel layer through the P-type layer and are provided on the carrier supply layer; and the gate electrode forms a part of the carrier supply layer. Rise formed by removing A field effect transistor formed in contact with the gate portion,

 The thickness t of the p-type layer between the recess and the channel layer, the impurity concentration NA, and the activation rate?

5. 6 X 1 0 ¹¹ X <Ν _Α Χ η xt [cm " ² ] <5.6 x 1 0 ¹³ x

 A field effect transistor satisfying the above is provided.

[0022] Further, according to the present invention,

A channel layer consisting of I n _y G a, _ _y N (0≤ y≤ 1),

A carrier supply layer comprising AI _X G a, _ _x N (0≤ x≤ 1) provided on the channel layer and including at least one p-type layer;

 A source electrode, a drain electrode, and a gate electrode that face the channel layer through the P-type layer and are provided on the carrier supply layer; and the gate electrode forms a part of the carrier supply layer. A field effect transistor formed in contact with the removed recess portion,

The AI composition ratio at the interface between the carrier supply layer and the gate electrode is smaller than the AI composition ratio _{X1 at} the interface with the channel layer, and the AI composition ratio x _a , the AI composition ratio χ, the recess portion and the channel The thickness t of the vertical layer, the impurity concentration N _A and the activation rate?

^{5. 6 X 1 0 11 X!} <N A X 77 X t [cm- 2] +5. 6 X 1 0 13 (x _{"x a) <5. 6 X} 1 0 13 X!

 A field effect transistor satisfying the above is provided.

[0023] It should be noted that any combination of these components, or a conversion of the expression of the present invention between methods, devices, etc. is also effective as an aspect of the present invention.

 The invention's effect

 As described above, according to the present invention, the gate leakage current of the I I I group nitride system H J FE T can be reduced.

 Brief Description of Drawings

[0025] The above and other objects, features and advantages are The invention will be further clarified by suitable embodiments and the following drawings attached thereto.

 FIG. 1 is a cross-sectional view showing a cross-sectional structure of H J F E T in a mobile phone.

 FIG. 2 is a diagram showing a potential distribution of H J F E T in an example.

 FIG. 3 is a graph showing p-type impurity concentration dependence of H J F E T gate current in an example.

 FIG. 4 is a graph showing the p-type impurity concentration dependence of the maximum drain current of H J F E T in an example.

 FIG. 5 is a graph showing the dependence of the threshold voltage of H J FET on the p-type impurity concentration in an example.

 FIG. 6 is a cross-sectional view showing a cross-sectional structure of H J F E T in an example.

 FIG. 7 is a cross-sectional view showing a cross-sectional structure of H J F E T in an example.

 FIG. 8 is a cross-sectional view showing a cross-sectional structure of H J F E T in an example.

 FIG. 9 is a cross-sectional view showing a cross-sectional structure of H J F E T in an example.

 FIG. 10 is a cross-sectional view showing a cross-sectional structure of H J F E T in an example.

 FIG. 11 is a cross-sectional view showing a cross-sectional structure of H J F E T in an example.

 FIG. 12 is a cross-sectional view showing a cross-sectional structure of H J F E T in an example.

 FIG. 13 is a cross-sectional view showing a cross-sectional structure of H J F E T in an example.

 FIG. 14 is a cross-sectional view showing a cross-sectional structure of H J F E T in an example.

 FIG. 15 is a cross-sectional view showing a cross-sectional structure of a conventional H J F E T.

 BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, common components are given the same reference numerals, and explanations are omitted as appropriate.

[0028] First, in order to facilitate understanding of the present invention, an outline of the present invention will be described.

FIG. 1 is a cross-sectional view showing the configuration of the HJFET in the present embodiment. In the HJFET 110 shown in Fig. 1, the substrate 10 made of silicon carbide (SiC) 10 Above, buffer layer 1 1 consisting of aluminum nitride (AIN) layer, channel layer 1 2 consisting of I n _y G 3 N (0≤ y≤ 1) and AI _X G _ai - _x N (0≤ x≤ 1) A carrier supply layer 13 made of is provided in this order.

In the present embodiment, the channel layer 12 is composed of an undoped G a N layer.

[0031] The carrier supply layer 13 is provided on the channel layer 12 and includes at least a P-type layer. In the present embodiment, the carrier supply layer 13 is made of p-type Al _x Ga ^ N. This p-type Al _{x Ga i} -xN layer is provided over the entire region between the source and drain as well as in contact with the channel layer 12.

[0032] In HJFET 110, the channel layer 12 near the interface with the carrier supply layer 13 due to the piezoelectric and spontaneous polarization effects caused by the difference in lattice constant between G a N and AIG a N In addition, a two-dimensional electron gas 14 is formed. The HJ FET 1 1 0 is configured so that a two-dimensional electron gas is generated in the channel layer in a region between the source electrode and the gate electrode and a region between the gate electrode and the drain electrode without applying a voltage to the gate electrode. It has a configuration to generate. That is, the threshold voltage of H J FE T 1 1 0 is negative.

Further, the source electrode 15 S, the drain electrode 15 D, and the gate electrode 17 face the channel layer 12 through the P-type layer and are provided on the carrier supply layer 13.

 Specifically, a source electrode 15 S and a drain electrode 15 D are formed on a carrier supply layer 13 made of p-type AIG a N, and ohmic contact is made with the carrier supply layer 13, respectively. It has been taken. Gate electrode 17 is provided in the same plane as source electrode 15 S and drain electrode 15 D, and the bottom surface of gate electrode 17 is the same as the bottom surfaces of source electrode 15 S and drain electrode 15 D Located at the level.

[0034] Further, a gate electrode 17 is provided at a portion sandwiched between the source electrode 15S and the drain electrode 15D on the carrier supply layer 13 and the carrier supply layer 1 3 is provided at the interface 13A. And Schottky contact. By adjusting the potential of the gate electrode 17 and modulating the concentration of the two-dimensional electron gas 14, a transistor is obtained. Works.

 A surface protective film 18 made of SiN is provided on the carrier supply layer 13 on which the gate electrode 17 is formed from the upper surface of the source electrode 15 S to the upper surface of the drain electrode 15 D. The region between the source electrode 15 S and the drain electrode 15 D is covered.

 [0036] In HJFET 110, the AI composition ratio x of the carrier supply layer 13 made of p-type AIG a N, the thickness t of the carrier supply layer 13 made of p-type AIG a N, and the p-type AIG a Impurity concentration NA in N and activation rate 7?

 [Equation 3]

_{^{5.6xlO n x <N A 7 xt}} [cm- 2] meet the <5.6xl0 ^13.

 This point will be described below.

[0037] First, the AIG a NG a N heterointerface has a fixed charge due to spontaneous polarization between group III and N atoms and piezo polarization based on the lattice constant difference between AIG a N and G a N. Will occur. It is known that the surface density σ _{こ の} of this polarization charge can be approximated by the following equation (1) as a function of the AI composition ratio x of the AIG a N layer.

[0038] [Equation 4] σ _ρ = + qx (0

層の厚さをセ、 p型不純物の濃度を N_A、 活性化率 を 77とすると、 イオン化不純物電荷の面密度 σ_Αは下記式 （2) によって表わ される。 [0039] In the above equation (1), q (= 1.6 X 1 0 " ¹⁹ C) is an elementary charge, and a (= 5.6 X 1 0 ¹³ cm" ² ) is a proportional coefficient. The sign of the polarization charge is positive for the AIG a N interface on G a N and negative for the G a N interface on AIG a N for normal Ga plane growth. Meanwhile, P-type AI

When the layer thickness is _C , the p-type impurity concentration is N _A , and the activation rate is 77, the surface density σ _の of the ionized impurity charge is expressed by the following equation (2).

[0040] [ _Equation 5] σ _Α A = one — q nN _A 7} i (2)

 [0041] Note that the thickness t of the p-type AIGAN layer is the thickness of the carrier supply layer 13 at the contact portion with the gate electrode 17. In the HJFET 1 1 0 shown in FIG. 1, the gate electrode 1 7 is the same as the source electrode 15 S and the drain electrode 15 D. The source electrode is provided in the same plane and includes the contact with the gate electrode 17. A carrier supply layer 13 having a uniform thickness is provided in the entire region between 15 S and the drain electrode 15 D. As will be described later, when the gate electrode has a structure formed by removing a part of the carrier supply layer, that is, a so-called gate recess structure, the thickness t of the p-type AIG a N layer is reduced in the recess portion. This is the thickness of the carrier supply layer 13 at the contact surface with the gate electrode formed in contact.

 [0042] Here, since the threshold voltage of HJFET 110 is negative, two-dimensionally, in the vicinity of the interface between channel layer 12 and carrier supply layer 13 in the state where no voltage is applied to gate electrode 17 Electron gas 14 is generated.

[0043] In this case, if the absolute value of the ionized impurity charge density σ _Α (sign: negative) is lower than the absolute value of the polarization charge density σ _Ρ (sign: positive), that is, the configuration satisfying the following formula (3): If there is, a two-dimensional electron gas 14 is generated near the interface between the channel layer 12 made of G a G and the carrier supply layer 13 made of AIG a N.

[0044] [Equation 6]

 [0045] When this condition is rewritten using the above formulas (1) and (2), the following formula (

 3 ')

[0046] [Equation 7]

[0047] Further, the carrier supply layer 13 made of AIG a N is doped with a p-type impurity. By doing so, an upwardly convex conduction band profile is obtained. For this reason, it is expected that the gate tunnel current can be suppressed by increasing the energy barrier against electrons. However, if the P-type impurity concentration is too low, the energy barrier thickness may be insufficient and the gate leakage current suppression effect may not be obtained.

. On the other hand, if the p-type impurity concentration is too high, the two-dimensional electron gas 14 may not be formed. However, by adopting a configuration that satisfies the above formula (3) or (3,), Electron gas can be generated.

[0048] Thus, by clarifying the relationship between the element structure parameters and the element characteristics by numerical calculation, a p-type impurity concentration condition for reducing the gate tunnel current was designed.

 [0049] First, the conduction band energy distribution was calculated by solving the Poisson equation. Figure 2 shows an example of the conduction band energy distribution in the direction perpendicular to the calculated substrate. FIG. 2 shows the distance from the interface between the carrier supply layer 13 and the gate electrode 17 (distance = 0), and the longer the distance, the farther away from the gate electrode 17.

[0050] In FIG. 2, the effective impurity concentration in the carrier supply layer 13 made of AIG a N, that is, N _A x? 7, which is the product of the P-type impurity concentration and the activation rate, is 0 cm− ^3. showed 5 X 1 0 ¹⁷ cm- ³ and 1 X 1 0 ¹⁸ calculation results of triplicate c ^m-3. Here, the AI composition ratio x of the AIG a N layer was assumed to be 20%.

In FIG. 2, the result of N _A x? 7 = 0 cm- ³ corresponds to the case of the conventional configuration shown in FIG. As shown in Fig. 2, when N _A X? 7 = 0 cm- ³ , a linear conduction band energy distribution is obtained in the AIG a N layer. As a result, the electron tunnel barrier at the gate interface becomes thinner and the tunnel current increases.

[0052] On the other hand, in the case of N _A x 7? = 5 X 1 0 ¹⁷ cm- ³ , an upward convex conduction band energy distribution is obtained due to negative ionized impurity charges. As a result, the electron tunnel barrier at the gate interface becomes thicker and the tunnel current decreases. In the case of _{N A X 77 = 1 X 1} 0 18 cm_ 3 becomes thick electron tunneling barrier is et at the gate interface is expected that the tunnel current decreases further.

[0053] Next, based on the calculation result of the conduction band energy distribution, it consists of AIG a N The tunnel current density flowing through the carrier supply layer 13 was calculated.

[0054] Fig. 3 shows the dependence of the gate leakage current N _A x? 7 estimated from the tunnel current density. The AI composition ratio X showed three results of 15%, 20%, and 25%. Here, the thickness of the p-type AIG a N layer was assumed to be t = 20 nm.

[0055] From Fig. 3, it was shown that the reverse gate leakage current sharply decreased on the high concentration side, with the point indicated by the black circle (image) in the figure as the boundary. Therefore, this point is used as the lower limit of N _A x 7 ?. From this equation (1) and equation (2), | σ _Α | = | σ _Ρ | 1 00

This is a condition. As a result, when N _A x? 7 is high concentration, the reverse gate current decreases rapidly. From this, the following equation (4) or (4 ′) is obtained as a condition for effectively reducing the gate leakage current. The following formulas (4) and (4 ′) can be rewritten from the above formulas (1) and (2).

[0056] [Equation 8]

[0057] [Equation 9] "cm— ² ]> 5.6x10

[0058] By combining the above equations (3 ') and (4'), a two-dimensional electron gas can be formed in the channel, and the conditions for obtaining the gate current suppressing effect are as follows.

5. 6 X 1 0 ¹¹ X <Ν _Α Χ η xt [cm " ² ] <5.6 x 1 0 ¹³ x

[0059] Further, in order to further reduce the gate leakage current, a configuration satisfying the following formula (5) may be used. In this case, the reverse gate current decreases to about 110 times that of undoped. Moreover, when the following formula (5) is rewritten using the above formulas (1) and (2), the following formula (5 ′) is obtained.

[0060] [Equation 10] σ A | σ / 10 [0061] [Equation 11]

W 4cm -―21] ^> c5.6, x, 1l Λ01 "2x (5

[0062] Next, the dependence of the maximum drain current I _max on Χ _Α Χ 77 was calculated.

Figure 4 shows the dependence of the calculated I _max on Χ _Α Χ 77. In FIG. 4, three results are shown: AI composition ratio X force << 15%, 20% and 25%. The thickness of the p-type AIG a N layer, which is the carrier supply layer 13, was assumed to be t = 20 nm.

[0063] From FIG. 4, _ax decreases as N _A x 7? Increases. However, in in FIG. 4, white circles conditions displayed by (〇), i.e. _{| σ Α | = | σ Ρ} | as the conditions that 2 to become boundary, it than if the low concentration reduction rate I _max 50% It was shown to be suppressed within. If this condition is used as the upper limit of N _A x 7 ?, the reduction in I _max can be reduced to 50% or less, so that a significant decrease in current drive capability can be suppressed more reliably. This condition is shown in the following formula (6) or (6 ′). These equations can be rewritten using the above equations (1) and (2).

2 (6) [0064] [Equation 12]

2 (6)

[0065] [Equation 13]

[0066] From the viewpoint of further reducing the amount of decrease in I max, it is preferable to satisfy the conditions represented by the following formula (7) or (7 '). In this case, it was shown that the decrease rate of I _max was suppressed within 20%.

[0067] [Equation 14]

[0068]

[0069] Finally, to calculate the N _A x? 7-dependent threshold voltage V _th.

Figure 5 shows the calculated V _th dependence on N _A x? 7. In Figure 5, the AI composition ratio

Three results of X force << 1 5%, 20% and 25% were shown. P-type A I

The thickness of the G a N layer was assumed to be t = 20 nm.

[0070] From FIG. 5, V _th moves to the positive side as N _A x 7? Increases. In Figure 5, the formula (

4) Critical point of

| σ _Α | = | σ _Ρ | 1 00

 These conditions are indicated by black circles. Also, the critical point of equation (6), that is,

| σ _Α | = | σ _Ρ | / 2

 These conditions are indicated by white circles.

 [0071] Further, from FIG. 5, a range satisfying the equations (4) and (6), that is,

| σ _Ρ | 1 00 <| σ _Α | <| σ _Ρ | 2

It can be seen that V _th is negative in the range satisfying.

[0072] Under the condition that _Vth is negative, the two-dimensional electron gas 14 is generated even if no positive charge is applied to the gate electrode 17; therefore, not only under the gate electrode 17 but also the source electrode A two-dimensional electron gas 14 is also generated in the channel layer 1 2 between 15 S and the gate electrode 17. Similarly, a two-dimensional electron gas 14 is also generated in the channel layer 12 between the gate electrode 17 and the drain electrode 15D.

 [0073] In the present embodiment, unlike the case of Patent Document 1 described above in the background art section, the threshold voltage is negative. Therefore, the p-type impurity is not selectively doped only under the gate electrode 17. However, since it operates as a transistor, the process is simplified, leading to cost reduction in device fabrication and improvement in yield.

Furthermore, in the present embodiment, a p-type layer also exists between the source and the gate and between the gate and the drain that are easily affected by the surface charge. For this reason, the effect of surface charge can be partially shielded by the p-type layer, and the current-voltage characteristics are stable against the surface state. Become. For example, the current collab phenomenon is suppressed.

[0075] From the above considerations, it can be seen that the gate leakage current can be effectively suppressed by adopting the configuration satisfying the above formula (4) or (4 '). Furthermore, the range of N _A x η for further suppressing the reduction of I _max while suppressing the gate leakage current is expressed by the following formula (8) or (8 ′).

[0076] [Equation 16]

[0077] [Equation 17]

[0078] By adopting a configuration that satisfies the above formula (8) or (8 '), the potential barrier for electrons under the gate electrode 17 is increased, the gate leakage current is reduced, and a predetermined maximum drain current and Group III nitride HJ FET with threshold voltage is obtained. As a result, the high-frequency performance and power performance of the HJ FET can be further improved. As described above with reference to FIG. 5, the threshold voltage V _th is negative in the configuration satisfying the following formula (8) or (8 ′).

[0079] Further, a more preferable range of N _A X? 7 is represented by the following formula (9) or (9 ').

[0080] [Equation 18]

 [0081] [Equation 19]

5.6xl0 ¹ <cm “ ^J ] <1.12 10 In the above, the case where the p-type impurity concentration in the carrier supply layer 13 composed of the AIG a N layer is substantially uniform has been described. [0083] If N _A and 77 inside the carrier supply layer composed of the AIG a N layer are non-uniform, in the above formulas (8 ') and (9'), the portion of N _A x ?? xt Can be calculated in the same way by using the more generalized equations (8 '') and (9 '').

 [0084] [Equation 20]

[0085] [Equation 21]

^{5.6Χ10 Π Λ <<2.8xl0 13 Jf} (8 ")

[0086] [Equation 22]

Where N _A (y) is the impurity concentration distribution,? 7 (y) is the activation rate distribution, and the integration is performed in the direction perpendicular to the substrate. The integration range is from the interface between the AIG a N carrier supply layer 13 and the channel layer 12 to the interface with the gate electrode 17. Note that in the HJ FET 110 in FIG. 1, N _A (y) and? 7 (y) are constant values N _A and 77, respectively, so that the integrated value is Ν _Α Χ η xt.

 [0088] FIG. 1 shows a configuration in which the AI composition ratio in the p-type layer is constant in the stacking direction. Next, the case where the AI composition ratio in the p-type layer is not constant in the stacking direction will be described with reference to FIG.

 FIG. 6 is a cross-sectional view showing another configuration of the H J FET in the present embodiment. The HJ FET 120 shown in FIG. 6 is the same as the HJFET 110 shown in FIG. 1 except that the carrier supply layer 13 consisting of a p-type AIG a N layer is replaced with a carrier supply layer 23 consisting of a p-type gradient composition AIG a N layer. It has been replaced with.

[0089] Here, the AI composition ratio x of the carrier supply layer 23 composed of the AIG a N layer continuously decreases from the channel interface (x = _Xl ) to the surface (x = x ₂ ) ( χι> x ₂ ). In Fig. 6 etc., AI composition ratio X of AIG a N layer The continuous decrease from the channel interface (X = _{X 1} ) to the surface (χ = χ ₂ ) is also expressed as “x = X 1 → χ 2”.

[0090] The HJ FET 120 has a planar structure. That is, the gate electrode 1 7 is provided in the same plane as the source electrode 15 S and the drain electrode 15 D, and the bottom surface of the gate electrode 17 is the same as the bottom surfaces of the source electrode 15 S and the drain electrode 15 D Located at the level. Therefore, the AI composition ratio x _{a at} the interface 23 A with the gate electrode 17 of the carrier supply layer 23 composed of the AIG a N layer is equal to x ₂ .

From the above equation (1), the surface density σ _の of the polarization charge generated at the interface between the carrier supply layer 23 composed of the AIG a N layer and the channel layer 12 composed of the G a N layer is expressed by the following equation (1 0 )

[0092] [Equation 23] X _P = + qx ₁ do)

[0093] When the G a N layer is stacked on the AIG a N layer, negative polarization charges are discretely generated at the heterointerface. Therefore, if the AI composition ratio is continuously decreased in the carrier supply layer 23 made of AIG a N, a continuous negative polarization charge is generated in the AIG a N layer. From the above equation (1), the surface density ( _G ) of this polarization charge generated inside the AIG a N layer under the gate is expressed by the following equation (1 1).

[0094] [Equation 24] o- _G =-(11)

[0095] Since this polarization charge is electrically equivalent to the charge due to the ionization of impurities, the total fixed charge density generated in the carrier supply layer 23 is the sum of the ionization charge density σ _Α and the polarization charge density _G. .

[0096] From the above equation (3), the conditions for the formation of the two-dimensional electron gas 14 near the interface between the G a Ν channel layer 12 and the AIG a Ν carrier supply layer 23 are as follows: 1 2)

[0097] [Equation 25] + "+ I (? Loku kl ( ¹² )

 When this condition is rewritten using the above equations (2), (1 0) and (1 1), it becomes as follows.

 [0099] [Equation 26]

¾ ?? cm- ² ] <5.6xl0 ¹³ x _a (12 ')

[0100] By doing so, a two-dimensional electron gas 14 is generated in the channel.

[0101] From the above equation (4), the conditions for obtaining the gate leakage current suppressing effect are as follows.

| σ _Α | + | σ _α |> | σ _Ρ | / Ί 00

 When this condition is rewritten using the above equations (2), (1 0) and (1 1), it becomes as follows.

N _A x η X t [cm- ² ] +5.6 xl 0 ¹³ (x `` x _a )> 5.6 x 1 O ¹¹ _X1

 [0102] By combining with the above formula (1 2 '), a two-dimensional electron gas can be formed in the channel, and the conditions under which the gate current suppression effect can be obtained are as follows.

5. 6 X 1 0 ¹¹ Χ! <Ν _Α Χ 77 X t [cm- ² ] + 5. 6 Χ 1 0 ¹³ (Χ “Χ ₃ ) <5.6 X 1 0 ¹³ Χ!

Further, from the above formula (8), the gate leakage current suppressing effect can be obtained, and the range of N _A X? 7 for the more preferable ranges of I _max and V _th is the following formula (13) or (1 3 ') These can be rewritten using the above equations (2), (1 0) and (1 1).

(13) [0105] [数 28] ί.όχΐθ¹¹^ < Ν_Αηί[ cm "² ] + 5. x 10" - ¾ ) < 2 , S x 10¹³ ^ ! (13') [0104] [Equation 27]

(13) [0105] [number _{^{28] ί.όχΐθ 11 ^ <Ν Α}} ηί [cm "2] + 5. x 10" -! ¾) <2, S x 10 13 ^ (13 ')

[0106] From the above formula (9), the more preferable range of N _A x 7? Is the following formula (1 4) or

 (1 4 ') These can be rewritten using the above equations (2), (1 0) and (1 1).

(14) [0107] [Equation 29] and 10 <|

(14)

[0108] [Equation 30]

[0109] If Ν _で and? 7 are not uniform inside the carrier supply layer 23 composed of the AIG a Ν layer, in the above formulas (1 3 ') and (1 4'), N _A x? Replace 7 X t with the following formula.

 [0110] [Equation 31]

Here, N _A (y) is the impurity concentration distribution, η (y) is the activation rate distribution, and the integration is performed in the direction perpendicular to the substrate. The integration range is from the interface with the channel layer 12 of the carrier supply layer 23 made of AIG a N to the interface with the gate electrode 17.

 Next, examples of the present invention will be described with reference to the drawings.

 [0113] (First Example)

 FIG. 1 is a cross-sectional view showing the configuration of H J F E T of this example. Such an H J FET is manufactured as follows.

[0114] First, the following layers are grown on a (0001) SiC substrate 10 by, for example, metal organic chemical vapor deposition (MOCVD), for example. . Undoped AIN buffer layer 1 1: 20 nm

 Channel layer consisting of undoped G a N 1 2:

Carrier supply layer consisting of P-type AI _X G _ai - _x N 1 3 (x = 0.2): 20 nm

Here, A I G a N and G a N have different lattice constants. The film thickness 20 nm of the carrier supply layer 13 made of p-type A I G a N is less than the critical film thickness of dislocation generation.

 For example, magnesium (Mg) or zinc (Zn) is used as the P-type impurity.

 [0116] On the carrier supply layer 1 3, for example, a metal such as titanium (T i) aluminum (AI) niobium (N b) gold (A u) is deposited and alloyed to form the source electrode 15 S The drain electrode 15 D is formed, and ohmic contact is made. Next, a metal such as nickel (N i) A u is deposited on the carrier supply layer 13, that is, between the source electrode 15 S and the drain electrode 15 D on the surface of the AIG a N layer, and liftoff is performed. Thus, the gate electrode 17 is formed. Thus, Schottky contact is made at the interface 1 3 A with the carrier supply layer 1 3. Finally, for example, a surface protective film 18 made of SiN is grown to about 100 nm, for example, by using plasma vapor deposition (abbreviated as PI a sma-E nhanced Chemical vapor Deposition: PECVD). To do. In this way, the semiconductor device as shown in FIG. 1 is manufactured.

[0117] The p-type impurity concentration N _A and the activation rate? 7 of the AIG a N layer 13 that functions as the carrier supply layer 13 are combinations that satisfy the above formula (8 ').

In such an HJ FET, a gate leakage current suppressing effect can be obtained based on the above-described principle, and I _max and V _th are further within preferable ranges. As an example, N _A = 1 X 1 0 ¹⁸ cm 3,? When 7 = 0.5, the effective impurity concentration is 5 X 1 0 ¹⁷ cr rrr ³ . At this time, the gate leakage current is suppressed to about 12% of the conventional technique, that is, when the carrier supply layer is made of undoped Al ₂ Ga ₈ N. In addition, the decrease in I _max compared to the conventional technology is about 9%, and V _th is about _2. 3V. [0119] (Second Example)

 FIG. 6 is a diagram showing a cross-sectional structure of a second embodiment of the H J FET according to the present invention. In this embodiment, in the first embodiment shown in FIG. 1, a carrier supply layer 13 made of a p-type AIG a N layer is replaced with a carrier supply layer 23 made of a p-type gradient composition AIG a N as follows. It is a replacement.

Carrier supply layer consisting of P-type gradient composition AI _X G _ai _ _x N 23 (0.1 75≤ x≤ 0.2): 20 nm

 Here, although A I G a N and G a N have different lattice constants, the film thickness 20 nm of the p-type gradient composition A I G a N layer is not more than the critical film thickness of dislocation generation.

[0121] As the p-type impurity, for example, Mg or Zn is used. p-type composition graded _{AI X} G _ai - AI composition ratio of _x N layer, i.e. the carrier supply layer 23, toward the interface _(X1 = 0 2.) between the channel layer 1 2 on the surface _{(x 2 = 0 1 75.} ) Continuously decreasing (x = 0.2 → 0.175).

The present example has a planar structure, and the AI composition ratio x _{a at} the interface 23 A between the carrier supply layer 23 and the gate electrode 17 is equal to x ₂ = 0.175.

[0123] Further, in forming a carrier supply layer 23, trimethyl gallium from the gas introducing pipe of an MOCVD apparatus (TMG), trimethyl aluminum (TMA), ammonia (NH ₃₎ to adjust the supply amount of gas, trimethyl While keeping the supply of aluminum (TMA) and ammonia (NH ₃ ) constant, the supply of trimethylgallium (TMG) is gradually increased.

[0124] The p-type impurity concentration N _A and the activation rate? 7 of the carrier supply layer 23 are combinations that satisfy the above formula (1 3 '). In such an HJ FET, a gate current suppressing effect can be obtained based on the above-described principle, and I _max and V _th are in a more preferable range.

[0125] - As an example, if you set ^{_{N A = 5 X 1 0 17}} cm- 3, 77 = 0. 6, the effective impurity concentration becomes ³ X 1 0 ¹⁷ cm_ 3. In this case, the gate leakage current, wire carrier rear supply layer is suppressed to about 4% of the structure is a uniform composition of undoped _{AI Q. 2 G a Q 8} N. Also, the I _max decrease compared to this configuration is about 18%, and V _th is approximately 1 _2.2 V.

 In this embodiment, the gradient composition AIG a N is used as the p-type carrier supply layer 23, so that the gate current suppression effect can be achieved at a lower impurity concentration than in the first embodiment using the uniform composition AIG a N. Is obtained. Since the activation rate tends to improve as the impurity concentration is lower, the controllability of the epitaxial growth is improved, and the yield and reproducibility of device characteristics are further improved.

 In this embodiment, the carrier supply layer 23 made of p-type AIG a N is composed of the gradient composition AIG a N layer in which the AI composition ratio continuously decreases. However, the present invention is not limited to this. It is also possible to adopt a configuration in which the AI composition decreases, and it is possible to have a two-layer or three-step or more step composition AIG a N layer.

 [0128] (Third Example)

 FIG. 7 is a cross-sectional view showing the configuration of the H J F E T of this example.

 In FIG. 7, on a substrate 30 made of SiC, a buffer layer 3 1 made of undoped AIN, a channel layer 3 2 made of undoped G a N, and a carrier supply layer made of p-type AIG a N 3 3 Are sequentially stacked. 〇 Due to the piezoelectric polarization effect and spontaneous polarization effect caused by the lattice constant difference between 3 1 \ 1 and 8 10 a N, there is a two-dimensional electron gas near the interface between the channel layer 3 2 and the carrier supply layer 3 3. 3 4 is formed.

 A source electrode 35 S and a drain electrode 35 D are formed on the carrier supply layer 33 made of A IG a N, and are in ohmic contact. A surface protective film 36 made of SiN is formed on the A I G a N carrier supply layer 33. The gate electrode 3 7 is formed on the recess formed by etching and removing a part of the surface protective film 3 6 and the carrier supply layer 3 3, and Schottky with the carrier supply layer 3 3 at the interface 3 3 A Contact is being made. A part of the gate electrode 37 is embedded in the carrier supply layer 33.

 Here, the gate electrode 37 has a flange portion 3 7 F projecting toward the drain electrode 35 D, and the gate electrode 37 is in contact with the surface protective film 36 at the flange portion.

[0132] Such a semiconductor device is manufactured as follows. (0 0 0 1) S i The following layers are grown sequentially on the C substrate 30 by, for example, MO CVD. Buffer layer 31 of undoped AIN: 20 nm

 Undoped G a N channel layer 32 2 um

Carrier supply layer 33 made of P-type AI _X G _ai _ _x N (x = 0.2): 40 nm [0133] where AIG a N and G a N function as different carrier constants 33 P-type to AI _X G _ai - thickness 40 nm of the _x N layer is under the critical film Atsu以of dislocation generation. For example, Mg or Zn is used as the p-type impurity. On the AIG a N layer, for example, a metal such as T i / Ik IH b A u is deposited and alloyed to form a source electrode 35 S and a drain electrode 35 D, respectively, with ohmic contact Take.

Next, for example, a surface protective film 36 made of SiN is grown to about 100 nm, for example, by using the PECVD method. An opening is formed in the surface protective film 36 between the source electrode 35 S and the drain electrode 35 D by etching removal.

Next, using the surface protective film 36 as a mask, for example, by using a dry etching apparatus using a chlorine (CI ₂ ) -based gas, a part of the carrier supply layer 33 is etched away to remove the recess portion. Form. On the recess portion, a metal such as Ni ZA u is deposited, and the gate electrode 37 having the flange portion 37 F is formed by lift-off. Thus, Schottky contact is made at the interface 33 A with the AIG a N layer. The HJ FET shown in Fig. 7 is fabricated by the above procedure.

Also in the present embodiment, the p-type impurity concentration N _A and the activation rate 77 of the carrier supply layer 33 are combinations that satisfy the above formula (8 ′). In this embodiment, the gate electrode 37 is formed in contact with the recess formed by removing a part of the carrier supply layer 33, and the p-type AIG a N layer thickness t in the above formula (8 ′) Is the thickness of the p-type layer present in the portion sandwiched between the gate interface 33 A and the channel layer 32, that is, the thickness of the p-type layer between the recess portion and the channel layer 32. In this embodiment, for example, t = 20 nm. In such an HJFET, a gate leakage current suppressing effect is obtained based on the above-described principle, and I _max and V _th are further within desired ranges. —As an example, when the composition ratio is set to 0.2, the p-type impurity concentration N _{A is set} to 1 X 1 0 ¹⁸ cm ³ , and the activation rate 77 is set to 0.5 (the effective impurity concentration is 5 X 1

), The gate leakage current is suppressed to about 12% of the conventional technology (undoped AIG a N). In addition, the decrease in I _max compared to the conventional technology is about 9%, and V _th is about _2. 3 V.

 In the present embodiment, the gate electrode 37 is formed in the recess portion where a part of the carrier supply layer 33 is removed by etching. For this reason, the distance between the two-dimensional electron gas layer 34 and the AIG a N surface can be increased while the distance between the two-dimensional electron gas layer 34 and the gate electrode 37 is reduced and the mutual conductance is kept high. Compared with one embodiment, instability caused by surface traps such as current collapse can be suppressed.

 Furthermore, the gate electrode 37 has a flange 37 F in contact with the surface protective film 36 made of SiN. This flange 37 F functions as a so-called field-plate electrode. That is, a depletion layer is formed under the flange portion 37F, the electric field strength between the gate and the drain is reduced, and the gate breakdown voltage is improved as compared with the first embodiment having no flange portion.

 [0140] (Fourth embodiment)

 FIG. 8 is a cross-sectional view showing the configuration of the H J F E T of this example. In this embodiment, in the third embodiment shown in FIG. 7, the carrier supply layer 33 made of p-type AIG a N is replaced with a carrier supply layer 43 made of a p-type gradient composition AIG a N layer shown below. It is a thing.

Carrier supply layer consisting of P-type gradient composition AI _X G _ai _ _x N 43 (0.1 5≤ x≤0.2): 40 nm

Here, AIG a N and G a N have different lattice constants. The P-type gradient composition AIG a N layer constituting the carrier supply layer 43 has a film thickness of 40 nm or less than the critical film thickness for the generation of dislocations. For example, Mg or Zn is used as the p-type impurity. [0142] The p-type graded composition A l _x G _ai _ _x N layer, which functions as the carrier supply layer 43, has an AI composition ratio from the interface with the channel layer 32 made of G a N ( ₂₁ = _0.2 ) to the surface. (Χ ₂ = 0. 1 5) continuously decreasing (X = 0.2 → 0.1 5)

[0143] In this embodiment, because it uses a recessed structure, that it puts the gate interface 43 Alpha AI composition ratio x _a is a value between _Xl and x _2, for example, a x _a = 0. 1 75 Become.

The p-type impurity concentration N _A and the activation rate 7? Of the AIG a N layer are combinations that satisfy the above formula (1 3 '). In the present embodiment, the gate electrode 37 force is formed in contact with the recess formed by removing a part of the carrier supply layer 4 3, and the p-type AIG a N layer in the above formula (1 3 ′) The thickness t is the thickness of the p-type layer existing in the portion sandwiched between the gate interface 43 A and the channel layer 32, that is, the thickness of the p-type layer between the recess portion and the channel layer 32. In this embodiment, for example, t = 20 nm.

In such an HJ FET, a gate leak current suppressing effect is obtained based on the above-described principle, and I _max and V _th are further within desired ranges. As an example, when N _A = 5 X 10 ¹⁷ cm- ³ and 77 = 0.6 (effective impurity concentration is 3 X 1 O ^ cm-3), the gate leakage current is It is suppressed to about 4% of the (and uniform composition A l o.2G a ₀₈ N). In addition, the decrease in I _max compared to the conventional technology is about 18%, and V _th is about _1.2.2 V.

 In this embodiment, since the gradient composition AIG a N is used as the p-type carrier supply layer, the gate is formed at a lower p-type impurity concentration than in the third embodiment using the uniform composition AIG a N. A current suppression effect is obtained. Since the activation rate tends to improve as the impurity concentration is lower, the controllability of epitaxial growth is improved, and the yield and reproducibility of device characteristics are further improved.

In this embodiment, the p-type carrier supply layer 43 is composed of the gradient composition AIG a N layer, but of course, it may be composed of two or three or more step composition AIG a N layers. . [0147] (Fifth Example)

 FIG. 9 is a cross-sectional view showing the configuration of the H J F E T of this example.

[0148] In FIG. 9, on the SiC substrate 50, a buffer layer 51 made of undoped AIN, a channel layer 52 made of undoped G a N, a p-type AI _X G a N layer 5 31, and an undoped AI _X G _ai _ _x N layers 532 are sequentially stacked.

[0149] Due to the piezoelectric polarization effect and spontaneous polarization effect due to the difference in lattice constant between G a N and AIG a N, near the interface of the channel layer 52 with the p-type Al _x Ga ₁ - _x N layer 531 The two-dimensional electron gas 54 is formed.

 [0150] On undoped A I G a N layer 532, source electrode 55 S, drain electrode

 55 D is formed and ohmic contact is made. A surface protective film 56 made of SiN is formed on the undoped A I G a N layer 532.

 [0151] A gate electrode 57 is formed on the recess formed by etching away part of the surface protective film 56 and the undoped AIG a N layer 532, and shot with the AIG a N layer 532 at the interface 53 A. Key contact is taken. Here, the gate electrode 57 has a flange 57 F protruding toward the drain electrode 55 D, and the gate electrode 57 is in contact with the surface protection film 56 at the flange.

 [0152] Such an H J FET is manufactured as follows.

 First, on the (0001) SiC substrate 50, for example, the MOC VD method is used to sequentially grow the layers in the following order and film thickness.

 Undoped A I N buffer layer 51: 20 nm

 Channel layer 52 of undoped G a N:

p-type AI _X G a —xN layer 531 (x = 0.2): 20 nm

Undoped AI _X G a to _X N layer 532 (x = 0.2): 20 nm

[0153] where AIG a N and G a N have different lattice constants p-type A l _x G _ai _ _x N layer

531 and undoped AI _X G _ai - sum 40 nm in the thickness of the _x N layer 532 is below the critical thickness for the occurrence of dislocation. For example, Mg or Zn is used as the P-type impurity.

[0154] Undoped AI _X G _ai — _x N layer 532, for example, T i ZA I ZN bZ By vapor-depositing and alloying a metal such as Au, the source electrode 55 S and the drain electrode 55 D are formed to make ohmic contact.

[0155] Next, for example, a SiN film functioning as the insulating protective film 56 is grown by, for example, about 100 nm using PECVD. An opening is formed by etching removal at a portion sandwiched between the source electrode 55 S and the drain electrode 55 D of the Si N film.

Next, undoped AIG a N in a predetermined region between the source electrode 55 S and the drain electrode 55 D, for example, by a dry etching method using a CI ₂ gas with the Si N film as a mask. A recess is formed in the undoped AIG a N layer 532 by selectively etching away a portion of the layer 532

On the recess portion, a metal such as Ni ZAu is deposited, and the gate electrode 57 having the flange portion 5 7 F is formed by lift-off. Thus, Schottky contact is made at the interface 53 A with the A I G a N layer. In this way, the semiconductor device shown in FIG. 9 is manufactured.

[0158] In the present embodiment, p-type _{AI X} G _ai _ _x N layer concentration N _A of the p-type impurity in 531, the activation rate 7 are combined so as to satisfy the above relational expression (8 '). Here, the P-type AIG a N layer thickness t in the above formula (8 ′) is the thickness of the P-type layer existing in the portion sandwiched between the gate interface 53 A and the channel layer 52. In this case, t = 20 nm.

In such an HJ FET, a gate leakage current suppressing effect is obtained based on the above-described principle, and I _max and V _th are further within desired ranges. — As an example, when p-type impurity concentration N _{A is set} to 1 X 1 0 ¹⁸ cm ³ and activation rate 7? Is set to 0.5 (effective impurity concentration is 5 X 1 O ^ cm-3 ), the gate leakage current is suppressed to about 1 2% of the prior art (undoped _{AI 0. 2 G a 0.} 8 N). In addition, the I _max reduction range compared to the conventional technology is about 90/0.

[0160] Further, in this embodiment, the undoped _{AI X} G _ai - _x N layer gate electrode 57 in the recess portion which is Etsuchin grayed removing a portion of 532 is formed. For this reason, Ion of charge density sigma _Alpha of p-type impurities under the gate be varied depth slightly does not change. For this reason, the process margin is improved and the in-plane uniformity of the device characteristics is improved as compared with the third embodiment in which the recess portion is formed inside the ρ-type AI _{X Ga i} _ _x N layer 531. .

[0161] (Sixth embodiment)

FIG. 10 is a cross-sectional view showing the configuration of the HJFET of this example. This embodiment is different from the fifth embodiment shown in FIG. 9 in that the p-type AI _X G _{ai -x} N layer 531 and the undoped AI _X G _{ai -x} N layer 532 are each of the following AIG a N layers: It has been replaced by a structure.

P-type graded composition AI _X G a to _X N layer 631 (0.1 75≤ x≤ 0.2): 20 nm Undoped A l _x G a to _X N layer 632 (x = 0.1 75): 20 nm

[0162] Here, AIG a N and G a N are have different lattice constants, p-type composition graded AI _X G a _i - _x N layer 631 and the undoped AI _X G _ai - the thickness of the _x N layer 632 The sum of 40 nm is less than the critical film thickness for dislocation generation.

[0163] The p-type impurity in the p-type gradient composition AI _{X Ga i — x} N layer 631 is, for example, Mg or Zn. The AI composition ratio of the p-type graded composition AI _X G _ai _ _x N layer 631 is from the interface with the channel layer 52 (x O. 2) to the interface with the undoped AI _X Ga layer 632 (x ₂ = 0. 1 75) continuously decreasing (x = 0.2 to 0.1 75).

[0164] Since the recess portion is formed by etching away a part of the undoped AI _X G _ai _ _x N layer 632, the AI composition ratio x _{a at} the interface 63 A with the gate electrode 57 is x ₂ = 0.1 Equal to 75.

 [0165] The p-type impurity concentration N A and the activation rate 7? Of the A IG a N layer 631 are combinations that satisfy the above formula (1 3 '). Here, the p-type AIG a N layer thickness t in the above formula (1 3 ′) is the thickness of the p-type layer existing in the portion sandwiched between the gate interface 63 A and the channel layer 52. In this case, t = 20 nm.

In such an HJ FET, a gate current suppressing effect is obtained based on the above-described principle, and I _max and V _th are further within desired ranges. With an example When N _A = 5 X 10 " _C m- ³ and 77 = 0.6 (effective impurity concentration is 3 X 10" cm- ³ ), the gate leakage current is It is suppressed to about 4% of the prior art (undoped uniform composition _{a l o. 2 G a 0} . 8 N). Compared with the conventional technology

I _max decrease is about 18%.

 [0167] In this example, since the gradient composition AIG a N is used as the p-type carrier supply layer, the p-type impurity concentration is lower than that in the fifth example using the uniform composition AIG a N. A gate current suppressing effect can be obtained. Since the activation rate tends to improve as the impurity concentration is lower, the controllability of epitaxial growth is improved, and the yield and reproducibility of device characteristics are improved.

 [0168] In this example, the p-type carrier supply layer is formed of a p-type gradient composition A I G a N layer 63

 Although it is composed of 1, of course, it may be composed of two or three or more step composition A I G a N layers.

 [0169] (Seventh embodiment)

 FIG. 11 is a cross-sectional view showing the configuration of H J F E T of this example.

In FIG. 11, on the substrate 70 made of SiC, an undoped AIN buffer layer 7 1, a channel layer 72 made of undoped G a N, a p-type AI _X Ga to _X N layer 731, an undoped AI _X G a to _X N layer 732 and n-type AI _X G ₃₁ - _Χ Ν layer 733 are stacked in this order. The p-type AI _X G _ai _ _x N layer 731 of the G a N layer functioning as the channel layer 72 due to the piezo polarization effect and the spontaneous polarization effect caused by the lattice constant difference between G a A and AIG a N Near the interface, a two-dimensional electron gas 74 is formed.

[0172] On the n-type _{AI X} G _ai _ _x N layer 733 is formed the source electrode 75 S and the drain electrode 75 D is, ohmic contact therewith. On the n-type AI _{X Ga} i — _x N layer 733, an insulating surface protective film 76 made of an Si N film is formed. A gate electrode 77 is formed on the recess formed by etching away the Si N film and the n-type AI _X Ga to _X N layer 733 and a part of the undoped AI _X Ga to _X N layer 732. Thus, Schottky contact with the AI _{X Ga i} -xN layer 732 is made at the interface 73 A. Here, the gate electrode 77 protrudes toward the drain electrode 75 D side. The gate electrode 77 is in contact with the surface protective film 76 at the flange.

 [0173] Such an H J FET is manufactured as follows.

 First, the following layers are sequentially formed on the (0001) SiC substrate 70 by, for example, the MOC VD method.

 Undoped A I N buffer layer 7 1: 20 nm

 Undoped G a N channel layer 72 2 um

p-type AI _X Ga to _X N layer 731 (x = 0.2): 20 nm

Undoped AI _X Ga to _X N layer 732 (x = 0.2): 10 nm

n-type A l _x G a to _X N layer 733 (x = 0.2): 10 nm

[0174] Here, AIG a N and G a N have different lattice constants. AIG a N layer (p-type AI _X G a to _X N layer 731, undoped AI _X G a to _X N layer 732 and n-type AI The sum 40 nm of the film thickness of the _X G _ai _ _x N layer 733) is less than the critical film thickness for dislocation generation.

[0175] As the p-type impurity in the p-type AI _X G _ai _ _x N layer 731, for example, Mg or Zn is used as the n-type impurity in the n-type AI _X G _ai _ _x N layer 733. For example, silicon (S i) is used.

[0176] The source electrode 75 S and the drain electrode 75 D are formed on the n-type AI _X G a ^ xN layer 733 by evaporating and alloying metals such as T i ZA l ZN bZA u, respectively. And make ohmic contact.

Next, for example, a SiN film functioning as the surface protective film 76 is grown by, eg, about 100 nm using the PECVD method. An opening is formed in the Si N film between the source electrode 75 S and the drain electrode 75 D by etching away. Next, S i the N film as a mask, for example, n-type using a draw dry etching apparatus using a CI ₂ system gas _{AI X} G _ai _ _x N layer 733 and the undoped AI _X G a _i - _x N layer 732 A recess is formed by etching away a part of the recess. A metal such as Ni ZAu is deposited on the recess, and a gate electrode 77 having a flange 7 7 F is formed by lift-off. Thus, undoped gate electrode 77 _{AI X} G _ai - take Schottky first contact at the interface between _x N layer 732 73 A. In this way, the HJFET as shown in Fig. 11 is fabricated.

[0178] p-type _{AI X} G _ai _ _x concentration of the p-type impurity of the N layer 731 N _A, activation rate? 7 is the above formula (

 8 '). Here, the p-type AIG a N layer thickness t in the above formula (8 ′) is the thickness of the P-type layer existing in the portion sandwiched between the gate interface 73 A and the channel layer 72. In this case, t = 20 nm.

In such an HJ FET, a gate leakage current suppressing effect is obtained based on the above-described principle, and I _max and V _th are further within desired ranges. — As an example, when p-type impurity concentration N _{A is set} to 1 X 10 ¹⁸ cm_ ³ and activation rate 7? Is set to 0.5 (effective impurity concentration is 5 X 1 0 ¹⁷ cm-3) the gate leakage current is suppressed to about 1 2% of the prior art (undoped _{AI 0. 2 G a 0.} 8 N). In addition, the I _max reduction range compared to the conventional technology is about 90/0.

[0180] In this example, positive ionized impurity charges are generated in the n-type AIG a N layer 733. Therefore, the lower Omikku electrode (the source electrode 75 S and the drain electrode 75 D) _{AI X} G _ai - negative polarization charge in the _x N layer 731 is a depletion layer is reduced to cancel, lowering the potential barrier to electrons Thus, ohmic contact resistance is reduced.

 [0181] (Eighth Example)

FIG. 12 is a cross-sectional view showing the configuration of the HJ FET of this example. This embodiment is different from the seventh embodiment shown in FIG. 11 in that the AIG a N layer (p-type AI _X G _{31. Χ}ト layer 731, undoped AI _X G to _X N layer 732 and n-type AI _X G _ai _ _x N layer 73 3) is replaced with the following AIG a N layer structure.

P-type gradient composition AI _X G a to _X N layer 831 (0. 1 75≤ χ ≤ 0.2): 20 η m Undoped AI _X G a to _X layer 832 (χ = 0.1 75): 1 0 nm

n-type graded composition AI _X G a to _X N layer 833 (0. 1 75≤ x≤ 0.2): 10 nm

[0182] Here, AIG a N and G a N have different lattice constants. AIG a N layer (p-type gradient composition AI _X G a to _X N layer 831, undoped AI _X G to _x N layer 832, n The total film thickness of the type gradient composition AI _X G _ai - _x N layer 833) is less than the critical film thickness for dislocation generation. [0183] As the p-type impurity in the p-type gradient composition AI _X G _ai _ _x N layer 831, for example, Mg or Zn is used, and the n-type gradient composition AI _X G _ai _ _x N layer 833 n For example, S i is used as the type impurity.

[0184] The AI composition ratio of the p-type gradient composition AI _X G _ai _ _x N layer 831 is from the interface with the channel layer 72 (x O. 2) to the interface with the undoped AI _X G a to _X N layer 832 (x ₂ = 0. 1 75) continuously decreasing (x = 0.2 → 0.175). The AI composition ratio of the n-type gradient composition AI _X G a _X N layer 833 is from the interface (χ ₂ = 0. 1 75) to the undoped AI _X G _{3 ι} _ _χ層 layer 832 (χ ₃ = 0. Increase continuously toward (2) (χ = 0.1 75 → 0.2).

[0185] The recess portion is formed by etching away the η-type gradient composition AI _X G _{ai -x} N layer 833 and a part of the undoped AI _X G _{3 ι} _ _χ層 layer 832, so that the interface with the gate electrode 77 The AI composition ratio x _a in 83 Α is equal to χ ₂ = 0.175. ρ-type gradient composition _{Α 6 31 -.) (?} 1 concentration N _A of the p-type impurity \ 1 layer 831, the activation rate 7 above formula (1 3 ') a combination satisfying this case, the above equation (1 The p-type AIG a N layer thickness t in 3 ') is the thickness of the p-type layer that exists between the gate interface 83 A and the channel layer 72. In this example, t = 20 nm It is.

In such an HJ FET, a gate leakage current suppressing effect is obtained based on the above-described principle, and I _max and V _th are further within desired ranges. —For example, if N _A = 5 X 10 " _C m- ³ and 77 = 0.6 (effective impurity concentration is 3 X 10" _cm -3), the gate leakage current Is suppressed to about 4% of the conventional technology (and one-piece composition AI 0.2G a ₀₈ N). In addition, the I _max reduction range compared to the conventional technology is about 18%.

[0187] Also, in this example, since the p-type gradient composition A Ι _Χ Θ _{31. Χ} N layer 831 is used as the p-type carrier supply layer, it is lower than the seventh example using the uniform composition AIG a N. The effect of suppressing gate leakage current can be obtained at high P-type impurity concentration. Since the activation rate tends to improve as the impurity concentration decreases, the controllability of epitaxial growth is improved, and the yield and reproducibility of device characteristics are improved.

[0188] In this example, the p-type carrier supply layer is formed of a p-type gradient composition A l _x G _ai - _x N Although it is composed of the layer 831, of course, it may be composed of two layers or three or more step composition AIG a N layers.

 [0189] (Ninth Example)

 FIG. 13 is a cross-sectional view showing the configuration of the H J F E T of this example.

[0190] In FIG. 13, on the substrate 90 made of SiC, a buffer layer 91 made of undoped AIN, a channel layer 92 made of undoped G a N, a p-type AI _X Ga _i — _x N layer 931 and Undoped AI _X G _ai — _x N layers 932 are stacked in this order. Due to the piezo polarization effect and spontaneous polarization effect caused by the difference in lattice constant between G a N and AIG a N, there is a two-dimensional area near the interface with the p-type AI _X G _ai - _x N layer 931 of the channel layer 92. Electron gas 94 is formed.

A source electrode 95 S and a drain electrode 95 D are formed on the undoped AI _X G _{ai -x} N layer 932 to make ohmic contact. A surface protective film 96 made of SiN is provided on the undoped AI _X G a, _ _x N layer 932. Surface protective film 96 and the undoped _{AI X} G _ai - _x a portion of the N layer 932 etched away to form the recessed portion on the gate electrode 97 is formed, undoped at the interface 93 A _{AI X} G _ai _ _x N layer 932 is in Schottky contact.

 Here, the gate electrode 97 has a flange 97 F protruding toward the drain electrode 95 D, and the gate electrode 97 is in contact with the surface protective film 96 at the flange. Furthermore, in this embodiment, a Schottky electrode 99 is formed at a portion sandwiched between the gate electrode 97 and the drain electrode 95D on the surface protective film 96.

 [0193] Such an H J FET is manufactured as follows.

 First, growth is performed sequentially on the (0001) SiC substrate 90 in the following order and film thickness by, for example, the MOC VD method.

 Undoped A I N buffer layer 91: 20 nm

 Undoped G a N channel layer 92 2 um

p-type AI _X Ga to _X N layer 931 (x = 0.2): 20 nm

Undoped AI _X G a to _X N layer 932 (x = 0.2): 20 nm

[0194] where AIG a N and G a N have different lattice constants AIG a N layer (p-type _{AI X} G _ai - _x N layer 931, film sum 40 nm thick undoped _{AI X} G _ai _ _x N layer 932) is below the critical thickness for the occurrence of dislocation.

[0195] As the p-type impurity in the p-type _{AI X} G _ai _ _x N layer 931, for example, Mg or the like Z n. On the undoped AI _X G _ai _ _x N layer 932, for example, a metal such as T i ZA IN bZA u is deposited and alloyed to form a source electrode 95 S and a drain electrode 95 D, respectively. Take ohmic contact.

[0196] Next, for example, a SiN film functioning as the surface protective film 96 is grown by, for example, about 100 nm using PECVD. An opening is formed in the Si N film between the source electrode 95 S and the drain electrode 95 D by etching. Then, as a mask S i N film, for example, an undoped using a draw dry etching apparatus using a CI ₂ system gas _{AI X} G _ai - _x part Etsu quenching removing things by Ririsesu portion of the N layer 932 Form.

 [0197] On the recess portion, a metal such as Ni ZAu is deposited, and a gate electrode 97 having a flange portion 9 7 F is formed by lift-off. In this way, Schottky contact is made at the interface 93 A with the A I G a N layer. A metal such as Ti platinum (P t) ZAu is deposited on a portion sandwiched between the gate electrode 97 and the drain electrode 95D on the surface protective film 96, and a schottky electrode 99 is formed by lift-off. In this way, the H J FE T shown in FIG. 13 is produced.

_{[0198] AI X G ai _} x N concentration N _A, the activation of the p-type impurity layer 931? 7, a combination that satisfies the above expression (8 '). Here, the p-type AIG a N layer thickness t in the above formula (8 ′) is the thickness of the p-type layer existing in the portion sandwiched between the gate interface 93 A and the channel layer 92. In this case, t = 20 nm.

In such an HJ FET, a gate leakage current suppressing effect can be obtained based on the principle described above, and I _max and V _th are further within desired ranges. — As an example, when p-type impurity concentration N _{A is set} to 3 X 10 ¹⁸ cm_ ³ and activation rate 7? Is set to 0.33 (effective impurity concentration is 1 X 10 ¹⁸ cm-3) , the gate leakage current may be suppressed to about 1% of the prior art (undoped _{AI 0. 2 G a 0.} 8 N). Ma In addition, the decrease in I _max compared to the conventional technology is about 18%.

 [0200] Further, in this embodiment, the Schottky electrode 99 functions as a so-called Faraday shield by connecting it to the source. That is, the gate-drain electrical coupling is shielded, the gate-drain capacitance is reduced, and the gain and isolation characteristics are improved. Schottky electrode 99 may be connected to a gate. In this case, it functions as a so-called field plate, and the gate breakdown voltage is further improved.

 [0201] (Tenth example)

 FIG. 14 is a cross-sectional view showing the configuration of H J F E T of this example.

[0202] In FIG. 14, a buffer layer 1 01 made of undoped AIN, a channel layer 1 02 made of undoped G a N, a p-type AI _X G a _{X X} layer 1 on a substrate 100 made of SiC 031 and undoped AI _X Ga to _X N layers 1 032 are sequentially stacked. Due to the piezo polarization effect and spontaneous polarization effect due to the lattice constant difference between G a N and AIG a N, the type of the layer 63 _{1- ) (} 1 \ 1 layer 1 0 31 near the interface is A two-dimensional electron gas 104 is formed.

[0203] A source electrode 1 05 S and a drain electrode 1 05 D are formed on the undoped AI _X Ga ^ xN layer 1 032 and are in ohmic contact. On the undoped AI _X G a _i _ _x N layer 1 032, to form an S i N film serving as a first surface passivation film 1 06. A gate electrode 107 is formed on the recess formed by etching away a part of the first surface protective film 106 and the undoped AI _X G _ai _ _x N layer 10 322, and the undoped AI is formed at the interface 103 A. Schottky contact with _X G _ai - _x N layer 1 032 is taken.

[0204] Here, the gate electrode 107 has a flange 1 07 F projecting toward the drain electrode 105 D side, and the gate electrode 107 is in contact with the first surface protective film 106 at the flange. Yes. Further, in this embodiment, a second surface protective film 108 covering the upper surfaces of the first surface protective film 106 and the gate electrode 107 is provided in the region between the source electrode 105S and the drain electrode 105D. It has been. The second surface protective film is a Si N film, and is drained with the gate electrode 107 on the second surface protective film 108. A Schottky electrode 109 is formed at a portion sandwiched between the two electrodes 1105D.

 [0205] Such an H J FET is manufactured as follows.

 First, the following layers are sequentially formed on a substrate 100 made of (0001) SiC by, for example, MOCVD.

 Buffer layer consisting of undoped A I N 1 01: 20 nm

 Channel layer made of undoped G a N 10 2: 2 m

p-type AI _X Ga to _X N layer 1 031 (x = 0.2): 20 nm

Undoped AI _X G a to _X N layer 1 032 (x = 0.2): 20 nm

[0206] Here, AIG a N and G a N have different lattice constants. AIG a N layer (p-type AI _X G a to _X N layer 1 031, undoped AI _X G a to _X N layer 1 032) The total film thickness of 40 nm is below the critical film thickness for dislocation generation.

[0207] As the p-type _{AI X} G _ai _ _x N layer 1 p-type impurity in 031, for example, Mg or uses such as Z n. On the undoped AI _X G _ai - _x N layer 1 032, for example, a metal such as Ti ZA I ZN bZA u is deposited and alloyed to form a source electrode 1 05S and a drain electrode 1 05 D, respectively. And ohmic contact.

 [0208] Next, for example, a SiN film functioning as the first surface protective film 106 is grown by, for example, about 100 nm using PECVD. S i N film source electrode 1

An opening is formed in the region between 05S and drain electrode 1 05 D by etching. Next, using the first surface protective film 106 as a mask, for example

Then, a recess portion is formed by etching away a part of the undoped AI _X G _{31 .ΧN} layer 10 ₃₂ using a dry etching apparatus using a CI ₂ gas. On the recess portion, a metal such as Ni ZAu is vapor-deposited, and the gate electrode 107 having the flange portion 10 07 F is formed by lift-off. In this way, Schottky contact is made at the interface 103 A with the Al _x G a _{1 -x} N layer 10 32.

[0209] Next, for example, S functioning as a second surface protective film using the PECVD method.

1 N film 108 is grown to about 200 nm, for example. On the second surface protective film 1 08 A metal such as T i / P t ZAu is deposited on a portion sandwiched between the gate electrode 107 and the drain electrode 105 D to form a Schottky electrode 109 by lift-off. In this way, the HJFET shown in Fig. 14 is fabricated.

[0210] The p-type impurity concentration N _A and the activation rate 7? Of the AIG a N layer 1 03 1 are combinations that satisfy the above equation (8 '). Here, the p-type AIG a N layer thickness t in the above formula (8 ′) is the thickness of the P-type layer existing in the portion sandwiched between the gate interface 10 03 A and the channel layer 102. In the example, t = 20 nm.

[0211] In such an HJFET, a gate current suppression effect is obtained based on the above-described principle, and I _max and V _th are further within desired ranges. And an example, P-type impurity concentration N _A of the ^{3 X 1 0 18 c m_ 3} , when set to the activation of 7? A 0.33 (the effective impurity concentration is 1 X 1 0 ¹⁸ c m- 3), the gate leakage current may be suppressed to about 1% of the prior art (undoped _{AI 0. 2 G a 0.} 8 N). In addition, the I _max reduction compared with the _conventional technology is about 18%.

 In this example, the second surface protective film 108 is sandwiched between the gate electrode 107 and the Schottky electrode 109. Therefore, the Schottky electrode 109 can surround at least the portion of the gate electrode 107 with the second surface protective film 108 interposed therebetween. Therefore, when the Schottky electrode 109 is connected to the source, the shielding effect between the gate and the drain is greatly improved, and the gain and isolation characteristics are further improved.

 [0213] Although the present invention has been described with reference to the above-described embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that the present invention includes various embodiments according to the principle of the present invention.

[0214] For example, in the above embodiments, AIG a N is used as the material of the carrier supply layer, but other group III nitride semiconductors may be used. For example, In AIN, InGaN, InAIGaN, AIN, and GaN may be used. Also, it may be a superstrain layer made of at least two different semiconductor materials among G a N, AIG a N, In AIN, In GaN, In AIG a N, AIN, and In N. . [0215] In the above embodiment, the carrier supply layer made of p-type AIG a N is formed in contact with the Ga N channel layer, but undoped between the Ga N layer and the p-type AIG a N layer. An AIG a N spacer layer may be inserted. In addition, an n-type impurity such as Si may be doped into a part of the AIG a N carrier supply layer.

 [0216] In the above embodiments, GaN is used as the channel material. However, the channel material may be another group I I I nitride semiconductor having a smaller band gap than the carrier supply layer. For example, I n N, I n G a N, A I G a N, I n A I N, and I n A I G a N may be used. In addition, although the channel layer is an AND, an n-type impurity such as Si may be doped into a part or the whole of the channel layer.

[0217] In the above embodiments, SiN is used as the dielectric film constituting the insulating protective film, but the material of the insulating protective film may be other dielectrics. For example, S i 0 ₂ or S i ON may be used.

[0218] Furthermore, in the above embodiment, SiC was used as the substrate material, but other substrates may be used. For example, sapphire, Si, or G a N may be used.

Claims

Claims AI XG a, _x N (0≤x≤ 1) including a channel layer consisting of I nyG a, _yN (0≤ y≤ 1) and at least one P-type layer provided on the channel layer A carrier supply layer comprising: a source electrode, a drain electrode and a gate electrode facing the channel layer through the P-type layer and provided on the carrier supply layer; and AI of the carrier supply layer The composition ratio x, the thickness t of the p-type layer, the impurity concentration NA and the activation rate 7 are:  [Number 1] _{^{5.6X10 1 <N A x7 xt [}} cm- 2] <5.6xl0 13 field effect transistor satisfying.  The field effect transistor according to claim 1,  [Equation 2] _{^{5.6xl u <N A X7J xt [}} cm '2] field effect transistor that satisfies <2.Sx X. A channel layer made of _{I n y G ai. Y N} (0≤ y≤ 1), Provided on the channel layer, and _{AI X G ai. X N (} 0≤x≤ 1) a carrier supplying layer comprising at least one layer of p-type layer,  A source electrode, a drain electrode, and a gate electrode that face the channel layer through the P-type layer and are provided on the carrier supply layer, and a two-dimensional electron gas is generated in the channel layer, AI composition ratio at the interface between the AI composition ratio X _a and before SL channel layer at an interface between the gate electrode of the Kyaria supply layer,  X a, X 1 And AI composition ratio x _a , p-type layer thickness t, impurity concentration NA and activation rate 77 But, [Equation 3]

Satisfy field effect transistor. [4] The field effect transistor according to claim 3, [Equation 4]

Satisfy field effect transistor.  [5] The field effect transistor according to any one of claims 1 to 4,  A field effect transistor in which the gate electrode is provided in the same plane as the source electrode and the drain electrode. [6] A channel layer consisting of I n _y G a, _ _y N (0≤ y≤ 1), A carrier supply layer formed of AI _X G a, _ _x N (0≤x≤ 1) including at least one p-type layer provided on the channel layer;  A source electrode, a drain electrode, and a gate electrode that face the channel layer through the P-type layer and are provided on the carrier supply layer; and the gate electrode forms a part of the carrier supply layer. A field effect transistor formed in contact with the removed recess portion,  The thickness t of the p-type layer between the recess and the channel layer, the impurity concentration NA, and the activation rate? 5. 6 X 1 0 ¹¹ X <Ν _Α Χ η xt [cm " ² ] <5.6 x 1 0 ¹³ x  Satisfy field effect transistor. [7] A channel layer consisting of I n _y G a _{y y} (0≤ y≤ 1), Provided on the channel layer, and _{AI X G ai. X N (} 0≤x≤ 1) a carrier supplying layer comprising at least one layer of p-type layer, A source electrode, a drain electrode, and a gate electrode that face the channel layer through the P-type layer and are provided on the carrier supply layer; and the gate electrode forms a part of the carrier supply layer. A field effect transistor formed in contact with the removed recess portion, The AI composition ratio at an interface between the gate electrode of the carrier supply layer, with less than AI composition ratio _X1 in the interface between the channel layer, wherein the AI composition ratio x _a, the AI composition ratio _Xl, and the recessed portion The thickness t of the P-type layer, the impurity concentration N _A and the activation rate 77 between the channel layers are: _{^{5. 6 X 1 0 11 X1 <}} N A X 77 X t [cm "2] +5 6 x 1 0 13. (X '- x a) Ku 5 ■

Satisfy field effect transistor.  8. The field effect transistor according to claim 1, wherein the threshold voltage is negative.