JP2007173426A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device assuring a lower ON resistance (R<SB>ON</SB>) and a higher OFF withstand voltage. <P>SOLUTION: The ON resistance (R<SB>ON</SB>) of an element is maintained small and withstand voltage thereof is maintained higher by giving a distortion characteristic to lower the threshold voltage to an insulating film formed between source and gate electrodes, and also giving a distortion characteristic to raise the threshold voltage to an insulating film 7 formed between drain and gate electrodes. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a heterojunction field effect transistor structure using an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) heterostructure or the like.

Circuits such as switching power supplies and inverters use power semiconductor elements such as switching elements and diodes, and the power semiconductor elements are required to have characteristics such as high breakdown voltage and low on-resistance (R _ON ). There is a trade-off relationship determined by the element material between the breakdown voltage and the on-resistance (R _ON ). Advances in technology development have made it possible to achieve low on-resistance (R _ON ) near the limit of silicon (hereinafter referred to as Si), which is a main element material for power semiconductors.
In order to further reduce the on-resistance (R _ON ), it is necessary to change the element material. For example, by using a nitride semiconductor such as gallium nitride (hereinafter referred to as GaN) or aluminum gallium nitride (hereinafter referred to as AlGaN) as a switching element material, the trade-off relationship determined by the material is improved and the on-resistance (R) is dramatically increased. _ON ) can be lowered.

As an element using a nitride semiconductor such as GaN or AlGaN, there is a hetero field effect transistor (hereinafter referred to as HFET) using an AlGaN / GaN heterostructure. This HFET realizes a low on-resistance due to the high mobility of the heterointerface channel and the high electron concentration generated by the piezo polarization due to the strain at the heterointerface. For this reason, it has been attracting attention as a high-power high-frequency device.
A general HFET structure is shown in FIG. A gate is formed on the surface of a nitride semiconductor having a heterojunction structure including a carrier traveling layer (channel layer) 1 made of a GaN film formed on a semiconductor substrate and a barrier layer (barrier layer) 2 made of an AlGaN film formed thereon. An electrode 6 is provided, and a source electrode 5 and a drain electrode 4 are provided with the electrode 6 interposed therebetween. Although not shown in FIG. 25, the nitride semiconductor surface and each electrode are usually covered with an insulating film for surface protection.

In such a nitride semiconductor device, various attempts have been made to improve the trade-off relationship between the reduction in on-resistance (R _ON ) and the improvement in off-breakdown voltage described above. For example, in order to reduce the on-resistance (R _ON ), the resistance value between the gate and the source is lowered by using a recess gate structure that improves the ohmic characteristics of the source electrode or digs into a gate electrode semiconductor layer. It was. In order to improve the off breakdown voltage, the resistance value between the gate and the drain is increased by using an offset electrode structure that increases the distance between the gate electrode and the drain electrode. However, in the case of an AlGaN / GaN heterostructure, the process of digging a semiconductor surface to form a recess gate structure is limited to reactive plasma etching (RIE), and thus plasma damage enters the semiconductor layer. There's a problem. Furthermore, the offset amount of the offset electrode structure is largely due to alignment accuracy in a series of processes (hereinafter referred to as PEP process: Photo Engraving Preocess) such as resist coating, mask alignment, exposure, development, and etching, resulting in variations in performance. There is a problem of end.

On the other hand, Patent Document 1 describes a technique for locally inducing a piezo effect by providing a semiconductor layer called a strain applying layer 3 under a gate electrode in order to alleviate electric field concentration at the end of the gate electrode.
Separately, Patent Document 2 discloses that a compressive or tensile stress is applied to a semiconductor substrate from an insulating film covering a current path of a gallium arsenide (GaAs) metal-semiconductor field effect transistor (MESFET). A technique for mitigating fluctuations in the current value flowing through the current path due to the stress is described. Patent Document 3 describes a technique for compensating for the temperature dependence of the threshold value of a transistor by using a piezo effect caused by stress. As described above, various discussions have been made on a technique for generating a stress by applying a strain to a semiconductor or an insulating film formed over a semiconductor substrate and changing a current value flowing through the transistor by the stress.
JP 2005-79346 A Japanese Patent Laid-Open No. 10-74776 JP-A-8-222579

An object of the present invention is to provide a semiconductor device having a low on-resistance (R _ON ) and a high off-breakdown voltage.

According to one aspect of the invention,
A first semiconductor layer made of a nitride semiconductor;
A second semiconductor layer formed on the first semiconductor layer and made of a non-doped or n-type nitride semiconductor having a band gap larger than that of the first semiconductor layer;
A control electrode formed directly or via an insulating film on the second semiconductor layer;
First and second main electrodes provided on the second semiconductor layer with the control electrode interposed therebetween;
By applying compressive or extensible stress to the second semiconductor layer formed between the control electrode and the first main electrode, at the interface between the first semiconductor layer and the second semiconductor layer. A first insulating film for changing the generated piezo effect;
By applying compressive or extensible stress to the second semiconductor layer formed between the control electrode and the second main electrode, at the interface between the first semiconductor layer and the second semiconductor layer. A second insulating film for changing the generated piezo effect;
With
The semiconductor device is characterized in that the first insulating film and the second insulating film give different values of stress to the second semiconductor layer.

According to the present invention, a low on-resistance (R _ON ) and a high off-breakdown voltage can be realized in a semiconductor device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic cross-sectional view showing the structure of a GaN-HFET according to the first embodiment of the present invention.
The HFET shown in FIG. 1 has a structure in which a barrier layer 2 made of a non-doped or n-type nitride semiconductor having a substantially uniform thickness is formed on a channel layer 1 made of a non-doped nitride semiconductor.
In the present specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ In the chemical formula 1), it is assumed to include semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges. In addition, the “nitride semiconductor” includes those further containing various impurities added to control the conductivity type.
The band gap of the nitride semiconductor constituting the barrier layer 2 is larger than the band gap of the nitride semiconductor constituting the channel layer 1. Specifically, for example, GaN can be used as the material of the channel layer 1, and AlGaN can be used as the material of the barrier layer 2. Hereinafter, the case where these materials are used as the material of the channel layer 1 and the barrier layer 2 will be described.

On the barrier layer 2, a gate electrode 3 (control electrode) that is Schottky-bonded to the barrier layer 2, a source electrode 4 (first main electrode) that is ohmic-bonded to the barrier layer 2, and a drain electrode 5 (first electrode) 2 main electrodes). A first insulating film 6 is formed on the substrate surface between the gate electrode 3 and the source electrode 4, and a second insulating film 7 is formed on the substrate surface between the gate electrode 3 and the drain electrode 5. For example, aluminum nitride (AlN) is used for the first and second insulating films.
The GaN-HFET uses a two-dimensional electron gas (hereinafter referred to as 2DEG: 2 Dimensional Electron Gas) generated by the piezo effect in the vicinity of the junction interface between the GaN channel layer 1 and the AlGaN barrier layer 2 as a channel, and a voltage applied to the gate electrode. Is operated with on / off control. According to the present embodiment, this piezo effect can be changed also by the film stress of the insulating film formed on the surface of the HFET. The film stress can be generated by giving strain to the insulating film.

FIG. 2 is a chart showing the relationship between the magnitude of the film stress of the insulating film formed on the semiconductor substrate of the GaN-HFET and the current value.
In the figure, the case where the film stress is negative is the compressive stress, and the case where the film stress is positive is the tensile stress. It can be seen that in the region where the film stress is positive, the current value per unit area changes almost linearly according to the film stress. That is, by increasing the film stress, the threshold voltage of the transistor can be lowered. An example of a method for changing the film stress will be described below.

FIG. 3 is a chart showing the relationship between sputtering pressure and film stress when forming an aluminum nitride film (AlN).
It can be seen from the figure that the film stress changes from negative to positive by increasing the sputtering pressure, and the state of the change is almost linear. Although this characteristic is highly dependent on the sputtering apparatus, as a general tendency, when the reaction pressure during film formation is increased, a dense film is formed and a film having a positive film stress (tensile property) is formed. Further, since the film quality tends to become denser when the RF power power is increased, it is possible to obtain a desired film stress by changing the RF power power.
When silicon nitride (SiNx) is formed as an insulating film by plasma CVD (Chemical Vapor Deposition), it is possible to reduce the film stress by increasing the flow ratio of silane (SiH ₄ ) to ammonia (NH ₃ ). is there. This is considered to be because the bond between silicon and nitrogen (N) becomes weak because the bond between silicon (Si) and hydrogen (H) increases.
By using such a method, the threshold voltage can be changed by forming the first insulating film 6 and the second insulating film 7 shown in FIG. By reducing the threshold voltage, the on-resistance (R _ON ) of the element can be reduced, and by increasing the threshold voltage, the breakdown voltage of the element can be kept high. In particular, if the distortion of the first insulating film 6 is formed so that the threshold voltage is low and the distortion of the second insulating film 7 is formed so that the threshold voltage is high, the low on-resistance (R _ON). ) Characteristics and high breakdown voltage can be realized at the same time. Further, since the threshold voltage of the second insulating film 7 can be increased, it is not necessary to use a conventional offset structure, and the gate-drain distance (L _GD ) shown in FIG. L _GS ) or so can be reduced.
FIG. 4 is a schematic cross-sectional view showing the structure of a GaN-HFET according to the second embodiment of the present invention. Elements similar to those of the GaN-HFET shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
The GaN-HFET in this figure is different from the GaN-HFET shown in FIG. 1 in that the third insulating film 8 is between the AlGaN barrier layer 2 and the first and second insulating films 6 and 7. Is formed. The third insulating film 8 is an insulating film having no distortion, such as a silicon nitride film (SiNx) formed by photo-CVD.

In order to maintain the performance of the MOSFET, it is desirable that film formation damage does not enter the semiconductor layer. However, in the case of forming a strained insulating film such as the first insulating film 6 and the second insulating film 7, damage to the semiconductor layer is large. In particular, the more the insulating film having a large strain is obtained, the greater the damage becomes. For this reason, in the GaN-HFET shown in this figure, the third insulating film 8 having no strain is provided between the semiconductor layer and the insulating film having strain. First, the third semiconductor layer 8 with little damage to the semiconductor layer is formed, and then the first insulating film 6 and the second insulating film 7 having a desired strain are formed. With such a structure, film-forming damage at the time of forming the first insulating film 6 and the second insulating film 7 is suppressed by the third semiconductor layer and does not enter the semiconductor layer. Therefore, a low-damage semiconductor layer can be obtained, and GaN-HFET quality having both low on-resistance (R _ON ) characteristics and high breakdown voltage characteristics can be improved.

FIG. 5 is a schematic cross-sectional view showing the structure of a GaN-HFET according to the third embodiment of the present invention. Elements similar to those of the GaN-HFET shown in FIGS. 1 and 4 are given the same reference numerals, and detailed descriptions thereof are omitted.
In the figure, the GaN-HFET differs from the GaN-HFET shown in FIG. 4 in that a third insulating film 8 is also formed below the gate electrode 3 and adopts a MIS (Metal Insulator Semiconductor) type gate structure. It is a point. Since the third insulating film 8 has no distortion, it can be used as a gate insulating film if it is formed to be thin to some extent. Even in this case, the same effect as the GaN-HFET according to the second embodiment described above can be obtained.

FIG. 6 is a schematic cross-sectional view showing the structure of a GaN-HFET according to the fourth embodiment of the present invention. Elements similar to those of the GaN-HFET shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
1 is different from the GaN-HFET shown in FIG. 1 in that the gate-drain distance (L _GD ) is larger than the gate-source distance (L _GS ). . By adopting an offset structure for the GaN-HFET in which the threshold voltage between the gate and the drain is increased by the distortion of the second insulating film, the high breakdown voltage characteristics can be enhanced. Since there is a limit to the high breakdown voltage due to the distortion of the insulating film, the high breakdown voltage characteristic can be promoted by combining with the offset structure.
Combination with the offset structure is also possible in the GaN-HFETs according to the second and third embodiments, and the same effects as those of the present embodiment can be obtained.

  FIG. 7 is a top view of the GaN-HFET shown in FIG. This figure shows the arrangement of each electrode and the insulating film formed therebetween. The source electrode 4, the drain electrode 5, and the gate electrode 3 are formed in a stripe shape, and can be formed symmetrically with respect to the source electrode. A first insulating film 6 is formed between the source electrode 4 and the gate electrode 3, and a second insulating film is formed between the drain electrode 5 and the gate electrode 3.

So far, in the GaN-HFETs according to the first to fourth embodiments, the first insulating film 6 and the second insulating film 7 have been described as having different strain characteristics. Depending on the application, they may have the same distortion characteristics. For example, in the case of a switching element that does not handle a high voltage, both the first and second insulating films employ an insulating film having a distortion characteristic that lowers the threshold voltage, and has a low on-resistance (R _ON ) characteristic. What is necessary is just to improve.

  Further, although aluminum nitride (AlN) has been described as an example of the material of the first and second insulating films, for example, silicon nitride (SiNx) or silicon oxynitride (SiOxNy) can also be used. In the case of silicon nitride (SiNx) or silicon oxynitride (SiOxNy), by changing the flow ratio of silane (Si) and nitrogen (N) or oxygen (O) and nitrogen (N) during plasma CVD, Obtained by distorting the lattice. In addition, aluminum oxide (AlxOy), silicon oxide (SiOx), or the like can be used.

  Further, the present invention can be applied to a GaN-HFET having a recessed gate structure. If an insulating film having a distortion characteristic that lowers the threshold voltage is employed, the amount of recess digging can be reduced.

1 is a schematic cross-sectional view showing a structure of a GaN-HFET according to a first embodiment of the present invention. It is the graph showing the relationship between the magnitude | size of the film stress of the insulating film formed on the semiconductor substrate of GaN-HFET, and an electric current value. 4 is a chart showing the relationship between sputtering pressure and film stress when forming an aluminum nitride film (AlN). It is a schematic cross section showing the structure of the GaN-HFET concerning the 2nd Embodiment of this invention. It is a schematic cross section showing the structure of GaN-HFET concerning the 3rd Embodiment of this invention. It is a schematic cross section showing the structure of GaN-HFET concerning the 4th Embodiment of this invention. It is a top view of GaN-HFET represented in FIG.

Explanation of symbols

1 GaN channel layer, 2 AlGaN barrier layer, 3 gate electrode, 4 source electrode, 5 drain electrode, 6 first insulating film, 7 second insulating film, 8 third insulating film

Claims (5)

A first semiconductor layer made of a nitride semiconductor;
A second semiconductor layer formed on the first semiconductor layer and made of a non-doped or n-type nitride semiconductor having a band gap larger than that of the first semiconductor layer;
A control electrode formed directly or via an insulating film on the second semiconductor layer;
First and second main electrodes provided on the second semiconductor layer with the control electrode interposed therebetween;
By applying compressive or extensible stress to the second semiconductor layer formed between the control electrode and the first main electrode, at the interface between the first semiconductor layer and the second semiconductor layer. A first insulating film for changing the generated piezo effect;
By applying compressive or extensible stress to the second semiconductor layer formed between the control electrode and the second main electrode, at the interface between the first semiconductor layer and the second semiconductor layer. A second insulating film for changing the generated piezo effect;
With
The semiconductor device, wherein the first insulating film and the second insulating film give different values of stress to the second semiconductor layer. The first insulating film applies either the compressive or extensible stress to the second semiconductor layer,
2. The semiconductor device according to claim 1, wherein the second insulating film applies one of the compressive stress and the extensible stress to the second semiconductor layer. A third insulating film provided between the second semiconductor layer and the first insulating film and having a stress lower than that of the first insulating film;
A fourth insulating film provided between the second semiconductor layer and the second insulating film and having a stress lower than that of the second insulating film;
The semiconductor device according to claim 1, further comprising:   By applying the stress from the first insulating film, a channel formed at the interface between the first semiconductor layer and the second semiconductor layer between the first main electrode and the control electrode is formed. By reducing the resistance value and applying the stress from the second insulating film, the interface between the first semiconductor layer and the second semiconductor layer between the second main electrode and the control electrode is applied. 4. The semiconductor device according to claim 2, wherein a resistance value of a channel to be formed is increased. The first and second insulating films are selected from the group consisting of aluminum nitride (AlN), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), and silicon oxide (SiO ₂ ). The semiconductor device according to claim 1, wherein the semiconductor device is any one of the above.

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