CN112382637A - Display back plate, preparation method thereof and display device - Google Patents
Display back plate, preparation method thereof and display device Download PDFInfo
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- CN112382637A CN112382637A CN202011253817.1A CN202011253817A CN112382637A CN 112382637 A CN112382637 A CN 112382637A CN 202011253817 A CN202011253817 A CN 202011253817A CN 112382637 A CN112382637 A CN 112382637A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 238000002161 passivation Methods 0.000 claims abstract description 81
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 292
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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Abstract
The embodiment of the invention provides a display back plate, a preparation method thereof and a display device, wherein the display back plate comprises the following components: a liner plate; a source layer disposed on the liner; a first passivation layer disposed on the source layer; a drain layer disposed on the first passivation layer; arranging a first groove on the source electrode layer, the first passivation layer and the drain electrode layer; the width of the opening of the first groove is larger than that of the bottom; and the semiconductor layer is arranged on the inner wall of the first groove. In the embodiment of the invention, the source electrode layer and the drain electrode layer are arranged on different layers, the first groove is arranged, and the semiconductor layer is arranged on the inner wall of the first groove to connect the source electrode layer and the drain electrode layer, so that the length of the semiconductor layer between the source electrode layer and the drain electrode layer can be ensured to meet the requirement that no channel effect occurs, the aperture ratio of the display device can be improved, and the pixels of the display device can be further improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display back plate, a preparation method of the display back plate and a display device.
Background
Referring to fig. 1, a display backplane of the prior art includes: a gate layer 11, an insulating layer 12, and a semiconductor layer 13 which are stacked in this order; the semiconductor device further comprises a drain electrode 14 and a source electrode 15 which are arranged on two sides of the semiconductor layer 13, wherein the source electrode 15 and the drain electrode 14 are arranged in the same layer; wherein the distance between the source electrode 15 and the drain electrode 14 is W1.
In the display backplane of the prior art, when the distance W1 between the source electrode 15 and the drain electrode 14 is too small, the channel effect is obtained, and when the distance W1 is too large, the aperture ratio of the display device including the display backplane is small, and the pixels of the display device are low.
Disclosure of Invention
The invention provides a display backboard, which aims to solve the problem that pixels of a display device are influenced due to the fact that the distance between a source electrode and a drain electrode in the display backboard is large.
A first aspect of the invention provides a display backplane comprising:
a liner plate;
a source layer disposed on the liner;
the first passivation layer is arranged on one surface, away from the lining plate, of the source electrode layer;
the drain electrode layer is arranged on one surface, away from the lining plate, of the first passivation layer; wherein a first groove is disposed on the source layer, the first passivation layer and the drain layer; the first groove penetrates from one surface, which is far away from the first passivation layer, of the drain electrode layer to one surface, which is facing the source electrode layer, of the lining plate; the width of the opening of the first groove is larger than that of the bottom;
and the semiconductor layer is arranged on the inner wall of the first groove and is connected with the lining plate, the source electrode layer, the first passivation layer and the drain electrode layer.
Optionally, the method further comprises:
the first insulating layer is arranged on one surface, away from the first passivation layer, of the drain layer and covers the semiconductor layer in the first groove;
the first gate layer is arranged in the first groove and is arranged on one side, away from the semiconductor layer, of the first insulating layer;
and the second passivation layer is arranged on the outer side of the first groove and on the surface, away from the drain layer, of the first insulating layer, and the second passivation layer is arranged on the surface, away from the first insulating layer, of the first gate layer in the first groove.
Optionally, between the liner plate and the source layer, further comprising:
the second insulating layer is arranged on the lining plate, and a second groove is formed in one surface, away from the lining plate, of the second insulating layer;
a second gate layer disposed within the second recess;
and the third insulating layer is arranged outside the second groove and on one surface of the second gate layer deviating from the lining plate, and the third insulating layer is arranged in the second groove and on one surface of the second gate layer deviating from the second insulating layer.
Optionally, the shape of the cross-section of the first groove comprises: a triangle shape; the vertex angle of the triangle faces the lining plate.
Optionally, the shape of the cross-section of the first groove comprises: a trapezoid shape; the first bottom edge of the trapezoid faces the lining plate, and the second bottom edge of the trapezoid is far away from the lining plate; the first base edge is smaller than the second base edge.
Optionally, the shape of the cross-section of the second groove is the same as the shape of the cross-section of the first groove.
The second aspect of the invention provides a display device comprising the display back plate,
The third aspect of the present invention provides a method for manufacturing a display backplane, including:
providing a lining plate;
forming a source electrode layer on the liner;
forming a first passivation layer on one surface of the source electrode layer, which is far away from the lining plate;
forming a drain layer on one surface of the first passivation layer, which is far away from the lining plate;
forming a first groove on the source layer, the first passivation layer and the drain layer; the first groove penetrates from one surface, which is far away from the first passivation layer, of the drain electrode layer to one surface, which is facing the source electrode layer, of the lining plate; the width of the opening of the first groove is larger than that of the bottom;
depositing a semiconductor layer on the inner wall of the first groove; the semiconductor layer is connected with the lining plate, the source electrode layer, the first passivation layer and the drain electrode layer.
Optionally, a first insulating layer is formed on a side of the drain layer, which faces away from the first passivation layer, and the semiconductor layer;
forming a first gate layer on one side, away from the semiconductor layer, of the first insulating layer in the first groove;
and a second passivation layer is formed on one surface, which is far away from the drain electrode layer, of the first insulating layer outside the first groove, and on one surface, which is far away from the first insulating layer, of the first gate layer in the first groove.
Optionally, after the providing the liner plate, further comprising:
forming a second insulating layer on the lining plate, and forming a second groove on one surface, facing the source electrode layer, of the second insulating layer;
forming a second gate layer in the second groove;
forming a third insulating layer on one surface, deviating from the lining plate, of the second insulating layer outside the second groove, and forming a third insulating layer on one surface, deviating from the second insulating layer, of the second gate layer in the second groove;
the forming a source layer on the liner comprises: and forming the source electrode layer on one surface of the third insulating layer, which is far away from the lining plate.
An embodiment of the present invention provides a display backplane, including: a liner plate; a source layer disposed on the liner; the first passivation layer is arranged on one surface, away from the lining plate, of the source electrode layer; the drain electrode layer is arranged on one surface, away from the lining plate, of the first passivation layer; wherein a first groove is disposed on the source layer, the first passivation layer and the drain layer; the first groove penetrates from one surface, which is far away from the first passivation layer, of the drain electrode layer to one surface, which is facing the source electrode layer, of the lining plate; the width of the opening of the first groove is larger than that of the bottom; and the semiconductor layer is arranged on the inner wall of the first groove and is connected with the lining plate, the source electrode layer, the first passivation layer and the drain electrode layer. In the embodiment of the invention, the source electrode layer and the drain electrode layer are arranged on different layers, the first groove is arranged, and the semiconductor layer is arranged on the inner wall of the first groove to connect the source electrode layer and the drain electrode layer, so that the length of the semiconductor layer between the source electrode layer and the drain electrode layer can be ensured to meet the requirement that no channel effect occurs, the aperture ratio of the display device can be improved, and the pixels of the display device can be further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic diagram of a display backplane of the prior art;
FIG. 2 is a schematic structural diagram of a display backplane according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a method for manufacturing a display backplane according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a display back plate provided with a first groove according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram illustrating a semiconductor layer disposed in a first groove of a display backplane according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of another display backplane according to an embodiment of the present invention;
fig. 7 is a flowchart illustrating a method for manufacturing a display backplane according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, a schematic diagram of a display backplane structure provided in an embodiment of the present invention is shown, including:
a liner plate 21;
a source layer 22, the source layer 22 being disposed on the liner 21;
a first passivation layer 23, wherein the first passivation layer 23 is disposed on a side of the source layer 22 facing away from the liner 21;
the drain layer 24 is arranged on one side, away from the lining plate 21, of the first passivation layer 23; wherein a first groove a is provided on the source layer 22, the first passivation layer 23 and the drain layer 24; the first groove a penetrates from a side of the drain layer 24 facing away from the first passivation layer 23 to a side of the liner plate 21 facing the source layer 22; the width W1 at the opening of the first groove A is larger than the width W2 of the bottom;
and a semiconductor layer 25, wherein the semiconductor layer 25 is disposed on an inner wall of the first groove a, and is connected to the liner 21, the source layer 22, the first passivation layer 23, and the drain layer 24.
The substrate 21 is a glass substrate, and the materials of the source layer 22 and the drain layer 24 may be materials that can be dry etched, such as: titanium and aluminum. The thickness of the source layer 22 includes: 300nm-800 nm; the thickness of the drain layer 24 includes: 300nm-800 nm. Wherein, the material of the first passivation layer 22 includes: silicon dioxide.
In the embodiment of the present invention, referring to fig. 3, a schematic diagram illustrating a process flow structure of the backplane from C1-C5 in fig. 3 is shown, a first groove a is shown in C2, the first groove a is formed by exposure and etching processes, a width at an opening of the first groove a is W2, and a length of the first groove a is the same as a length of the backing plate 21 in a vertical cross section.
In the embodiment of the present invention, when the outlet width of the first groove a is made larger than the bottom width, as C2 in fig. 3, when the cross section of the first groove a is triangular, the outlet width of the first groove a is the width W2 of the side length a, and the width of the bottom of the first groove a is 0. As shown in fig. 4, when the cross section of the first groove a is a trapezoid, the outlet width of the first groove a is the second base c of the trapezoid, the bottom width of the first groove a is the first base b of the trapezoid, and the second base c is greater than the first base a.
In the embodiment of the present invention, the semiconductor layer 25 is provided on the inner wall of the first groove a; referring to C2 and C3 in fig. 3, the total length of the semiconductor layer 25 is W3+ W4, and when the total length of the semiconductor layer is W1 required in the prior art, the width of the display backplane occupied by the first groove a is W2, where the width W2 is much smaller than W1, which may correspondingly increase the aperture ratio of the display device to which the display backplane belongs, and further increase the pixels of the display device. Referring to fig. 5, when W7+ W8+ W9 and W1 are equal, the width W6 is much smaller than W1, so that the aperture ratio of the display device to which the display backplane belongs can be correspondingly increased, and the pixels of the display device can be further increased.
In the embodiment of the invention, the structure of each layer of the display panel is changed, and the first groove A is arranged, so that the channel effect can be avoided, and the pixels of the display device can be improved.
Wherein, the material of the semiconductor layer 25 includes: IGZO (indium gallium zinc oxide), in the embodiment of the present invention, the material of the semiconductor layer 25 may also be other oxide semiconductor materials, and may be the single layer or multiple layers, which is not limited herein.
In the embodiment of the present invention, referring to C2 in fig. 3, the shape of the cross section of the first groove a includes: a triangle shape; the apex angle a of the triangle faces the liner 21.
In an embodiment of the present invention, referring to fig. 4, a cross-sectional shape of the first groove a includes: a trapezoid shape; the first bottom edge b of the trapezoid faces the lining plate 21, and the second bottom edge c of the trapezoid is far away from the lining plate 21; the first base line b is smaller than the second base line c.
The thickness of the semiconductor layer 25 includes: 20nm-200 nm. The angle of the apex angle alpha of the triangle is greater than 0 DEG and less than 180 deg. The angle of the included angle beta formed by the waist of the trapezoid and the first bottom edge comprises: 90-150 degrees.
In an embodiment of the present invention, the display backplane is a top gate display backplane as shown in fig. 2, and the top gate display backplane further includes:
a first insulating layer 26, wherein the first insulating layer 26 is disposed on a side of the drain layer 24 facing away from the first passivation layer 23, and covers the semiconductor layer 25 in the first groove a;
a first gate layer 27, wherein the first gate layer 27 is disposed in the first groove a and is disposed on a side of the first insulating layer 26 facing away from the semiconductor layer 25;
a second passivation layer 28, outside the first recess a, the second passivation layer 28 being arranged on a side of the first insulating layer 26 facing away from the drain layer 24, and in the first recess, the second passivation layer being arranged on a side of the first gate layer facing away from the first insulating layer.
In the embodiment of the present invention, the first insulating layer 26 is a gate first insulating layer, and the materials include: silicon dioxide or silicon nitride; the first insulating layer 26 may be a single layer or multiple layers, and when the first insulating layer is a double layer, one layer may be made of silicon dioxide and the other layer may be made of silicon nitride. Wherein, the thickness of the first insulating layer 26 includes: 100-500 nm.
In an embodiment of the present invention, the material of the first gate layer 27 includes: molybdenum or copper; the thickness of the first gate layer 27 includes: 300nm-800 nm. The material of the first gate layer 27 may also be selected from other metal materials or alloy materials, and the first gate layer 27 may also be a single layer or a stacked layer, which is not limited herein.
In an embodiment of the present invention, the material of the second passivation layer 28 includes: silicon dioxide and/or silicon nitride, wherein the second passivation layer 28 may be a single layer of silicon dioxide or a double layer of silicon dioxide and silicon nitride, and the thickness of the second passivation layer is 200nm to 400 nm.
In the embodiment of the present invention, referring to fig. 2 and 3, a via structure B is disposed at an edge position of the second passivation layer 28; the via structure B penetrates from the side of the second passivation layer 28 facing away from the first insulating layer 26 to the side of the drain layer 24 facing away from the first passivation layer 23; the display back plate further comprises: an electrode 29; the electrode 29 is disposed in the via structure B, connected to the drain layer 24, and covers the outlet of the via structure B.
Wherein, a via structure B is disposed at the edge position of one side of the second passivation layer 28, and with specific reference to fig. 2 and 3, the cross section of the electrode 29 is T-shaped.
In the embodiment of the present invention, the thickness of the first passivation layer 23 is 100nm to 500 nm. Through the arrangement of the thickness of the first passivation layer, the thickness of the semiconductor and the vertex angle alpha or the included angle beta, the pixel is improved while the display back plate is prevented from generating a channel effect. The thickness of the first passivation layer, the thickness of the semiconductor and the vertex angle alpha or the included angle beta can be adjusted according to the requirements of the specific display back plate.
In an embodiment of the present invention, referring to fig. 6, a bottom gate display backplane is shown, which includes:
between the liner plate and the source layer, further comprising:
the second insulating layer 29 is arranged on the lining plate 21, and a second groove B is formed in one surface, away from the lining plate 21, of the second insulating layer 29;
a second gate layer 30, the second gate layer 30 being disposed within the second recess B;
and a third insulating layer 31, outside the second groove B, a surface of the second insulating layer 29, which is away from the liner 21, of the third insulating layer 31, and in the second groove B, the third insulating layer 31 is disposed on a surface of the second gate layer 30, which is away from the second insulating layer 29.
In the embodiment of the present invention, the shape of the cross section of the second groove B is the same as the shape of the cross section of the first groove a. Wherein the plane of the second gate layer is parallel to the plane of the semiconductor layer.
A second aspect of an embodiment of the present invention provides a display device, including the display backplane described in any one of the above.
An embodiment of the present invention provides a display backplane, including: a liner plate; a source layer disposed on the liner; the first passivation layer is arranged on one surface, away from the lining plate, of the source electrode layer; the drain electrode layer is arranged on one surface, away from the lining plate, of the first passivation layer; wherein a first groove is disposed on the source layer, the first passivation layer and the drain layer; the first groove penetrates from one surface, which is far away from the first passivation layer, of the drain electrode layer to one surface, which is facing the source electrode layer, of the lining plate; the width of the opening of the first groove is larger than that of the bottom; and the semiconductor layer is arranged on the inner wall of the first groove and is connected with the lining plate, the source electrode layer, the first passivation layer and the drain electrode layer. In the embodiment of the invention, the source electrode layer and the drain electrode layer are arranged on different layers, the first groove is arranged, and the semiconductor layer is arranged on the inner wall of the first groove to connect the source electrode layer and the drain electrode layer, so that the length of the semiconductor layer between the source electrode layer and the drain electrode layer can be ensured to meet the requirement that no channel effect occurs, the aperture ratio of the display device can be improved, and the pixels of the display device can be further improved.
Referring to fig. 7, a flow chart of a manufacturing method of a display backplane according to a third aspect of the embodiment of the present invention is shown, where fig. 3 is a schematic structural diagram corresponding to the method, and the method includes:
In an embodiment of the invention, the material of the backing plate comprises glass.
A source layer is formed on the liner, step 102.
And 104, forming a drain layer on one surface of the first passivation layer, which is far away from the lining plate.
In an embodiment of the invention, referring to C1 in fig. 3, the source layer 21, the first passivation layer 22, and the drain layer 23 may be formed sequentially by a deposition process.
In the embodiment of the present invention, referring to C2 in fig. 3, the first groove a may be formed by exposing and etching to form a first groove having a triangular or trapezoidal cross section.
In an embodiment of the present invention, referring to C3 in fig. 3, the semiconductor layer 25 is formed using a deposition process and a patterning process.
In the embodiment of the present invention, when the display backplane is a top gate display backplane, a structural schematic diagram corresponding to a manufacturing method of the top gate display backplane is shown in fig. 3, and the manufacturing method further includes:
and forming a first insulating layer on one surface of the drain layer, which is far away from the first passivation layer, and the semiconductor layer.
And 108, forming a first gate layer on one surface, away from the semiconductor layer, of the first insulating layer in the first groove.
In the embodiment of the present invention, referring to C4 in fig. 3, corresponding to step 107 and step 108.
Step 109, forming a second passivation layer on a surface of the first insulating layer outside the first groove, the surface being away from the drain layer, and a surface of the first gate layer, the surface being away from the first insulating layer, in the first groove.
In the embodiment of the invention, a via hole structure is formed at the edge position of the second passivation layer; the via hole structure penetrates from one surface, deviating from the first insulating layer, of the second passivation layer to one surface, deviating from the first passivation layer, of the drain layer; depositing an electrode within the via structure and covering the electrode with an outlet of the via structure.
In an embodiment of the present invention, referring to C5 in fig. 3, the second passivation layer 28 is deposited and the via structure B is formed.
In the embodiment of the present invention, when the display backplane is a bottom gate display backplane, the method further includes:
forming a second insulating layer on the lining plate, and forming a second groove on one surface, facing the source electrode layer, of the second insulating layer;
forming a second gate layer in the second groove;
forming a third insulating layer on one surface, deviating from the lining plate, of the second insulating layer outside the second groove, and forming a third insulating layer on one surface, deviating from the second insulating layer, of the second gate layer in the second groove;
the forming a source layer on the liner comprises: and forming the source electrode layer on one surface of the third insulating layer, which is far away from the lining plate.
In the embodiments of the present invention, the details of the preparation method are referred to above, and are not described herein again.
The embodiment of the invention provides a preparation method of a display back plate, which comprises the following steps: providing a lining plate; forming a source electrode layer on the liner; forming a first passivation layer on one surface of the source electrode layer, which is far away from the lining plate; forming a drain layer on one surface of the first passivation layer, which is far away from the lining plate; forming a first groove on the source layer, the first passivation layer and the drain layer; the first groove penetrates from one surface, which is far away from the first passivation layer, of the drain electrode layer to one surface, which is facing the source electrode layer, of the lining plate; the width of the opening of the first groove is larger than that of the bottom; depositing a semiconductor layer on the inner wall of the first groove; the semiconductor layer is connected with the lining plate, the source electrode layer, the first passivation layer and the drain electrode layer. In the embodiment of the invention, the source electrode layer and the drain electrode layer are arranged on different layers, the first groove is arranged, and the semiconductor layer is arranged on the inner wall of the first groove to connect the source electrode layer and the drain electrode layer, so that the length of the semiconductor layer between the source electrode layer and the drain electrode layer can be ensured to meet the requirement that no channel effect occurs, the aperture ratio of the display device can be improved, and the pixels of the display device can be further improved.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A display backplane, comprising:
a liner plate;
a source layer disposed on the liner;
the first passivation layer is arranged on one surface, away from the lining plate, of the source electrode layer;
the drain electrode layer is arranged on one surface, away from the lining plate, of the first passivation layer; wherein a first groove is disposed on the source layer, the first passivation layer and the drain layer; the first groove penetrates from one surface, which is far away from the first passivation layer, of the drain electrode layer to one surface, which is facing the source electrode layer, of the lining plate; the width of the opening of the first groove is larger than that of the bottom;
and the semiconductor layer is arranged on the inner wall of the first groove and is connected with the lining plate, the source electrode layer, the first passivation layer and the drain electrode layer.
2. The display backplane of claim 1, further comprising:
the first insulating layer is arranged on one surface, away from the first passivation layer, of the drain layer and covers the semiconductor layer in the first groove;
the first gate layer is arranged in the first groove and is arranged on one side, away from the semiconductor layer, of the first insulating layer;
and the second passivation layer is arranged on the outer side of the first groove and on the surface, away from the drain layer, of the first insulating layer, and the second passivation layer is arranged on the surface, away from the first insulating layer, of the first gate layer in the first groove.
3. The display backplane of claim 1, further comprising, between the liner and the source layer:
the second insulating layer is arranged on the lining plate, and a second groove is formed in one surface, away from the lining plate, of the second insulating layer;
a second gate layer disposed within the second recess;
and the third insulating layer is arranged outside the second groove and on one surface of the second gate layer deviating from the lining plate, and the third insulating layer is arranged in the second groove and on one surface of the second gate layer deviating from the second insulating layer.
4. The display backplane of claim 1, wherein a cross-sectional shape of the first groove comprises: a triangle shape; the vertex angle of the triangle faces the lining plate.
5. The display backplane of claim 1, wherein a cross-sectional shape of the first groove comprises: a trapezoid shape; the first bottom edge of the trapezoid faces the lining plate, and the second bottom edge of the trapezoid is far away from the lining plate; the first base edge is smaller than the second base edge.
6. A display backplane according to claim 4 or 5, wherein the shape of the cross-section of the second groove is the same as the shape of the cross-section of the first groove.
7. A display device comprising the display backplane of any one of claims 1 to 6.
8. A preparation method of a display back plate is characterized by comprising the following steps:
providing a lining plate;
forming a source electrode layer on the liner;
forming a first passivation layer on one surface of the source electrode layer, which is far away from the lining plate;
forming a drain layer on one surface of the first passivation layer, which is far away from the lining plate;
forming a first groove on the source layer, the first passivation layer and the drain layer; the first groove penetrates from one surface, which is far away from the first passivation layer, of the drain electrode layer to one surface, which is facing the source electrode layer, of the lining plate; the width of the opening of the first groove is larger than that of the bottom;
depositing a semiconductor layer on the inner wall of the first groove; the semiconductor layer is connected with the lining plate, the source electrode layer, the first passivation layer and the drain electrode layer.
9. The method of claim 8, further comprising:
forming a first insulating layer on one surface of the drain layer, which is far away from the first passivation layer, and the semiconductor layer;
forming a first gate layer on one side, away from the semiconductor layer, of the first insulating layer in the first groove;
and a second passivation layer is formed on one surface, which is far away from the drain electrode layer, of the first insulating layer outside the first groove, and on one surface, which is far away from the first insulating layer, of the first gate layer in the first groove.
10. The method of claim 8, further comprising, after said providing a liner sheet:
forming a second insulating layer on the lining plate, and forming a second groove on one surface, facing the source electrode layer, of the second insulating layer;
forming a second gate layer in the second groove;
forming a third insulating layer on one surface, deviating from the lining plate, of the second insulating layer outside the second groove, and forming a third insulating layer on one surface, deviating from the second insulating layer, of the second gate layer in the second groove;
the forming a source layer on the liner comprises: and forming the source electrode layer on one surface of the third insulating layer, which is far away from the lining plate.
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| CN202011253817.1A CN112382637A (en) | 2020-11-11 | 2020-11-11 | Display back plate, preparation method thereof and display device |
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| US20020000619A1 (en) * | 2000-05-25 | 2002-01-03 | Nanogate Ltd | Thin film field effect transistor |
| JP2008053450A (en) * | 2006-08-24 | 2008-03-06 | Rohm Co Ltd | Mis-type field effect transistor and manufacturing method thereof |
| CN104022156A (en) * | 2014-05-20 | 2014-09-03 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate, corresponding manufacturing method and display device |
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2020
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020000619A1 (en) * | 2000-05-25 | 2002-01-03 | Nanogate Ltd | Thin film field effect transistor |
| JP2008053450A (en) * | 2006-08-24 | 2008-03-06 | Rohm Co Ltd | Mis-type field effect transistor and manufacturing method thereof |
| CN104022156A (en) * | 2014-05-20 | 2014-09-03 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate, corresponding manufacturing method and display device |
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