JP2008205199A - METHOD OF MANUFACTURING GaN-BASED SEMICONDUCTOR ELEMENT - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a GaN-based semiconductor element preventing the semiconductor layer interface of a gate region from deteriorating even if performing annealing treatment to source and drain electrodes. <P>SOLUTION: An undoped GaN layer 2, an n-type AlGaN drain layer 3, an n-type GaN layer 4, a p-type GaN channel layer 5, and an n-type GaN source layer 6 are formed on a sapphire substrate 1. A lamination structure from the n-type AlGaN drain layer 3 to the n-type GaN source layer 6 is etched from the n-type GaN source layer 6 to a depth where the n-type AlGaN drain layer 3 is exposed so that the section becomes nearly rectangular, the drain and source electrodes 8, 7 are manufactured, and electrode annealing treatment is performed. After that, etching for forming a gate is performed, and a gate insulating film 9 and a gate electrode 10 are formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a GaN-based semiconductor element used for a semiconductor amplifying element such as a power transistor capable of obtaining a large current.

  MOS type FETs and HEMTs (High Electron Mobility Transistors) using GaN-based III-V group compound semiconductors such as GaN and AlGaN for the channel layer are more operating than MOS type FETs and HEMTs using Si, GaAs, etc. The device has been attracting attention as a device capable of high temperature operation and large current operation with a high withstand voltage and a small on-resistance.

  For example, as shown in Patent Document 1 and Non-Patent Document 1, the GaN-based semiconductor element has a MIS (Metal Insulator Semiconductor) structure in which a source electrode, a gate electrode, and a drain electrode are provided on the same surface side. In addition, a GaN-based semiconductor element having a MIS structure in which a source electrode is provided on the same surface side as a gate electrode among a source electrode and a drain electrode is known.

For example, according to Patent Document 1, when a vertical MIS structure of GaN is manufactured, an n-type GaN drain layer, a p-type GaN channel layer, and an n-type GaN source layer are stacked on a substrate, and then the stacked structure is removed by etching. An inclined surface or a vertical surface is formed on the side surface of the first electrode, and then a source electrode and a drain electrode are formed, and then a gate electrode is formed.
JP 2003-163354 A Satoshi Okubo, “GaN is behind the evolution of equipment, not just shining”, June 5, 2006, Nikkei Electronics, p. 51-60

  In the above prior art method, the source electrode or the drain electrode is formed after the GaN-based semiconductor layer wall surface for forming the gate insulating film and the gate electrode is formed.

  When a Ti—Al alloy, which is a metal more preferable as an electrode to be in ohmic contact with the n-type GaN layer, is formed using the above-described conventional method, a thermal alloy (annealing treatment) at about 500 ° C. is required to obtain ohmic contact. Therefore, the already fabricated GaN-based semiconductor layer wall surface is damaged by heat such as nitrogen depletion due to the electrode annealing treatment, and the channel characteristics are deteriorated.

  In electronic devices such as FETs and HEMTs, channel operating characteristics are an important factor, which affects on-resistance and on-off response characteristics, and therefore, an inversion channel (inversion layer) is formed as described above. There has been a problem that the characteristics of the semiconductor layer wall surface where the surface is present are deteriorated due to thermal damage.

  The present invention was devised to solve the above-described problems, and provides a method for manufacturing a GaN-based semiconductor element in which the semiconductor layer interface in the gate region does not deteriorate even when annealing of the source electrode and the drain electrode is performed. The purpose is to do.

  In order to achieve the above object, a first aspect of the present invention is a stacked structure including a semiconductor layer containing a p-type impurity and two n-type semiconductor layers arranged with the semiconductor layer containing the p-type impurity interposed therebetween. A gate electrode is formed on the surface of the semiconductor layer containing the p-type impurity exposed by forming the wall surface, the gate electrode being interposed between the semiconductor layer containing the p-type impurity and the two n-type semiconductor layers. A method of manufacturing a GaN-based semiconductor device in which a source electrode is formed on the same side as a gate electrode, wherein the wall surface is formed after electrode annealing of the source electrode is performed. A method for manufacturing a GaN-based semiconductor device.

  According to a second aspect of the present invention, a region having different conduction characteristics is formed on the surface of the semiconductor layer containing the p-type impurity, and a gate insulating film is formed in contact with the region. This is a method for manufacturing a GaN-based semiconductor device.

  According to a third aspect of the present invention, mesa etching is performed on the same surface as the surface on which the source electrode is formed, and a drain is formed in the n-type semiconductor layer located below the exposed semiconductor layer containing the p-type impurity. 3. The GaN-based semiconductor device according to claim 1, wherein the wall surface is formed after an electrode is formed and electrode annealing of the source electrode and the drain electrode is performed. 4. It is a manufacturing method.

  The invention according to claim 4 is characterized in that a drain electrode is formed on the side opposite to the surface on which the source electrode is formed. This is a method for manufacturing a semiconductor device.

  According to the present invention, the formation of the semiconductor layer wall surface including the p-type impurity including the channel region where the inversion distribution operation is performed is performed after the annealing process of the source electrode manufactured on the same surface side as the gate electrode. Deterioration of the surface of the semiconductor layer containing the p-type impurity can be prevented, and deterioration of channel operation characteristics can be prevented.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional structure of a GaN-based semiconductor device of the present invention.

The GaN-based semiconductor element of the present invention uses a III-V group GaN-based semiconductor that is a hexagonal compound semiconductor, and the III-V group GaN-based semiconductor is a quaternary mixed crystal Al _x Ga _y In _z. N (x + y + z = 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1). FIG. 1 shows an example of an npn structure.

  On the sapphire substrate 1, an undoped GaN layer 2, an n-type AlGaN drain layer 3, an n-type GaN layer 4, a p-type GaN channel layer 5 (corresponding to a semiconductor layer containing p-type impurities), and an n-type GaN source layer 6 are formed. ing. Both side surfaces of the laminated structure from the n-type AlGaN drain layer 3 to the n-type GaN source layer 6 are etched from the n-type GaN layer source layer 6 to a depth at which the n-type AlGaN drain layer 3 is exposed so that the cross section is substantially rectangular. Has been. The n-type AlGaN drain layer 3 has a lead portion 3a drawn in the horizontal direction. A drain electrode 8 is formed in contact with the surface of the lead portion 3a.

  On the other hand, a U-shaped groove B is formed at the center of the laminated structure of the n-type GaN source layer 6 to the n-type GaN layer 4 until reaching the middle of the n-type GaN layer 4. The structure is separated into two mesa regions, and a source electrode 7 is formed on the n-type GaN source layer 6 in each mesa region. A gate insulating film 9 is formed over the entire wall surface of the trench B and over the upper surface of the n-type GaN source layer 6, and a gate electrode 10 is stacked on the gate insulating film 9 in the region of the gate insulating film 9. (MIS structure). The groove B may be V-shaped, but a U-shape is more preferable in order to avoid dielectric breakdown due to electric field concentration at the tip of the V-shaped acute angle. As described above, in this embodiment, all of the source electrode 7, the drain electrode 8, and the gate electrode 10 are provided on the same surface side (front surface side) of the GaN-based semiconductor element.

  A region near the wall surface of the groove B in the p-type GaN channel layer 5 forms a region 5 a facing the gate electrode 10. The side surface of the mesa region including the region 5a becomes a region corresponding to the gate. When an appropriate bias voltage is applied to the gate electrode 10 in the region 5a, the n-type GaN layer source layer 6 and the n-type GaN layer 4 are electrically connected. An inversion channel (inversion distribution) is formed to be conducted to the.

  Two-dimensional electron gas is generated in the undoped GaN layer 2 in the vicinity of the interface between the undoped GaN layer 2 and the n-type AlGaN drain layer 3 due to the piezoelectric effect. The undoped GaN layer 2 is formed on the sapphire substrate 1 by so-called selective lateral epitaxial growth (ELO), and includes a region having a high dislocation density and a region having a low dislocation density (non-dislocation region) in the horizontal direction along the substrate surface. have. The formation positions of the regions other than the lead portions 3a are selected so as to have a laminated structure of regions having low dislocation density (non-dislocation regions).

  The undoped GaN layer 2 is grown on the sapphire substrate 1 so that its main surface (surface parallel to the sapphire substrate 1) is, for example, a C plane (0001). In this case, the n-type AlGaN drain layer 3, n-type GaN layer 4, p-type GaN channel layer 5, and n-type GaN source layer 6 stacked on the undoped GaN layer 2 by epitaxial growth again have a C plane (0001) as the main component. It will be laminated as a surface. The wall surface of the groove B is, for example, a nonpolar surface (M surface (10-10) or A surface (11-20)), or a semipolar surface ((10-1-1), (10-1-3), (11-22) etc.).

  On the undoped GaN layer 2, the main surface is a nonpolar surface (M surface (10-10) or A surface (11-20)), or semipolar surface ((10-1-1), (10-1-3)). , (11-22), etc.) may be grown on the sapphire substrate 1. In this case, accordingly, the n-type AlGaN drain layer 3 to the n-type GaN source layer 6 are laminated with the corresponding crystal plane as the main surface.

The gate insulating film 9 can be made of, for example, nitride or oxide. More specifically, if the gate insulating film is made of silicon nitride (Si _x N _y ) or silicon oxide, the charge at the interface with the p-type GaN layer 6 can be reduced, and the carrier mobility in the channel region 5a. Can be improved. That is, channel resistance can be reduced. The gate electrode 10 is made of a conductive material such as a Ni—Au alloy, a Ni—Ti—Au alloy, a Pd—Au alloy, a Pd—Ti—Au alloy, a Pd—Pt—Au alloy, Pt, Al, or polysilicon. The

  The drain electrode 8 is preferably made of a metal containing at least Al. For example, the drain electrode 8 can be made of a Ti—Al alloy. Similarly, the source electrode 7 is preferably made of a metal containing Al, for example, a Ti—Al alloy. By configuring the drain electrode 8 and the source electrode 7 with a metal containing Al, good contact with a wiring layer (not shown) can be obtained. In addition, the drain electrode 8 and the source electrode 7 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide). .

In each semiconductor layer, Si is used as an n-type dopant, and Mg is used as a p-type dopant. Since the n-type AlGaN drain layer 3 is in ohmic contact with the drain electrode 8 and the n-type GaN source layer 6 is in ohmic contact with the source electrode 7, for example, the impurity concentration is 2 × 10 ¹⁸ cm ^−3. The p-type GaN channel layer 5 needs to have a high carrier concentration so that the device is not turned on when no voltage is applied to the gate electrode. Impurity Mg is doped so as to be 3 × 10 ¹⁹ cm ⁻³ .

  Next, the operation of the MIS type GaN-based semiconductor element will be briefly described. A reverse bias voltage is applied between the source electrode 7 and the drain electrode 8 so that the drain electrode 8 side is positive. As a result, a reverse voltage is applied to the pn junction composed of the n-type GaN layer 4 and the p-type GaN channel layer 5. At this time, the source-drain is cut off, but in this state, if a predetermined voltage is applied between the source electrode 7 and the gate electrode 10 so that the gate electrode 10 side becomes positive, the p-type GaN channel layer 5 Is applied to the gate electrode 10.

  As a result, electrons are induced in the region 5a of the p-type GaN channel layer 5 to form an inversion channel. Through this inversion channel, the n-type GaN layer 4 and the n-type GaN source layer 6 are electrically connected, and electrons pass from the source electrode 7 through the side surface on the groove B side in the n-type GaN source layer 6 and the region 5a, and n Since it moves to the n-type AlGaN drain layer 3 via the type GaN layer 4 (current flows in the reverse path), the source and drain are conducted. In this manner, a normally-off operation is possible in which the source and drain are rendered conductive when a predetermined bias is applied to the gate electrode 10 and the source and drain are disconnected when no bias is applied to the gate electrode 10.

  When the inversion channel is formed in the region 5a, as described above, electrons supplied from the source electrode 7 flow from the n-type GaN source layer 6 through the region 5a into the n-type GaN layer 4 and are undoped. The two-dimensional electron gas generated near the interface between the GaN layer 2 and the n-type AlGaN drain layer 3 goes to the drain electrode 8. Since the two-dimensional electron gas is widely distributed at the interface between the undoped GaN layer 2 and the n-type AlGaN drain layer 3, the electrons flowing from the region 5a into the n-type GaN layer 4 are caused by the movement of electrons in the lateral direction. Resistance can be reduced.

  Next, a method for manufacturing the GaN-based semiconductor device of FIG. 1 will be described below with reference to FIGS. As a manufacturing method, an MOCVD method (metal organic chemical vapor deposition method) is mainly used. First, the sapphire substrate 1 is transported into the MOCVD apparatus, the substrate temperature is raised to 1000 ° C. or higher, and the undoped GaN layer 2, n-type AlGaN drain layer 3, n-type GaN layer 4, p-type are formed on the sapphire substrate 1. The GaN channel layer 5 and the n-type GaN source layer 6 are epitaxially grown in order to form a stacked structure as shown in FIG.

For example, when a GaN layer is formed, trimethylgallium (TMGa), which is a Ga atom source gas, and ammonia (NH ₃ ), which is a nitrogen atom source gas, are used together with hydrogen or nitrogen as a carrier gas. In the case of n-type GaN, silane (SiH ₄ ) or the like as an n-type dopant gas, and in the case of p-type GaN, CP ₂ Mg (cyclopentadiethyl magnesium) or the like as a p-type dopant gas is used. Add to the reaction gas. When fabricating the AlGaN layer, TMGa, added trimethylaluminum (TMA) in NH _3.

  In this way, by supplying the reaction gas corresponding to the components of each semiconductor layer, the dopant gas for making the n-type and p-type, the crystal is grown in order by changing to the optimum growth temperature, thereby having a predetermined composition. A semiconductor layer of a predetermined conductivity type was formed to a required thickness. The doping concentration of impurities was controlled by the flow rate of each source gas.

  Next, first mesa etching is performed from the n-type GaN source layer 6 to the middle of the n-type AlGaN drain layer 3 in the wafer having the above-described laminated structure to produce a groove A, and a plurality of stripe-shaped ridge portions are formed. At the same time, a lead portion 3 a made of an extension of the n-type AlGaN drain layer 3 is formed at the same time. The first mesa etching is performed by dry etching using plasma. After the trench A is formed, the drain electrode 8 and the source electrode 7 are formed, respectively, and the state shown in FIG. 3 is obtained. The drain electrode 8 is formed in contact with the bottom surface of the groove A, that is, the surface of the lead portion 3a.

  After the drain electrode 8 and the source electrode 7 are produced by sputtering or vapor deposition, for example, they are annealed at a temperature of about 500 ° C. in a nitrogen atmosphere, so that the contact resistance between the drain electrode 8 and the n-type AlGaN drain layer 3 is The contact resistance between the source electrode 7 and the n-type GaN source layer 6 is reduced. When performing the annealing treatment, heat treatment is performed with the surface (upper side in FIG. 3) on which the source electrode 7 and the drain electrode 8 are formed facing a heat source such as a heater. Since it is not formed and a region corresponding to the region 5a is not exposed on the surface, thermal damage from a heat source due to annealing treatment can be prevented.

  Next, as shown in FIG. 4, a U-shaped groove B is formed by the second mesa etching in the vicinity of the central portion of each stacked structure formed in a stripe shape to produce two mesa regions. The formation position of the groove B is determined so that the dislocation-free region of the p-type GaN channel layer 5 is exposed from the side wall to form the wall surface of the groove B. The second mesa etching is performed by dry etching (anisotropic etching) using plasma from the n-type GaN source layer 6 to the middle of the n-type GaN layer 4. Also, wet etching is performed to improve the exposed surface damaged by dry etching. When wet etching treatment is performed on a wall surface damaged by dry etching, a new wall surface from which the damaged surface layer is removed appears.

It is preferable to use a basic solution such as KOH (potassium hydroxide) or NH ₄ OH (ammonia water) for the wet etching. By reducing the damage on the wall surface of the groove B, the crystal state of the channel region 5a can be kept good, and the interface with the gate insulating film 9 can be made a good interface. The position can be reduced. Further, low-damage dry etching may be used instead of wet etching.

  Next, as shown in FIG. 5, a gate insulating film 9 is formed on the wall surface of the trench B. The gate insulating film 9 is formed so as to cover the wall surface of the trench B and to cover a part of the upper surface of the n-type GaN source layer 6 constituting the mesa region. The gate insulating film 9 is formed by using a PECVD (plasma enhanced chemical vapor deposition) method or the like, but more preferably, an ECR (Electron Cyclotron Resonance) sputtering method is applied.

When the ECR sputtering method is used, a p-type GaN channel layer is formed in a region near the wall surface of the U-shaped groove B, particularly a region under the wall surface of the groove B of the p-type GaN channel layer 5 by Ar plasma irradiation or the like in the ECR sputtering method. 5, a semiconductor layer having a different conduction characteristic is formed. The semiconductor layers having different conduction characteristics are p ^- type, i-type, or n-type. In this case, the region 5a is formed in the region of the semiconductor layer having different conduction characteristics.

  As described above, the p-type GaN channel layer 5 has semiconductor layers having different conduction characteristics. By forming an inversion channel in this layer, inversion distribution is likely to occur, and the on-voltage of the transistor can be lowered. it can.

  After the formation of the insulating film 9, as shown in FIG. 6, the gate electrode 10 is formed on the gate insulating film 9 by vapor deposition so as to be within the region of the gate insulating film 9. In this manner, the MIS type GaN-based semiconductor device of FIG. 1 is completed.

  In the above embodiment, the source electrode 7, the drain electrode 8, and the gate electrode 10 are all formed on the same surface side. However, the drain electrode 8 is formed on the surface side opposite to the gate electrode 10. In this case, after the annealing of the electrode of the source electrode 7 formed on the same surface as the gate electrode 10 is finished, a wall surface including the region 5a is formed by etching, and the wall surface including the region 5a is formed on the wall surface including the region 5a. By sequentially forming the gate insulating film and the gate electrode and then forming the drain electrode on the back side, the same effect as in the above embodiment can be obtained. Since the back surface can have a large electrode area, the contact resistance can be kept low without performing electrode annealing.

A plurality of mesa regions formed in a stripe shape on the sapphire substrate 1 each form a unit cell. The gate electrode 10 becomes a common electrode in adjacent mesa regions, and the drain electrode 8 can also be shared by adjacent mesa regions. The drain electrode 8, the gate electrode 10 and the source electrode 7 are commonly connected at positions not shown.

It is a figure which shows the cross-section of the GaN-type semiconductor element of this invention. It is a figure which shows 1 process of the manufacturing method of the GaN-type semiconductor element of this invention. It is a figure which shows 1 process of the manufacturing method of the GaN-type semiconductor element of this invention. It is a figure which shows 1 process of the manufacturing method of the GaN-type semiconductor element of this invention. It is a figure which shows 1 process of the manufacturing method of the GaN-type semiconductor element of this invention. It is a figure which shows 1 process of the manufacturing method of the GaN-type semiconductor element of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Sapphire substrate 2 Undoped GaN layer 3 n-type AlGaN drain layer 4 n-type GaN layer 5 p-type GaN channel layer 5a region 6 n-type GaN source layer 7 source electrode 8 drain electrode 9 gate insulating film 10 gate electrode

Claims (4)

A semiconductor layer including a p-type impurity and a semiconductor layer including two n-type semiconductor layers, each including a stacked structure including a semiconductor layer including a p-type impurity and two n-type semiconductor layers arranged with the semiconductor layer including the p-type impurity interposed therebetween A gate electrode is formed on the surface of the semiconductor layer containing the p-type impurity exposed by forming the wall surface via a gate insulating film, and the source electrode is formed on the same side as the gate electrode. A method of manufacturing a GaN-based semiconductor device,
The method of manufacturing a GaN-based semiconductor device, wherein the wall surface is formed after electrode annealing of the source electrode is performed.   2. The method of manufacturing a GaN-based semiconductor element according to claim 1, wherein a region having different conduction characteristics is formed on a surface of the semiconductor layer containing the p-type impurity, and a gate insulating film is formed in contact with the region.   Mesa etching is performed on the same surface as the surface on which the source electrode is formed, and a drain electrode is formed on the exposed n-type semiconductor layer under the semiconductor layer containing the p-type impurity. The method for manufacturing a GaN-based semiconductor device according to claim 1, wherein the wall surface is formed after electrode annealing of the electrode. The method for manufacturing a GaN-based semiconductor device according to claim 1, wherein a drain electrode is formed on a side opposite to a surface on which the source electrode is formed.

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