CN116960174B - P-channel semiconductor device and preparation method thereof - Google Patents
P-channel semiconductor device and preparation method thereof Download PDFInfo
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- CN116960174B CN116960174B CN202311204573.1A CN202311204573A CN116960174B CN 116960174 B CN116960174 B CN 116960174B CN 202311204573 A CN202311204573 A CN 202311204573A CN 116960174 B CN116960174 B CN 116960174B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 193
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 86
- 239000004047 hole gas Substances 0.000 claims abstract description 76
- 238000000407 epitaxy Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 55
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 230000006911 nucleation Effects 0.000 claims description 18
- 238000010899 nucleation Methods 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 16
- 150000001875 compounds Chemical class 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 263
- 238000010586 diagram Methods 0.000 description 21
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 14
- 229910002601 GaN Inorganic materials 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 229910002704 AlGaN Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- -1 fluorine ions Chemical class 0.000 description 1
- 239000010437 gem Substances 0.000 description 1
- 229910001751 gemstone Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004969 ion scattering spectroscopy Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Junction Field-Effect Transistors (AREA)
Abstract
The invention relates to a P-channel semiconductor device and a preparation method thereof, belongs to the technical field of semiconductors, and is used for solving the problem of high preparation difficulty of the P-channel device. The P channel semiconductor device provided by the invention comprises an epitaxial body formed by a channel layer and a barrier layer, wherein the barrier layer is obtained by epitaxy from a first vertical interface of the channel layer; the channel layer comprises an N-type semiconductor layer and a P-type semiconductor layer which are arranged from bottom to top; the epitaxial body is divided into a first epitaxial body and a second epitaxial body which are parallel from the top, and vertical two-dimensional hole gas in the first epitaxial body is isolated from vertical two-dimensional hole gas in the second epitaxial body in an insulating manner; a first electrode provided on top of the first epitaxial body; a second electrode provided on top of the second epitaxial body; a third electrode is provided on the barrier layer laterally of the epitaxial body extending from the first vertical interface. The enhanced P-channel semiconductor device provided by the invention can provide vertical high-density hole gas, and the preparation difficulty of the P-channel device is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a P-channel semiconductor device and a preparation method thereof.
Background
III-V compounds are important semiconductor materials, such as AlN, gaN, inN, alP, gaAs and compounds of these materials, such as AlGaN, inGaN, alInGaN, etc. Because III-V compound has advantages of direct band gap, wide band gap, high breakdown field intensity, etc., III-V compound semiconductor represented by GaN is widely used in the fields of light emitting device, power electronics, radio frequency device, etc.
III-V compounds are a class of polar semiconductor materials that have a fixed polarization charge at the surface of the polar semiconductor or at the interface of two different polar semiconductors. The presence of these fixed polarization charges can attract mobile carriers such as electrons or holes, thereby forming a two-dimensional electron gas (2 DEG) or a two-dimensional hole gas (2 DHG), and has a higher surface charge density. Meanwhile, the effect of ion scattering and the like of the two-dimensional electron gas or the two-dimensional hole gas is greatly reduced because doping of the semiconductor material is not needed, so that the semiconductor material has higher mobility. Taking the HEMT (High Electron Mobility Transistors, high electron mobility transistor) principle of fig. 1 as an example, fig. 1 is a schematic structural diagram of a lateral depletion HEMT in the prior art. The bottom layer of the HEMT is a substrate layer (generally made of SiC, si and other materials), then an N-type GaN is epitaxially grown to serve as a channel layer, a P-type AlGaN which is epitaxially grown on the channel layer serves as a barrier layer, an AlGaN/GaN heterojunction is formed at the interface of the channel layer and the barrier layer, and a two-dimensional electron gas (2 DEG) is formed at the heterojunction. And depositing a grid electrode (G) which is in insulating contact on the barrier layer, and carrying out high-concentration doping on the source electrode (S) region and the drain electrode (D) region so that the source electrode and the drain electrode are connected with two-dimensional electrons in a channel to form ohmic contact.
Although the III-V compound can generate high-density hole gas, the conventional device structure is mostly a planar transverse device as shown in fig. 1, so that the hole integration degree per unit area is not high enough, and a P-channel device with the effect similar to that of an N-channel device is difficult to prepare.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a P-channel semiconductor device and a preparation method thereof, which are used for reducing the preparation difficulty of the P-channel semiconductor device.
In order to solve the technical problems described above, the present invention provides a P-channel semiconductor device including an epitaxial body composed of a channel layer and a barrier layer, a first electrode, a second electrode, and a third electrode; the channel layer of the epitaxial body is provided with a first vertical interface, and the barrier layer is obtained by epitaxy from the first vertical interface of the channel layer; the channel layer comprises an N-type semiconductor layer and a P-type semiconductor layer from bottom to top, vertical two-dimensional hole gas is generated in the P-type semiconductor layer near the interface area with the barrier layer, and the vertical two-dimensional hole gas is exhausted in the N-type semiconductor layer; the epitaxial body is separated into a first epitaxial body and a second epitaxial body which are positioned at two sides of the isolation region in parallel through an isolation region with the depth being larger than the thickness of the P-type semiconductor layer and smaller than the overall thickness of the epitaxial body from the top, and vertical two-dimensional hole gas in the first epitaxial body is isolated from vertical two-dimensional hole gas in the second epitaxial body in an insulating manner; the first electrode is provided on top of the first epitaxial body; the second electrode is provided on top of the second epitaxial body; the third electrode is directly or indirectly provided on the barrier layer extending from the first vertical interface on the side surface of the epitaxial body, and covers a partial region of the P-type semiconductor layer in the first epitaxial body, a partial region of the P-type semiconductor layer in the second epitaxial body, and a partial region of the N-type semiconductor layer, respectively, and is capable of electrically connecting the two-dimensional hole gas in the first epitaxial body and the two-dimensional hole gas in the second epitaxial body when a voltage is applied to the third electrode; wherein the channel layer and the barrier layer are semiconductor layers of III-V compounds, respectively.
In another aspect, the present invention also provides a method for preparing a P-channel semiconductor device, including the steps of:
providing a channel layer, wherein the channel layer comprises an N-type semiconductor layer and a P-type semiconductor layer from bottom to top, and the channel layer is provided with a first vertical interface;
a barrier layer is obtained through epitaxy from a first vertical interface of the channel layer, vertical two-dimensional hole gas is generated in the P-type semiconductor layer in a nearby area close to the boundary with the barrier layer, and the vertical two-dimensional hole gas is exhausted in the N-type semiconductor layer; the channel layer and the barrier layer form an epitaxial body;
an isolation region with the depth larger than the thickness of the P-type semiconductor layer and smaller than the whole thickness of the epitaxial body is obtained from the top of the epitaxial body in an ion implantation mode or an etching mode, and a first epitaxial body and a second epitaxial body which are parallel are arranged on two sides of the isolation region, wherein vertical two-dimensional hole gas in the first epitaxial body is isolated from vertical two-dimensional hole gas in the second epitaxial body in an insulating mode;
providing a first electrode on top of the first epitaxial body;
providing a second electrode on top of the second epitaxial body;
providing a third electrode directly or indirectly on the barrier layer extending from the first vertical interface on the side surface of the epitaxial body, wherein the third electrode covers a partial region of the P-type semiconductor layer in the first epitaxial body, a partial region of the P-type semiconductor layer in the second epitaxial body and a partial region of the N-type semiconductor layer respectively, and can electrically connect the two-dimensional hole gas in the first epitaxial body and the two-dimensional hole gas in the second epitaxial body when a voltage is applied to the third electrode;
Wherein the channel layer and the barrier layer are semiconductor layers of III-V compounds, respectively.
The invention realizes a vertical enhanced P-channel semiconductor device, because the P-type semiconductor layer in the channel layer is arranged on the top layer, and the electrodes serving as the source electrode and the drain electrode are also arranged on the top layer, the preparation difficulty of the P-channel device is reduced; because the vertical structure is adopted, the vertical high-density cavity gas can be provided, so that the problem of low cavity integration level in a P channel of a transverse device is solved; from the safety aspect, the enhanced device provided by the invention can improve the safety of an application circuit.
Drawings
Preferred embodiments of the present invention will be described in further detail below with reference to the attached drawing figures, wherein:
fig. 1 is a schematic diagram of a prior art structure of a laterally depleted HEMT;
fig. 2 is a schematic view of the structure principle of a longitudinal section of a P-channel semiconductor device according to the first embodiment of the present invention;
fig. 3 is a schematic diagram of a structure of the P-channel semiconductor device shown in fig. 2 in a direction a;
fig. 4 is a schematic diagram of a B-direction structure of the P-channel semiconductor device shown in fig. 2;
fig. 5 is a schematic flow chart of a method for manufacturing a P-channel semiconductor device according to the first embodiment of the invention;
Fig. 6 is a schematic view of the structural principle of a longitudinal section of a substrate according to the first embodiment of the present invention;
fig. 7 is a schematic view of the structure of a longitudinal section of an epitaxial channel layer 110 on a substrate 3 according to an embodiment of the present invention;
fig. 8 is a schematic view of the structure in longitudinal cross section after the channel layer 110 and the barrier layer 120 are epitaxially grown on the substrate according to an embodiment of the present invention;
fig. 9 is a schematic diagram of the structure of a longitudinal section after removing the top barrier layer 120 according to an embodiment of the present invention;
fig. 10 is a schematic structural view of a longitudinal section in the a direction of the epitaxial body 1 shown in fig. 9 after an ion implantation process;
fig. 11 is a schematic view of a part of the structure in the B direction after the ion implantation process is performed on the epitaxial body 1 shown in fig. 9;
fig. 12 is a schematic view of the structure of a longitudinal section after providing electrodes on the epitaxial body 1 according to the embodiment of the present invention;
FIG. 13 is a schematic view of the structural principle of the A-direction longitudinal section of FIG. 12;
FIG. 14 is a schematic view of a portion of the structure in the direction B of FIG. 12;
fig. 15 is a schematic structural diagram of an a-direction longitudinal section of a P-channel semiconductor device according to a second embodiment of the present invention;
fig. 16 is a schematic view of a B-direction portion of the P-channel semiconductor device of fig. 15;
Fig. 17 is a schematic view of the structure principle of a longitudinal section of a P-channel semiconductor device according to the third embodiment of the present invention;
FIG. 18 is a schematic view of the structural principle of the longitudinal section A of FIG. 17;
FIG. 19 is a schematic view of a portion of the structure in the direction B of FIG. 17;
fig. 20 is a schematic structural diagram of an a-direction longitudinal section of a P-channel semiconductor device according to a fourth embodiment of the present invention;
fig. 21 is a schematic structural view of a longitudinal section of a P-channel semiconductor device according to a fifth embodiment of the present invention;
FIG. 22 is a schematic view of the structural principle of the A-direction longitudinal section of FIG. 21;
FIG. 23 is a schematic view of a portion of the structure in the direction B of FIG. 21;
fig. 24 is a schematic structural view of a longitudinal section of a P-channel semiconductor device according to a sixth embodiment of the present invention;
FIG. 25 is a schematic view of the structural principle of the A-direction longitudinal section of FIG. 24; and
fig. 26 is a schematic diagram of a part of the structure in the B direction of fig. 24.
Reference numerals illustrate:
1. an epitaxial body;
11. a first epitaxial body; 12. a second epitaxial body; 13. an isolation region;
110. a channel layer;
111. a P-type semiconductor layer; 112. an N-type semiconductor layer; 113. a third semiconductor layer;
120. a barrier layer;
130. two-dimensional hole gas;
21. a first electrode; 22. a second electrode; 23. a third electrode; 231. a first sub-electrode; 232. a second sub-electrode; 233. a conductive metal; 212. a first electrode lead-out terminal; 221. a second lead-out metal; 222. a second electrode lead-out terminal;
3. A substrate;
31. a first mesa; 32. a second mesa; 33. a substrate step side; 34. an epitaxial mask;
4. a nucleation layer;
51. a medium; 52. a first dielectric layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the application may be practiced. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application.
The invention provides a P channel semiconductor device, which comprises an epitaxial body formed by a channel layer and a barrier layer, a first electrode, a second electrode and a third electrode; the channel layer of the epitaxial body is provided with a first vertical interface, and the barrier layer is obtained by epitaxy from the first vertical interface of the channel layer; the channel layer comprises an N-type semiconductor layer and a P-type semiconductor layer from bottom to top, vertical two-dimensional hole gas is generated near the junction between the P-type semiconductor layer and the barrier layer, and the vertical two-dimensional hole gas is exhausted in the N-type semiconductor layer; the epitaxial body is divided into a first epitaxial body and a second epitaxial body from the top downwards, and vertical two-dimensional hole gas in the first epitaxial body is isolated from vertical two-dimensional hole gas in the second epitaxial body in an insulating manner; the first electrode is provided on top of the first epitaxial body; the second electrode is provided on top of the second epitaxial body; the third electrode is directly or indirectly provided on the barrier layer extending from the first vertical interface on the side surface of the epitaxial body, and covers a partial region of the P-type semiconductor layer in the first epitaxial body, a partial region of the P-type semiconductor layer in the second epitaxial body, and a partial region of the N-type semiconductor layer, respectively, and is capable of electrically connecting the two-dimensional hole gas in the first epitaxial body and the two-dimensional hole gas in the second epitaxial body when a voltage is applied to the third electrode; wherein the channel layer and the barrier layer are semiconductor layers of III-V compounds, respectively.
In the invention, the vertical side surface of the epitaxial body is used as the functional area of the device, and the vertical side surface of the epitaxial body is attached to the boundary of the barrier layer in the P-type semiconductor layerVertical high-density two-dimensional hole gas is generated nearly, so that high hole integration degree in unit area is realized, and the utilization rate of the wafer area is improved. When the channel layer is vertical P-N-P type, the acceptor activation capability of the lower P type semiconductor layer is affected by the upper N type semiconductor layer, so that the hole mobility is reduced, while the P type semiconductor layer is positioned on the top layer of the channel layer, the acceptor activation capability is not affected, and the two-dimensional hole gas concentration is more than 1E18cm -3 Hole mobility greater than 30cm 2 V/s. In addition, the invention is used for connecting electrodes in a current path, such as a source electrode and a drain electrode of a transistor, to be manufactured on the top layer of the epitaxial body, so that the contact area and the adhesiveness between metal and a semiconductor can be improved, and the ohmic contact is good. In conclusion, the P-channel semiconductor device provided by the invention has the advantages of small preparation difficulty and good device performance. The P-channel semiconductor device provided by the invention is described in detail below by means of specific embodiments.
Example 1
Fig. 2 is a schematic structural diagram of a longitudinal section of a P-channel semiconductor device according to a first embodiment of the present invention, fig. 3 is a schematic structural diagram of an a-direction structure of the P-channel semiconductor device shown in fig. 2 (the barrier layer 120 on the side is not shown in order to clearly show the channel layer 110 and the two-dimensional hole gas 130 therein), and fig. 4 is a schematic structural diagram of a B-direction structure of the P-channel semiconductor device shown in fig. 2. The P-channel semiconductor device according to the first embodiment of the present invention includes an epitaxial body 1 and an electrode formed on the epitaxial body 1, wherein the epitaxial body 1 is composed of a channel layer 110 and a barrier layer 120. The channel layer 110 and the barrier layer 120 are each a group III-V compound. For example, the material of the channel layer 110 may be a material capable of providing a crystal orientation of [0001 ]]Or [000-1 ]]Gallium nitride (GaN). The material of the barrier layer 120 is gallium aluminum nitride (AlGaN), indium aluminum nitride (AlInN), gallium indium nitride (InGaN), aluminum nitride (AlN), gallium indium aluminum nitride (AlInGaN), or the like. Channel layer 110 has a first vertical interface with a crystal orientation of [000-1 ]]The barrier layer 120 covers the sides of the channel layer 110, including the first vertical interface. In the first embodiment, the channel layer 110 includes an N-type semiconductor layer 112 and a P-type semiconductor layer 111 from bottom to top, and the first embodiment is formed by A vertical two-dimensional hole gas 130 is generated in the P-type semiconductor layer 111 in the vicinity of the boundary with the barrier layer 120, and the vertical two-dimensional hole gas 130 is depleted in the N-type semiconductor layer 112. Referring to fig. 3 and 4, the epitaxial body 1 is divided into a first epitaxial body 11 and a second epitaxial body 12 which are juxtaposed from the top, and an isolation region 13 for insulating the first epitaxial body 11 and the second epitaxial body 12 is provided in the middle. In the present embodiment, the isolation region 13 is a region obtained by ion implantation, for example, implanted ions are fluorine ions, and the concentration is 2E19cm -3 . The depth of the isolation region 13 is greater than the thickness of the P-type semiconductor layer 111, so that the vertical two-dimensional hole gas 130 in the first epitaxial body 11 is insulated from the vertical two-dimensional hole gas 130 in the second epitaxial body 12. The electrodes in this embodiment comprise a first electrode 21, a second electrode 22 and a third electrode 23, the first electrode 21 being provided on top of said first epitaxial body 11. A second electrode 22 is provided on top of the second epitaxial body 12 and the third electrode 23 is provided directly on the barrier layer 120 laterally of the epitaxial body 1, which is epitaxial from the first vertical interface. The first electrode 21 forms a P-type ohmic contact with the top of the first epitaxial body 11, the second electrode 22 forms a P-type ohmic contact with the top of the second epitaxial body 12, and the third electrode 23 forms a schottky contact with the barrier layer 120. The third electrode 23 covers a partial region of the P-type semiconductor layer 111 in the first epitaxial body 11, a partial region of the P-type semiconductor layer 111 in the second epitaxial body 12, and a partial region of the N-type semiconductor layer 112, respectively.
When no voltage is applied to the third electrode 23, the two-dimensional hole gas 130 is exhausted in the N-type semiconductor layer 112, and thus the first electrode 21 and the second electrode 22 are in an off state, and when a voltage is applied to the third electrode 23, holes are inversely formed in the region of the N-type semiconductor layer 112 corresponding to the third electrode 23, and the two-dimensional hole gas 130 in the first epitaxial body 11 and the two-dimensional hole gas 130 in the second epitaxial body 12 can be electrically connected, thereby conducting the first electrode 21 and the second electrode 22. Namely, the invention realizes the normally-off enhanced semiconductor device, thereby improving the circuit safety during application and saving energy.
Fig. 5 is a flow chart of a method for fabricating a P-channel semiconductor device according to a first embodiment of the present invention. Referring to fig. 2 to 8, the method for manufacturing a P-channel semiconductor device according to the present embodiment includes the following steps:
in step S11, a channel layer 110 is provided, wherein the channel layer 110 includes an N-type semiconductor layer 112 and a P-type semiconductor layer 111 from bottom to top, and the channel layer 110 has a first vertical interface.
In step S12, a barrier layer 120 is epitaxially obtained from the first vertical interface of the channel layer 110. In the vicinity of the boundary between the P-type semiconductor layer 111 and the barrier layer 120, a vertical two-dimensional hole gas 130 is generated, and the vertical two-dimensional hole gas 130 is depleted in the N-type semiconductor layer 112. The channel layer 110 and the barrier layer 120 constitute an epitaxial body 1.
In step S13, the epitaxial body 1 is separated into a first epitaxial body 11 and a second epitaxial body 12 in parallel from the top. Wherein the vertical two-dimensional hole gas 130 in the first epitaxial body 11 is insulated from the vertical two-dimensional hole gas 130 in the second epitaxial body 12.
In step S14, a first electrode 21 is provided on top of the first epitaxial body 11.
In step S15, a second electrode 22 is provided on top of said second epitaxial body 12.
In step S16, a third electrode 23 is directly or indirectly provided on the barrier layer 120 extending from the first vertical interface on the side of the epitaxial body 1, and the third electrode 23 covers a partial region of the first epitaxial body 11, a partial region of the second epitaxial body 12, and a partial region of the N-type semiconductor layer 112, respectively.
In providing the channel layer 110 in step S11, in one embodiment, the substrate 3 is first provided and the substrate 3 is patterned to obtain a substrate step. As shown in fig. 6, fig. 6 is a schematic structural view of a longitudinal section of a substrate 3 according to a first embodiment of the present invention. The substrate 3 includes a first mesa 31 and a second mesa 32 having a height difference, and a substrate step side 33 connecting the first mesa 31 and the second mesa 32 has six-axis symmetry. The substrate 3 in this embodiment may be silicon (Si), blue Gem (Al) 2 O 3 ) When the substrate 3 is GaN, one of materials such as silicon carbide (SiC) and gallium nitride (GaN), the substrate step side surface 33 is a (0001) or (000-1) surface of GaN; when the substrate 3 is Si, the substrate step side 33 is a (111) plane of Si; when the substrate 3 is sapphire, the substrate step side 33 is a (0001) plane of sapphire; when the substrate 3 is SiC, the substrate step side face 33 is a (0001) face or a (000-1) face of SiC.
Referring to fig. 7, fig. 7 is a schematic view of a structure of a longitudinal section of an epitaxial channel layer 110 on a substrate 3 according to an embodiment of the present invention. After patterning the substrate 3, the first mesa 31 and the second mesa 32 are covered with silicon oxide or the like as an epitaxial mask 34. When the substrate 3 is GaN, the lattice of the substrate 3 is matched with the lattice of the channel layer 110 also using GaN, and the channel layer 110 and the barrier layer 120 can be obtained directly by sequentially and epitaxially on the side surface 33 of the substrate step. When the substrate 3 is silicon (Si), a nucleation layer 4 may be deposited from the substrate step side 33 at this time, the nucleation layer 4 may be AlN or GaN, and then the channel layer 110 is epitaxially grown from the nucleation layer 4, because the lattice is greatly different from that of the channel layer 110 using GaN. When the substrate 3 is sapphire (Al 2 O 3 ) Or silicon carbide (SiC), the channel layer 110 using GaN may be directly formed on Al 2 O 3 Or nucleation growth on SiC, it may also be preferable to introduce nucleation layer 4 during the process from the standpoint of crystal quality.
Alternatively, a buffer layer may be grown from the nucleation layer 4, and the buffer layer may have a single layer or multiple layers, and may be one or more of AlN, gaN, alGaN, inGaN, alInN and AlGaInN. The channel layer 110 is then epitaxially grown from the buffer layer. The nucleation layer 4 and/or the buffer layer serve to make the channel layer 110 more crystalline.
In this embodiment, when the channel layer 110 is epitaxially grown, the P-type semiconductor layer 111 and the N-type semiconductor layer 112 are sequentially included from the outer layer to the inner layer. Taking the structure of the figure as an example, the nucleation layer 4 is epitaxially obtained from the substrate step side 33 of the substrate 3, and the nucleation layer 4 may be on part of the side or on all of the side of the substrate step side 33. Then, with the nucleation layer 4 as a core, the N-type semiconductor layer 112 is epitaxially grown outwards and upwards perpendicular to the second mesa 32 under the limitation of the second mesa 32 of the substrate 3, and then the P-type semiconductor layer 111 is epitaxially grown outwards and upwards on the outer surface of the N-type semiconductor layer 112, as shown in fig. 7. Then, the current epitaxial body 1 is processed to remove the wrapping layers of the layers on the side surfaces, and then the channel layer 110 is obtained, wherein the left side surface of the channel layer is [000-1] and is used as a first vertical interface, the right side surface of the channel layer is [0001], and the right side surface of the channel layer is used as a first vertical interface. It will be appreciated that the substrate 3 need not be etched in a stepped manner, for example, nucleation may be performed directly on the upper surface of the substrate 3 to provide the nucleation layer 4 and epitaxially grow the buffer layer and the channel layer 110.
In step S12, referring to fig. 8, fig. 8 is a schematic structural diagram of a longitudinal section after the channel layer 110 and the barrier layer 120 are epitaxially grown on the substrate 3 according to an embodiment of the present invention. The barrier layer 120 is epitaxially formed on the outer surface of the channel layer 110, and at this time, a vertical two-dimensional hole gas 130 is generated in the vicinity of the boundary between the P-type semiconductor layer 111 and the barrier layer 120 on the (000-1) surface of the channel layer 110, and the vertical two-dimensional hole gas 130 is depleted in the N-type semiconductor layer 112. Since the barrier layer 120 wraps around the outer surface of the channel layer 110, in order to grow an electrode on top, in this embodiment, the barrier layer 120 on top is removed, so as to obtain the epitaxial body 1 as shown in fig. 9, and fig. 9 is a schematic view of the structure principle of a longitudinal section of the epitaxial body after removing the barrier layer 120 on top according to the first embodiment of the present invention.
In step S13, an ion implantation process is performed in the middle region, with the top of the epitaxial body 1 down, and the implantation depth is greater than the thickness of the P-type semiconductor layer 111, thereby forming the isolation region 13. Referring to fig. 10 and 11, fig. 10 is a schematic structural view of a longitudinal section in the a direction of the epitaxial body 1 shown in fig. 9 after the ion implantation process (the barrier layer 120 on the side is not shown in order to clearly show the channel layer 110 and the two-dimensional hole gas 130 inside. Fig. 11 is a schematic view of a part of the structure in the B direction (substrate 3 is not shown) of the epitaxial body 1 shown in fig. 9 after the ion implantation process. The isolation region 13 has a first epitaxial body 11 on one side and a second epitaxial body 12 on the other side. Since the depth of the isolation region 13 is greater than the thickness of the P-type semiconductor layer 111, the vertical two-dimensional hole gas 130 in the first epitaxial body 11 is insulated from the vertical two-dimensional hole gas 130 in the second epitaxial body 12.
In step S14, a first electrode 21 of a P-type ohmic contact is provided on top of the first epitaxial body 11, i.e. on top of the P-type semiconductor layer 111.
In step S15, a second electrode 22 of P-type ohmic contact is provided on top of the second epitaxial body 12, i.e. on top of the P-type semiconductor layer 111.
It will be appreciated that the barrier layer 120 on top may not be removed, and that when the first electrode 21 and the second electrode 22 are provided, the region on top where the electrode is provided etches the barrier layer 120 to expose the partial P-type semiconductor layer 111, and then the metal is grown again to obtain the electrode.
In step S16, referring to fig. 12 to 14, fig. 12 is a schematic structural view of a longitudinal section after providing an electrode on the epitaxial body 1 according to the embodiment of the present invention. Fig. 13 is a schematic diagram of the structure principle of the a-direction longitudinal section of fig. 12 (the barrier layer 120 on the side is not shown in order to clearly show the channel layer 110 and the two-dimensional hole gas 130 inside. Fig. 14 is a schematic view of a part of the structure in the B direction of fig. 12. In order to provide the third electrode 23 on the barrier layer 120 extending from the first vertical interface on the side surface of the epitaxial body 1, the dielectric 51 is filled first, the position of the third electrode 23 is defined by the depth of the dielectric 51, then the third electrode 23 is obtained by depositing metal on the surface of the barrier layer 120 on the current side surface and the dielectric 51, and the third electrode 23 is in schottky contact with the barrier layer 120. The third electrode 23 covers a partial region of the first epitaxial body 11, a partial region of the second epitaxial body 12, and a partial region of the N-type semiconductor layer 112, respectively. When no voltage is applied to the third electrode 23, the two-dimensional hole gas 130 is depleted in the N-type semiconductor layer 112, and the two-dimensional hole gas 130 in the first epitaxial body 11 and the two-dimensional hole gas 130 in the second epitaxial body 12 do not contact, so that the first electrode 21 and the second electrode 22 are in an off state. When a voltage is applied to the third electrode 23, holes are inversely formed in the region of the N-type semiconductor layer 112 corresponding to the third electrode 23, and the two-dimensional hole gas 130 in the first epitaxial body 11 and the two-dimensional hole gas 130 in the second epitaxial body 12 can be electrically connected to each other, thereby conducting the first electrode 21 and the second electrode 22.
Example two
Fig. 15 is a schematic diagram of the structure principle of an a-direction longitudinal section of a P-channel semiconductor device according to the second embodiment of the present invention (the barrier layer 120 of the side is not shown in order to clearly show the channel layer 110 and the two-dimensional hole gas 130 therein). Fig. 16 is a schematic diagram showing the structure of the B-direction portion of the P-channel semiconductor device shown in fig. 15. Referring to fig. 15 and 16, the isolation region 13 in this embodiment is a region etched in the middle region of the epitaxial body 1 from top to bottom, and the etching depth is greater than the thickness of the P-type semiconductor layer 111. By etching away the middle region of the epitaxial body 1, the regions on both sides constitute a first epitaxial body 11 and a second epitaxial body 12 side by side.
Example III
Fig. 17 is a schematic view of the structure of a longitudinal section of a P-channel semiconductor device according to the third embodiment of the present invention. Fig. 18 is a schematic diagram of the structure principle of the longitudinal section a in fig. 17 (the barrier layer 120 and the medium 51 on the side are not shown in order to clearly show the channel layer 110 and the two-dimensional hole gas 130 inside. Fig. 19 is a schematic view of a part of the structure in the B direction of fig. 17. Referring to fig. 17 to 19, the channel layer 110 of the P-channel semiconductor device in the present embodiment further includes a third semiconductor layer 113. That is, in the step of providing the channel layer 110 in the flow of the method of manufacturing the P-channel semiconductor device, the third semiconductor layer 113 is first epitaxially grown from the substrate step side 33 of the substrate 3. In this embodiment, when GaN, sapphire or silicon carbide is used as the substrate 3, the buffer layer may be directly extended from the side surface 33 of the substrate step, and is limited by the second mesa 32 of the substrate 3, and extends outwards and upwards perpendicularly to the second mesa 32. The buffer layer is, for example, unintentionally doped GaN, which may be used as the third semiconductor layer 113 in this embodiment. Of course, it is also possible to first epitaxially grow the nucleation layer 4 from the substrate step side 33 (see fig. 12), then to epitaxially grow the third semiconductor layer 113 from the nucleation layer 4, then to epitaxially grow the N-type semiconductor layer 112 outward and upward, and then to epitaxially grow the P-type semiconductor layer 111 further outward and upward on the outer surface of the N-type semiconductor layer 112 as an example. Then, the current epitaxial body is processed to remove the wrapping layers of the lateral layers, and the channel layer 110 is obtained, wherein the right side crystal orientation is [0001], the left side crystal orientation is [000-1], the left side of the crystal orientation is [000-1] is used as a first vertical interface, and then the barrier layer 120 is epitaxially grown on the outer surface of the channel layer 110. At this time, due to the polarization effect between the channel layer 110 and the barrier layer 120, vertical two-dimensional hole gas 130 is generated in both the P-type semiconductor layer 111 and the third semiconductor layer 113 in the channel layer 110, and the two-dimensional hole gas 130 is depleted in the N-type semiconductor layer 112.
Then, the current epitaxial body is etched, and the barrier layer 120 on the top and the middle area on the top are removed, so as to form a first epitaxial body 11 and a second epitaxial body 12.
In the present embodiment, the first and second sub-electrodes 231 and 232 are formed on the barrier layer 120 corresponding to the N-type semiconductor layer 112, corresponding to the first and second epitaxial bodies 11 and 12, respectively. Referring to fig. 18 and 19, the body of the first sub-electrode 231 spans the N-type semiconductor layer 112, the upper end of the first sub-electrode 231 covers a partial region of the P-type semiconductor layer 111 in the first epitaxial body 11, and the lower end of the first sub-electrode 231 covers a partial region of the third semiconductor layer 113. The body of the second sub-electrode 232 spans the N-type semiconductor layer 112, the upper end of the second sub-electrode 232 covers a partial region of the P-type semiconductor layer 111 in the second epitaxial body 12, and the lower end of the second sub-electrode 232 covers a partial region of the third semiconductor layer 113. The electrode formed by the first sub-electrode 231 and the second sub-electrode 232 serves as a gate electrode of the transistor. When no voltage is applied to the gate electrode, the two-dimensional hole gas 130 is depleted in the N-type semiconductor layer 112, and when a voltage is applied to the gate electrode, holes are inversely formed in the region of the N-type semiconductor layer 112 corresponding to the first sub-electrode 231 and the second sub-electrode 232, so that the two-dimensional hole gas 130 in the first epitaxial body 11, the two-dimensional hole gas 130 in the third semiconductor layer 113, and the two-dimensional hole gas 130 in the second epitaxial body 12 can be electrically connected to each other, and the first electrode 21 and the second electrode 22 can be further turned on.
Example IV
Fig. 20 is a schematic diagram of a structure of an a-direction longitudinal section of a P-channel semiconductor device according to the fourth embodiment of the present invention (the barrier layer 120 on the side and the dielectric 51 defining the positions of the first sub-electrode 231 and the second sub-electrode 232 are not shown in order to clearly show the channel layer 110 and the two-dimensional hole gas 130 therein). In this embodiment, the first sub-electrode 231 and the second sub-electrode 232 are electrically connected through the conductive metal 233, and the electrode structure formed at present is used as a gate electrode, so that when a voltage is applied to the gate electrode, the area of the N-type semiconductor layer 112 capable of inverting holes is increased, the current conducting area is increased, and the current conducting rate is improved.
Example five
Fig. 21 is a schematic structural view of a longitudinal section of a P-channel semiconductor device according to a fifth embodiment of the present invention. Fig. 22 is a schematic diagram of the structure principle of the longitudinal section a in fig. 21 (the barrier layer 120 on the side and the medium 51 defining the positions of the first sub-electrode 231 and the second sub-electrode 232 are not shown in order to clearly show the channel layer 110 and the two-dimensional hole gas 130 inside. Fig. 23 is a schematic diagram of a part of the structure in the B direction of fig. 21 (the substrate 3 and the medium 51 are not shown). In this embodiment, after the epitaxial body 1 is obtained, the top barrier layer 120 is not required to be removed, and when the first electrode 21 and the second electrode 22 are manufactured, a part of the barrier layer 120 region is etched on the top layer of the first epitaxial body 11 and the second epitaxial body 12 to expose the P-type semiconductor layer 111 under the barrier layer 120, and the first electrode 21 and the second electrode 22 are manufactured in the etched region. In this embodiment, when the first sub-electrode 231 and the second sub-electrode 232 are prepared, the first sub-electrode 231 and the second sub-electrode 232 start from the position defined by the medium 51, and when the electrode metal is grown, the metal can be extended and grown to the top layers of the first epitaxial body 11 and the second epitaxial body 12, and the resulting structure is shown in fig. 21 to 23.
Example six
Fig. 24 is a schematic structural view of a longitudinal section of a P-channel semiconductor device according to a sixth embodiment of the present invention. Fig. 25 is a schematic diagram of the structure principle of the longitudinal section a in fig. 24 (the barrier layer 120 on the side and the medium 51 defining the positions of the first sub-electrode 231 and the second sub-electrode 232 are not shown in order to clearly show the channel layer 110 and the two-dimensional hole gas 130 inside. Fig. 26 is a schematic diagram of a part of the structure in the B direction of fig. 24 (the substrate 3 and the medium 51 are not shown). In this embodiment, after the epitaxial body 1 is obtained, the first dielectric layer 52 is provided from the barrier layer 120 that is epitaxially grown on the first vertical interface, and the first dielectric layer 52 is epitaxially grown on top of the first epitaxial body 11 and the second epitaxial body 12 and covers the first electrode 21 on top of the first epitaxial body 11 and the second electrode 22 on top of the second epitaxial body 12. Then, according to the positions of the top of the first epitaxial body 11 and the top of the second epitaxial body 12, where the electrode lead-out ends are required to be arranged, holes are respectively formed in the first dielectric layer 52 on the top of the first epitaxial body 11 and the top of the second epitaxial body 12, and the first electrode 21 and the second electrode 22 on the lower layer are exposed. In this embodiment, when the first sub-electrode 231 extends from the side of the epitaxial body 1 to the top of the first epitaxial body 11 and the second sub-electrode 232 extends from the side of the epitaxial body 1 to the top of the second epitaxial body 12, the position where the metal does not need to be grown is blocked by a mask, and the electrode lead-out end region is defined at the position where the electrode lead-out end needs to be provided, so that the sub-electrode and the electrode lead-out end can be obtained simultaneously when the metal is grown. The sub-electrodes in this embodiment extend from the top to opposite sides during growth. Of course, it may extend only to the top of the first epitaxial body 11 and the top of the second epitaxial body 12.
See fig. 24-26. The first sub-electrode 231 extends from the side surface of the epitaxial body 1 to the top and the opposite side surface of the first epitaxial body 11, the lower layer is a first dielectric layer 52, and the first dielectric layer 52 covers the first electrode 21 on the top of the first epitaxial body 11. The first sub-electrode 231 on the top of the first epitaxial body 11 has a first electrode lead-out terminal 212 in a middle region, the first sub-electrode 231 is separated from the first electrode lead-out terminal 212 and is not in contact with the first electrode lead-out terminal 212, and the first electrode lead-out terminal 212 is electrically connected to the first electrode 21 through a first lead-out metal (not shown).
Similarly, a first dielectric layer 52 overlies the second electrode 22 on top of the second epitaxial body 12. The second sub-electrode 232 at the top of the second epitaxial body 12 has a second electrode lead-out 222 in the middle, the second sub-electrode 232 is separated from the second electrode lead-out 222 and is not in contact with the second electrode 22, and the second electrode lead-out 222 is electrically connected to the second electrode 22 through the second lead-out metal 221.
In the process of manufacturing the sub-electrode, the first dielectric layer 52 may be deposited on the entire outer surface of the epitaxial body 1, or the first dielectric layer 52 may be deposited only at the position where the sub-electrode is located. This embodiment employs depositing a first dielectric layer 52 at the location of the sub-electrodes, as shown in fig. 25 and 26.
The P-channel semiconductor device provided by the invention is a vertical device, and solves the problem that the hole integration degree is not high in unit area when a P-channel is adopted in a transverse device, so that hole gas with enough current density can be provided, and the same effect as that of an N-channel device can be achieved; in addition, the invention arranges the electrode on the surface, thereby ensuring the contact yield of the electrode and the semiconductor layer and solving the problem of poor contact of the electrode caused by arranging the electrode on the side surface of the traditional vertical device.
The above embodiments are provided for illustrating the present invention and not for limiting the present invention, and various changes and modifications may be made by one skilled in the relevant art without departing from the scope of the present invention, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.
Claims (17)
1. A P-channel semiconductor device is characterized by comprising an epitaxial body formed by a channel layer and a barrier layer, a first electrode, a second electrode and a third electrode; the barrier layer is obtained by epitaxy from the first vertical interface of the channel layer;
the channel layer comprises an N-type semiconductor layer and a P-type semiconductor layer which are arranged from bottom to top, vertical two-dimensional hole gas is generated in the P-type semiconductor layer near the area which is in boundary with the barrier layer, and the vertical two-dimensional hole gas is exhausted in the N-type semiconductor layer;
The epitaxial body is separated into a first epitaxial body and a second epitaxial body which are positioned at two sides of the isolation region and are parallel through an isolation region with the depth being larger than the thickness of the P-type semiconductor layer and smaller than the overall thickness of the epitaxial body from the top, and vertical two-dimensional hole gas in the first epitaxial body is isolated from vertical two-dimensional hole gas in the second epitaxial body in an insulating manner;
the first electrode is provided on top of the first epitaxial body;
the second electrode is provided on top of the second epitaxial body;
the third electrode is directly or indirectly provided on the barrier layer extending from the first vertical interface on the side surface of the epitaxial body, and covers a partial region of the P-type semiconductor layer in the first epitaxial body, a partial region of the P-type semiconductor layer in the second epitaxial body, and a partial region of the N-type semiconductor layer, respectively, and is capable of electrically connecting the two-dimensional hole gas in the first epitaxial body and the two-dimensional hole gas in the second epitaxial body when a voltage is applied to the third electrode;
wherein the channel layer and the barrier layer are semiconductor layers of III-V compounds, respectively.
2. The P-channel semiconductor device of claim 1, wherein said isolation region is implemented by ion implantation or etching.
3. The P-channel semiconductor device according to claim 1 or 2, wherein a lower layer of the N-type semiconductor layer in the channel layer further comprises a third semiconductor layer which is a semiconductor layer of a group III-V compound, and a vertical two-dimensional hole gas is generated in the third semiconductor layer near an area which interfaces with the barrier layer.
4. The P-channel semiconductor device of claim 3, wherein the third electrode comprises at least a first sub-electrode and a second sub-electrode, the body of the first sub-electrode spans the N-type semiconductor layer, the upper end of the first sub-electrode covers a partial region of the P-type semiconductor layer in the first epitaxial body, and the lower end of the first sub-electrode covers a partial region of the third semiconductor layer; the body of the second sub-electrode spans the N-type semiconductor layer, the upper end of the second sub-electrode covers a partial area of the P-type semiconductor layer in the second epitaxial body, and the lower end of the second sub-electrode covers a partial area of the third semiconductor layer.
5. The P-channel semiconductor device of claim 4, wherein said first sub-electrode and said second sub-electrode are electrically connected by a conductive metal.
6. The P-channel semiconductor device of claim 4, wherein said first sub-electrode extends from said epitaxial body side to a top of said first epitaxial body; and/or the second sub-electrode extends from the epitaxial body side to the top of the second epitaxial body.
7. The P-channel semiconductor device of claim 6, further comprising a first dielectric layer, a first electrode tap and/or a second electrode tap on top of an epitaxial body, said first dielectric layer at least encasing said first electrode on top of said first epitaxial body and/or said second electrode on top of said second epitaxial body, said first electrode under said first sub-electrode being electrically connected to said first electrode tap through a first tap metal over said first dielectric layer when said first sub-electrode extends from said epitaxial body side to top of said first epitaxial body; and the second electrode below the second sub-electrode is electrically connected with the second electrode leading-out end through a second leading-out metal.
8. The P-channel semiconductor device of claim 1, further comprising a substrate comprising a first mesa and a second mesa having a height difference, a substrate step side connecting the first mesa and the second mesa having six-axis symmetry; correspondingly, the channel layer and the barrier layer are sequentially obtained by epitaxy by taking the side surface of the substrate step as an epitaxial surface.
9. The P-channel semiconductor device of claim 8, further comprising a nucleation layer, the channel layer, and the barrier layer being sequentially epitaxially grown with the substrate step side as an epitaxial surface.
10. A method of fabricating a P-channel semiconductor device, comprising:
providing a channel layer, wherein the channel layer comprises an N-type semiconductor layer and a P-type semiconductor layer which are arranged from bottom to top, and the channel layer is provided with a first vertical interface;
a barrier layer is obtained through epitaxy from a first vertical interface of the channel layer, vertical two-dimensional hole gas is generated in the P-type semiconductor layer near the area which is in boundary with the barrier layer, and the vertical two-dimensional hole gas is exhausted in the N-type semiconductor layer; the channel layer and the barrier layer form an epitaxial body;
An isolation region with the depth larger than the thickness of the P-type semiconductor layer and smaller than the whole thickness of the epitaxial body is obtained from the top of the epitaxial body in an ion implantation mode or an etching mode, and a first epitaxial body and a second epitaxial body which are parallel are arranged on two sides of the isolation region, wherein vertical two-dimensional hole gas in the first epitaxial body is isolated from vertical two-dimensional hole gas in the second epitaxial body in an insulating mode;
providing a first electrode on top of the first epitaxial body;
providing a second electrode on top of the second epitaxial body;
providing a third electrode directly or indirectly on the barrier layer extending from the first vertical interface on the side surface of the epitaxial body, wherein the third electrode covers a partial region of the P-type semiconductor layer in the first epitaxial body, a partial region of the P-type semiconductor layer in the second epitaxial body and a partial region of the N-type semiconductor layer respectively, and can electrically connect the two-dimensional hole gas in the first epitaxial body and the two-dimensional hole gas in the second epitaxial body when a voltage is applied to the third electrode;
wherein the channel layer and the barrier layer are semiconductor layers of III-V compounds, respectively.
11. The method according to claim 10, wherein when providing a channel layer, a third semiconductor layer is further provided under the N-type semiconductor layer of the channel layer, the third semiconductor layer being a semiconductor layer of a group III-V compound, and a vertical two-dimensional hole gas is generated in the third semiconductor layer near a region that interfaces with the barrier layer.
12. The method of fabricating a P-channel semiconductor device according to claim 11, wherein the step of providing a third electrode directly or indirectly on the barrier layer laterally of the epitaxial body extending from the first vertical interface further comprises:
providing a first sub-electrode and a second sub-electrode directly or indirectly on the barrier layer extending from the first vertical interface on the side surface of the epitaxial body, wherein the body of the first sub-electrode spans the N-type semiconductor layer, the upper end of the first sub-electrode covers a partial area of the P-type semiconductor layer in the first epitaxial body, and the lower end of the first sub-electrode covers a partial area of the third semiconductor layer; the body of the second sub-electrode spans the N-type semiconductor layer, the upper end of the second sub-electrode covers a partial area of the P-type semiconductor layer in the second epitaxial body, and the lower end of the second sub-electrode covers a partial area of the third semiconductor layer.
13. The method of claim 12, further comprising providing a conductive metal to electrically connect the first sub-electrode and the second sub-electrode when the first sub-electrode and the second sub-electrode are provided directly or indirectly on the barrier layer of the epitaxial body side surface extending from the first vertical interface.
14. The method of manufacturing a P-channel semiconductor device according to claim 12, wherein a first dielectric layer is provided from the barrier layer that is epitaxial from the first vertical interface when a first sub-electrode and a second sub-electrode are provided directly or indirectly on the barrier layer that is epitaxial from the first vertical interface from the epitaxial body side; the first sub-electrode and the second sub-electrode are provided on the first dielectric layer.
15. The method of claim 14, wherein when providing a first dielectric layer from the barrier layer of the first vertical interface epitaxy, the first dielectric layer extends to the top of the first epi body and covers the first electrode on the top of the first epi body;
when the first sub-electrode is provided on the first dielectric layer, the first sub-electrode extends from the side surface of the epitaxial body to the upper part of the first dielectric layer on the top of the first epitaxial body;
the first electrode below the first sub-electrode is led out to the top of the first epitaxial body through a first lead-out metal, a first electrode lead-out end is provided on the top of the first epitaxial body, and the first electrode lead-out end is electrically connected with the first lead-out metal for leading out the first electrode;
And/or
The first dielectric layer extends to the top of the second epitaxial body and covers the second electrode on the top of the second epitaxial body;
when the second sub-electrode is provided on the first dielectric layer, the second sub-electrode extends from the side surface of the epitaxial body to the upper part of the first dielectric layer on the top of the second epitaxial body;
and the second electrode below the second sub-electrode is led out to the top of the second epitaxial body through a second lead-out metal, a second electrode lead-out end is provided at the top of the second epitaxial body, and the second electrode lead-out end is electrically connected with the second lead-out metal for leading out the second electrode.
16. The method for manufacturing a P-channel semiconductor device according to claim 10, further comprising: providing a substrate, wherein the substrate comprises a first table top and a second table top with height difference, and the side surface of a substrate step connecting the first table top and the second table top is provided with six-axis symmetry; correspondingly, the channel layer and the barrier layer are sequentially epitaxial by taking the side surface of the substrate step as an epitaxial surface.
17. The method for manufacturing a P-channel semiconductor device according to claim 16, further comprising, after providing the substrate: and taking the side surface of the substrate step as an epitaxial surface epitaxial nucleation layer, and taking the nucleation layer as a core to sequentially epitaxial the channel layer and the barrier layer.
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| CN103337516A (en) * | 2013-06-07 | 2013-10-02 | 苏州晶湛半导体有限公司 | Enhanced switching device and manufacturing method thereof |
| CN107731913A (en) * | 2017-10-31 | 2018-02-23 | 沈阳工业大学 | The double tunneling transistors of discrete double square grid-control U-shaped raceway groove source and drain and its manufacture method |
| CN113140628A (en) * | 2020-01-17 | 2021-07-20 | 广东致能科技有限公司 | Semiconductor device and manufacturing method thereof |
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