JP2006134935A - Semiconductor apparatus and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce contact resistance without disadvantageous result such as drop of withstand voltage characteristics and increase of leak current at a gate electrode. <P>SOLUTION: The semiconductor apparatus means a nitride semiconductor hetero-junction type field effect transistor where an electron supply layer 2 including a first seed layer of Al<SB>z</SB>Ga<SB>1-z</SB>N (0≤z≤1) is formed on the upper side of a channel layer 1 including the layer of Al<SB>x</SB>In<SB>y</SB>Ca<SB>1-x-y</SB>N (0≤x<1, 0≤y<1), with the channel layer 1 being hetero-jointed to the electron supply layer 2. A gate electrode 4, a source electrode 3, and a drain electrode 5 are arranged on the upper side of the electron supply layer 2. The electron supply layer 2 is n-type, impurity concentration of which is 1E18 cm<SP>-3</SP>or less at the upper side of the electrode 4. The lower sides of the source electrode 3 and drain electrode 5 are n-type where impurity concentration is 1E18 cm<SP>-3</SP>or higher. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device such as a heterojunction field effect transistor using a group III nitride semiconductor and a method for manufacturing the same.

  The group III nitride semiconductor heterojunction field effect transistor is expected to be a device that operates at high frequency and high output because it has the characteristics of high breakdown field strength and high electron mobility. Unlike a conventional GaAs-based semiconductor, a nitride semiconductor forms a two-dimensional electron gas due to strain. Therefore, good transistor characteristics can be obtained even when a non-doped layer (low concentration layer) that does not intentionally introduce impurities into the electron supply layer is used. For example, “Ka band 1.48 W high power AlGaN / GaN heterojunction FET” (Kasahara et al., IEICE Technical Report ED2002-93, pp.81-84 (2002)) (Non-patent Document 1) ).

In addition, JP-A-2004-111910 (Patent Document 1) is cited as a document describing a technique related to a group III nitride semiconductor.
JP 2004-111910 A “Ka band 1.48W high power AlGaN / GaN heterojunction FET”, Kasahara et al., IEICE Technical Report ED2002-93, pp.81-84 (2002)

  As reported in Non-Patent Document 1, in the conventional technique, there is also a non-doped layer as an electron supply layer under the source / drain electrodes. It is difficult to form a source / drain electrode having good ohmic characteristics, that is, low contact resistance, in a non-doped layer having a low impurity concentration. If impurities are introduced into the electron supply layer at a high concentration in order to obtain good ohmic characteristics, a high concentration electron supply layer exists also under the gate electrode, which causes a deterioration in leakage current and breakdown voltage characteristics. As described above, in the conventional technique, since an electron supply layer having a constant impurity concentration exists under both the gate electrode and the source / drain electrodes, it is difficult to achieve both breakdown voltage characteristics and good ohmic characteristics. .

  Accordingly, an object of the present invention is to provide a semiconductor device having a reduced contact resistance and a method for manufacturing the same without causing disadvantageous results such as a decrease in breakdown voltage characteristics and an increase in leakage current in a gate electrode.

In order to achieve the above object, a semiconductor device according to the present invention has an Al _z Ga layer on the upper side of a channel layer including a layer made of Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1). A nitride semiconductor heterojunction field effect in which an electron supply layer including a first type layer made of _1-zN (0 ≦ z ≦ 1) is formed, and the channel layer and the electron supply layer are heterojunctioned In the transistor, a gate electrode, a source electrode, and a drain electrode are arranged on the upper side of the electron supply layer, and the electron supply layer has an impurity concentration of 1E18 cm ⁻³ or less in a lower portion of the gate electrode. It is a type. The lower portion of the source electrode and the drain electrode is an n-type having an impurity concentration higher than 1E18 cm ⁻³ .

According to the present invention, the impurity concentration in the lower region of the gate electrode is a low concentration of 1E18 cm ⁻³ or less, and the impurity concentration in the lower region of the source / drain electrode is a high concentration exceeding 1E18 cm ^−3. It is possible to form a semiconductor device. Therefore, the contact resistance can be lowered while maintaining a high breakdown voltage.

In the description related to the present invention, the notation 1En means 1 × 10 ⁿ . Thus, for example, 1E18 represents 1 × 10 ¹⁸ .

(Embodiment 1)
(Production method)
With reference to FIGS. 1-8, the manufacturing method of the semiconductor device in Embodiment 1 based on this invention is demonstrated. The semiconductor device to be manufactured here is a group III nitride semiconductor heterojunction field effect transistor. First, a substrate 10 made of sapphire, SiC, Si, GaN or the like is prepared. By using MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), etc., as shown in FIG. The electron supply layer 2 stacked on the upper side is produced. However, the channel layer 1 is made of Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1). Electron supply layer 2 is assumed to consist of _{Al z Ga 1-z N (} 0 ≦ z ≦ 1).

The channel layer 1 only needs to have a thickness necessary for electrons to flow. Therefore, the thickness of the channel layer 1 may be 50 to 3000 nm. The impurity concentration of the channel layer 1 does not matter. The electron supply layer 2 has a wider band gap than the channel layer 1. For example, GaN / AlGaN, InGaN / AlGaN, etc. can be considered as a combination of the channel layer 1 and the electron supply layer 2. The thickness of the electron supply layer 2 may be a thickness that does not relax the lattice. That is, it may be 5 to 50 nm. The impurity concentration of the electron supply layer 2 is 1E18 cm ⁻³ or less in order to increase the breakdown voltage of the semiconductor device. Here, the impurity of the electron supply layer 2 is n-type.

FIG. 7 shows the relationship between the impurity concentration obtained from the Poisson equation and the withstand voltage. As the impurity concentration decreases, the depletion layer grows, so that the voltage required to reach the breakdown electric field (this is called “breakdown voltage”) increases. In order to increase the breakdown voltage of the semiconductor device, the breakdown voltage value may be increased. In general, “breakdown voltage” as a parameter refers to a breakdown voltage. It can be seen from the graph of FIG. 7 that the impurity concentration needs to be 1E18 cm ⁻³ or less in order to increase the breakdown voltage to 100 V or more. In addition, even when the impurity is not intentionally introduced into the nitride semiconductor, that is, in the case of non-doping, the impurity enters the semiconductor from the growth furnace or atmospheric gas and becomes n-type. For this reason, the present invention can be applied if the actual impurity concentration is 1E18 cm ⁻³ or less even if non-doped in crystal growth.

  Next, photoengraving is performed on the surface of the electron supply layer 2. By this photoengraving, as shown in FIG. 2, a resist pattern 6 is formed so as to cover a region other than the source / drain electrode region 7 in the surface of the electron supply layer 2. This resist pattern 6 becomes a mask for ion implantation in the next process. The thickness of the resist pattern 6 may be any thickness that prevents ions from reaching the electron supply layer 2. For example, it may be about 1 to 6 μm. A film such as an oxide film may be used as a mask instead of the resist pattern 6 as long as the film can block implanted ions.

  Alternatively, as a modification, after a nitride film or oxide film of about 10 to 100 nm is formed on the upper side of the electron supply layer 2, a resist pattern may be formed on the upper side. At this time, a nitride film, an oxide film, or the like formed as a base of the resist pattern suppresses atoms such as Ga and N constituting the electron supply layer from being blown into the vacuum by ions during ion implantation.

Thereafter, as an implantation process, as shown in FIG. 3, ions 8 subjected to electric field acceleration are irradiated using an ion implantation apparatus. In this way, ion implantation is performed. The ions 8 may be atoms that are n-type impurities. Specifically, Si, Ge, C, Sn, Pb, O, and the like can be considered, but Si or Ge having a shallow impurity level is desirable. Furthermore, the electrical activation of n-type impurities may be promoted by simultaneously implanting p-type impurities such as Mn and Mg. The acceleration energy and implantation concentration of ion implantation may be set so that the impurity concentration in the implanted region of the electron supply layer 2 exceeds 1E18 cm ⁻³ .

As an example, the impurity distribution in the depth direction when the thickness of the electron supply layer 2 made of Al _z Ga _1-z N (0 ≦ z ≦ 1) is 35 nm and the implantation concentration is 1E14 cm ⁻² is performed. The result obtained by Monte Carlo calculation is shown in FIG. From the graph of FIG. 8, it can be seen that even if only a part of the electron supply layer 2 has an impurity concentration of 1E18 cm ⁻³ or more when the acceleration energy is 200 keV or less. By further reducing the acceleration energy, the impurity concentration near the surface increases. It can be seen from the graph of FIG. 8 that the impurity concentration at a position very close to the surface of the electron supply layer 2 is 1E18 cm ⁻³ or more when the acceleration energy is 50 keV or less.

As can be seen from the graph of FIG. 8, when the acceleration energy is 5 keV, even if the injection amount is reduced by two orders of magnitude, a state where a part of the electron supply layer 2 has an impurity concentration of 1E18 cm ⁻³ or more can be obtained. Therefore, the implantation concentration may be 1E12 cm ⁻² which is two orders of magnitude smaller than 1E14 cm ⁻² employed in the experiment of FIG. After all, the implantation step includes the step of implanting Si ions at an implantation concentration of 1E12 cm ⁻² or more so that the impurity concentration becomes 1E18 cm ⁻³ even at least part of the electron supply layer with an acceleration energy of 200 keV or less. It can be said that it is preferable.

The electrons travel on the interface between the electron supply layer 2 and the channel layer 1. In order to reduce the resistance from the source / drain electrodes to this interface, it is desirable to make the total impurity concentration of the electron supply layer 2 higher than 1E18 cm ⁻³ as much as possible. For this purpose, it can be seen from the graph of FIG. 8 that when the implantation concentration is 1E14 cm ⁻² , the acceleration energy is preferably about 10 keV or more and 50 keV or less.

Since the implantation concentration and the surface impurity concentration are proportional, even when the implantation concentration is a value other than 1E14 cm ⁻² listed in the above example, the implantation conditions can be set appropriately using this result.

  Next, the resist pattern 6 is peeled off. As a heat treatment step, heat treatment for activating the implanted ions 8 is performed. As a result of the implantation of ions 8 into the source / drain electrode region 7, a high concentration region 9 exists locally as shown in FIG. The ions 8 included in the high concentration region 9 are activated by the heat treatment process. This heat treatment is performed in order to replace the implanted ions and the crystal constituent atoms, and to recover the damage formed by the ion implantation. For this reason, in the heat treatment step, it is desirable to hold at a temperature of 1100 ° C. or higher for 5 seconds or longer. In order to prevent nitrogen atoms from escaping from the surface, this heat treatment is preferably performed in a gas atmosphere containing nitrogen atoms such as nitrogen gas and ammonia gas. Further, heat treatment may be performed after the surface is covered with a nitride film, an oxide film, aluminum nitride, or the like.

  Next, a resist pattern (not shown) is formed by photolithography. The resist pattern is formed so as to cover other than the source / drain electrode region 7. An ohmic metal film (not shown) is deposited through the resist pattern. As the ohmic metal film, for example, a laminated film of Ti and Al, a laminated film of Ti, Al, Pt, and Au is deposited. The resist pattern is removed, and the source electrode 3 and the drain electrode 5 are formed. This is called “lift-off method”. This state is shown in FIG. A gate electrode 4 is formed by the same method as shown in FIG. Furthermore, you may form another component as needed.

(Action / Effect)
According to the method of manufacturing a semiconductor device in the present embodiment, the impurity concentration in the lower region of the gate electrode 4 is a low concentration of 1E18 cm ⁻³ or less, and in the lower region of the source electrode 3 and the drain electrode 5. It is possible to form a semiconductor device having a high impurity concentration exceeding 1E18 cm ⁻³ . Therefore, the contact resistance can be lowered while maintaining a high breakdown voltage.

Further, the source / drain resistance includes a contact resistance between a metal and a semiconductor and a resistance of the electron supply layer 2 itself. The resistance of the electron supply layer 2 itself is the resistance of the semiconductor from the semiconductor directly under the electrode to the two-dimensional electron gas site. In the present invention, since a region having an impurity concentration higher than 1E18 cm ⁻³ is formed immediately below the source / drain electrodes 3 and 5 by ion implantation, the source / drain resistance can also be reduced.

In the present invention, a region having an impurity concentration higher than 1E18 cm ⁻³ is formed only in a limited region including directly under the source / drain electrodes 3 and 5, and the other portion of the electron supply layer 2 has an impurity concentration. Since it remains at 1E18 cm ⁻³ or less, it is possible to avoid a decrease in breakdown voltage characteristics. In the present invention, it is only necessary that the high concentration region 9 is not under the gate electrode 4, so that the high concentration region 9 protrudes from the lower side of the source electrode 3 or the drain electrode 5 toward the gate electrode 4 side. However, the effect of the present invention can be obtained if the protruding high concentration region 9 does not reach under the gate electrode 4.

  In the present invention, since the high concentration region 9 is formed by ion implantation and heat treatment, there is no step at the boundary between the high concentration region and the low concentration region in the surface shape of the electron supply layer 2. Therefore, this is an advantageous method for forming a fine pattern such as the gate electrode 4. A fine pattern is a pattern of 1 micrometer or less, for example.

(Embodiment 2)
(Constitution)
With reference to FIGS. 1 to 6 again, a semiconductor device according to the second embodiment of the present invention will be described.

  A semiconductor device was actually manufactured and confirmed by the method for manufacturing a semiconductor device described in the first embodiment.

First, an SiC substrate was prepared as the substrate 10. As shown in FIG. 1, a GaN layer having a thickness of 2000 to 3000 nm was formed as the channel layer 1 on the upper surface of the substrate 10, and a non-doped AlGaN layer having a thickness of 20 to 35 nm was formed as the electron supply layer 2 so as to cover the upper side. However, this non-doped AlGaN layer has an Al composition of 0.2 to 0.25. As a result of SIMS analysis, the non-doped AlGaN layer was confirmed to have an impurity concentration of 1E18 cm ⁻³ or less.

A resist pattern 6 was formed as shown in FIG. 2, and as shown in FIG. 3, Si ions were implanted under conditions of 1E14 to 1E15 cm ⁻² and 100 keV as an implantation step. Further, as shown in FIG. 4, with the high concentration region 9 formed, as a heat treatment step, it was held at 1100 to 1200 ° C. for 5 minutes in a nitrogen gas atmosphere. Furthermore, the source electrode 3 and the drain electrode 5 were formed as shown in FIG. A gate electrode 4 was formed as shown in FIG.

As described above, Al _z Ga _1-z N (0 ≦ z ≦ 1) is formed on the upper side of the channel layer 1 including the layer made of Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1). A nitride semiconductor heterojunction field effect transistor in which a channel layer 1 and an electron supply layer 2 are heterojunction formed with an electron supply layer 2 including a first type layer comprising: The gate electrode 4, the source electrode 3, and the drain electrode 5 are arranged on the upper side, and the electron supply layer 2 is n-type with an impurity concentration of 1E18 cm ⁻³ or less in the lower part of the gate electrode 4. A semiconductor device having an n-type impurity concentration higher than 1E18 cm ^{−3 in} the lower part of the electrode 3 and the drain electrode 5 was obtained. This semiconductor device includes a substrate 10 containing SiC, and the channel layer 1 is formed on the upper side of the substrate 10.

(Action / Effect)
In the semiconductor device in the present embodiment, the impurity concentration in the lower region of the gate electrode 4 is a low concentration of 1E18 cm ⁻³ or less, and the impurity concentration in the lower region of the source electrode 3 and the drain electrode 5 is 1E18 cm ^{−. Since the} concentration is higher than ³ , the contact resistance can be lowered while maintaining a high breakdown voltage.

FIG. 9 shows the relationship between the heat treatment temperature and the contact resistance. However, the implanted ions are Si ions, the acceleration energy is 100 keV, and there are two implantation concentrations of 1E14 cm ⁻² and 1E15 cm ⁻² . From the graph of FIG. 9, it can be seen that a low contact resistance can be obtained by setting the heat treatment temperature to 1100 ° C. or higher. It has been found that in order to obtain a lower contact resistance than in the case of no implantation, the concentration near the surface can be increased by increasing the implantation amount to 1E14 cm ⁻² or more. From the graph of FIG. 9, it has been found that when Si ions are implanted at an acceleration energy of 100 keV and an implantation concentration of 1E14 cm ⁻² or more, it is desirable to perform heat treatment at 1100 ° C. or more.

Considering that the acceleration energy is preferably 200 keV or less in order to obtain a portion where the impurity concentration is higher than 1E18 cm ⁻³ as described in the first embodiment, as a result, as an implantation step, Si ions are eventually added to 200 keV or less. It can be said that it is preferable to implant at an implantation concentration of 1E14 cm ⁻² or more with an acceleration energy of 1E14 cm ⁻² .

  Further, FIG. 10 shows the results of examining the relationship between the heat treatment temperature and the gate leakage current (also referred to as “reverse current”). As the heat treatment temperature is increased from 1100 ° C., the value of the gate leakage current gradually increases, and is approximately the same as that in the sample in which ion implantation is not performed when the heat treatment temperature is 1200 ° C. In FIG. 10, a sample with “no ion implantation” is not subjected to heat treatment because no ion implantation is performed. Further, when the heat treatment temperature is higher than 1200 ° C., it is considered that the gate leakage current increases from the value in the sample without ion implantation. In a general amplifier device, the gate leakage current is not a problem, but in a low noise amplifier, the gate leakage current affects the characteristics.

  As described above, the heat treatment temperature is preferably 1100 ° C. or higher in order to increase the concentration in the vicinity of the surface, and the heat treatment temperature is preferably 1200 ° C. or lower in order to reduce the gate leakage current. Taking this into consideration, it can be said that the heat treatment temperature is desirably in the range of 1100 to 1200 ° C.

(Substrate type)
The semiconductor device according to the present embodiment includes a substrate 10 containing SiC and the channel layer 1 is formed on the upper side of the substrate 10. However, the substrate 10 is not limited to one containing SiC but is a substrate containing GaN. There may be. That is, it can be said that the semiconductor device preferably includes the substrate 10 containing SiC or GaN and the channel layer 1 is formed on the upper side of the substrate 10. In addition, as a method for manufacturing a semiconductor device, it is preferable to use a method in which the channel layer 1 is formed on the upper side of the substrate 10 containing SiC or GaN.

  Furthermore, leakage current between source / drain in a heterojunction field effect transistor formed using a sapphire substrate as the substrate 10 and a heterojunction field effect transistor formed using a SiC substrate as the substrate 10 The size was compared. The result is shown in FIG. From the graph of FIG. 11, it can be seen that the leakage current increases when the substrate 10 is a sapphire substrate. This is presumably because the resistance of GaN in the channel layer 1 was deteriorated by the heat treatment due to the fact that the sapphire of the substrate 10 and the GaN of the channel layer 1 had different lattice constants by 14%. On the other hand, since the difference in lattice constant between SiC and GaN is about 3%, when the substrate 10 is a SiC substrate, it is considered that the resistance of GaN did not deteriorate even by heat treatment. From the above experimental results, it is considered desirable to use a SiC substrate, which is a substrate made of a material having a small difference in lattice constant with respect to GaN, as the substrate 10. Furthermore, it is more desirable to use a GaN substrate as the substrate 10 in the sense of reducing the difference in lattice constant. As in the case of the gate leakage current, there is no problem with a general amplifier device. However, when the gate leakage current affects the characteristics, it is desirable to manufacture using a substrate having a lattice constant close to that of GaN. That is, it is preferable to use a substrate made of a material in which the difference in lattice constant from GaN is approximately 5% or less.

(Embodiment 3)
In the first and second embodiments, the example in which the electron supply layer 2 is formed of Al _z Ga _1-z N (0 ≦ z ≦ 1) having an impurity concentration of 1E18 cm ⁻³ or less has been described. Since the present invention is intended to reduce the desired resistance by locally ion-implanting a necessary portion of the layer having an impurity concentration of 1E18 cm ⁻³ or less, the object of application is that the entire electron supply layer 2 has an impurity concentration. not limited to being formed from 1E18 cm ^-3 or less of _{Al z Ga 1-z N (} 0 ≦ z ≦ 1), the present invention if there is 1E18 cm ^-3 or less in the region in a part of the electron supply layer 2 is applied it can.

(Constitution)
With reference to FIG. 12, a semiconductor device according to the third embodiment of the present invention will be described. In this semiconductor device, the electron supply layer 2 includes first seed layers 2a and 2c and a second seed layer 2b. The first type layer 2a, 2c and the second type layer 2b is formed from both _{Al z Ga 1-z N (} 0 ≦ z ≦ 1), the composition is the same. However, the second type layer 2b has the same composition but a different impurity concentration than the first type layers 2a and 2c. The first seed layers 2a and 2c have an impurity concentration of 1E18 cm ⁻³ or less, whereas the second seed layer 2b has an impurity concentration exceeding 1E18 cm ⁻³ .

(Action / Effect)
In the present embodiment, a layer having a low impurity concentration exists as a part of the electron supply layer 2, but since the high concentration region 9 is formed by ion implantation, the source / drain electrodes 3, 5 and The contact resistance with the electron supply layer 2 can be lowered. Furthermore, in the present embodiment, since a layer having a high impurity concentration exists inside the electron supply layer 2, not only the contact resistance between the source / drain electrodes 3 and 5 and the electron supply layer 2 is lowered, but also the electron supply layer The resistance of 2 itself can also be lowered.

As shown in FIG. 13, the present invention is applicable even when the electron supply layer 2 includes the first seed layers 2 a and 2 c and the third seed layer 2 d. The third type layer 2d is made of Al _w Ga _1-w N (0 ≦ w ≦ 1, w ≠ z). That is, the third type layer 2d is in a state in which the composition ratio is different from that of the first type layers 2a and 2c. Even in such a semiconductor device, the effect of the present invention of reducing the contact resistance while maintaining a high breakdown voltage can be enjoyed. The height of the Schottky barrier can be changed freely by changing the Al composition z of the portion of the electron supply layer 2 that is in direct contact with the gate electrode 4, that is, the Al composition z of the first seed layer 2a in the example shown in FIG. . If z> w, the height of the Schottky barrier is increased, and the Schottky characteristics are further improved.

(Embodiment 4)
(Constitution)
With reference to FIG. 14, a semiconductor device according to the fourth embodiment of the present invention will be described. In this semiconductor device, the electron supply layer 2 includes a first seed layer 2 c made of Al _z Ga ₁ -zN (0 ≦ z ≦ 1) having an impurity concentration of 1E18 cm ⁻³ or less and a GaN layer 12. The GaN layer 12 is the uppermost layer of the electron supply layer 2.

(Action / Effect)
In the present embodiment, since the GaN layer 12 is the uppermost layer of the electron supply layer 2, the GaN layer 12 is disposed below the gate electrode 4. Therefore, the Schottky characteristic is further improved. The film thickness of the GaN layer 12 is preferably 1 to 50 nm. The impurity concentration of the GaN layer 12 does not matter.

  In addition, the said embodiment disclosed this time is an illustration in all the points, Comprising: It is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and includes all modifications within the scope and meaning equivalent to the terms of the claims.

It is explanatory drawing of the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 and 2 based on this invention. It is explanatory drawing of the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 and 2 based on this invention. It is explanatory drawing of the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1 and 2 based on this invention. It is explanatory drawing of the 4th process of the manufacturing method of the semiconductor device in Embodiment 1 and 2 based on this invention. It is explanatory drawing of the 5th process of the manufacturing method of the semiconductor device in Embodiment 1 and 2 based on this invention. It is explanatory drawing of the 6th process of the manufacturing method of the semiconductor device in Embodiment 1 and 2 based on this invention. It is a graph which shows the relationship between the impurity concentration calculated | required from the Poisson equation in Embodiment 1 based on this invention, and a proof pressure. It is a graph which shows the result of having calculated | required the impurity distribution of the depth direction by Monte Carlo calculation in Embodiment 1 based on this invention. It is a graph which shows the relationship between heat processing temperature and contact resistance in Embodiment 2 based on this invention. It is a graph which shows the relationship between heat processing temperature and gate leakage current in Embodiment 2 based on this invention. It is the graph which compared the magnitude | size of the leakage current between the source / drain in the heterojunction field effect transistor each formed in the sapphire substrate and SiC substrate in Embodiment 2 based on this invention. It is sectional drawing of the semiconductor device in Embodiment 3 based on this invention. It is sectional drawing of the modification of the semiconductor device in Embodiment 3 based on this invention. It is sectional drawing of the semiconductor device in Embodiment 4 based on this invention.

Explanation of symbols

  1 channel layer, 2 electron supply layer, 2a, 2c first type layer, 2b second type layer, 2d third type layer, 3 source electrode, 4 gate electrode, 5 drain electrode, 6 resist pattern, 7 source / drain electrode Region, 8 ions, 9 high concentration region, 10 substrate, 12 GaN layer.

Claims (8)

A _first layer made of Al _z Ga _1-z N (0 ≦ z ≦ 1) is provided above the channel layer including the layer made of Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1). An electron supply layer including a seed layer is formed, and is a nitride semiconductor heterojunction field effect transistor in which the channel layer and the electron supply layer are heterojunction, the gate electrode on the electron supply layer, A source electrode and a drain electrode are disposed, and the electron supply layer is an n-type having an impurity concentration of 1E18 cm ⁻³ or less in a lower portion of the gate electrode, and is below the source electrode and the drain electrode. A semiconductor device having an n-type impurity concentration higher than 1E18 cm ⁻³ at the side portion.   The semiconductor device according to claim 1, comprising a substrate containing SiC or GaN, wherein the channel layer is formed on an upper side of the substrate.   3. The semiconductor device according to claim 1, wherein the electron supply layer includes a second type layer having the same composition as the first type layer but having a different impurity concentration. 4. The semiconductor device according to claim 1, wherein the electron supply layer includes a third type layer made of Al _w Ga _1-w N (0 ≦ w ≦ 1, w ≠ z). 5.   The semiconductor device according to claim 1, wherein the electron supply layer includes a GaN layer, and the GaN layer is an uppermost layer of the electron supply layers. A layer made of Al _z Ga _1-z N (0 ≦ z ≦ 1) is formed above the channel layer including the layer made of Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1). An implantation step of selectively injecting ions into a partial region as viewed from above the structure in which the electron supply layer is formed and the channel layer and the electron supply layer are heterojunction;
A heat treatment step of heat-treating the structure after the implantation step;
An electrode forming step of forming a source electrode and a drain electrode so as to cover the partial region. The implantation step includes a step of implanting Si ions at an implantation concentration of 1E12 cm ⁻² or more with an acceleration energy of 200 keV or less so that an impurity concentration of 1E18 cm ⁻³ is at least part of the electron supply layer. The method for manufacturing a semiconductor device according to claim 6, comprising a step of maintaining the temperature at 1100 ° C. or higher and 1200 ° C. or lower.   The method for manufacturing a semiconductor device according to claim 6, wherein the channel layer is formed on an upper side of a substrate containing SiC or GaN.

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