JP2002231653A - Method for manufacturing semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of the known fact that, when a heat hysteresis of 800 deg.C or higher is passed through, a resistance value is reduced markedly in association with annealing of ion implantation faults, and hence a high resistance region forming technique having a high heat resistance necessary to microminiaturize, accelerate, enhance the efficiency or highly integrate and integrate with an optical element, using a compound semiconductor containing gallium and nitrogen is obtained. SOLUTION: A method for manufacturing a semiconductor element comprises the steps of ion implanting Zn or C through a photomask in a sapphire (0001) substrate 7, by using a compound semiconductor substrate having an AlN buffer layer 8', an undoped layer 8 and an n-type AlxGa1-xN layer 9 formed by a MOCVD method to form inter-element isolation regions 10, 10', 10". Further, the method further comprises the steps of forming source and drain electrodes 12, 12' and 13, 13', annealing to obtain ohmic low contact resistance, and then forming gate electrodes 11, 11', thereby manufacturing a field effect transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for forming a high-resistance region in a gallium nitride (GaN) -based semiconductor containing gallium and nitrogen as constituent elements. It is.

[0002]

2. Description of the Related Art Gallium nitride (GaN) based semiconductors containing gallium and nitrogen as constituent elements are used not only for short-wavelength light-emitting devices such as blue-violet lasers, but also for electronic devices having high-frequency, high-output performance. Is possible. When miniaturizing, speeding up, or increasing the efficiency of these electronic elements, or when integrating these electronic elements or integrating them with an optical element, the periphery of the element, between adjacent elements, or between the element and the substrate It is necessary to form a high-resistance region and electrically isolate the region. Conventionally, attempts have been made to form these high-resistance regions by ion implantation, but the specific resistance and heat resistance of the formed regions are not sufficient. Or, it has been an obstacle in integration and integration with an optical element.

[0003]

When an element is formed on a semiconductor substrate, processes such as crystal growth, impurity doping, and electrode formation are performed. For this reason, these semiconductor substrates undergo a thermal history at a high temperature. Therefore, the high-resistance region provided for electrically separating the periphery of the element, between adjacent elements, or between the element and the substrate needs to sufficiently withstand the heat history in the device manufacturing process, and depends on the process flow. However, heat resistance of about 700 ° C. to 1100 ° C. is required. Furthermore, in order to cope with the miniaturization of devices, it is necessary to achieve sufficient electrical isolation with a narrow isolation width, and although it depends on the size of the isolation region to be employed, 10 ⁷ Ωcm
As described above, it is desirable that the specific resistance is as high as possible. For example, in an LSI using silicon, an SiO ₂ layer formed by a method such as thermal oxidation is generally used for these purposes, and is used for sub-half-micron device isolation or SOI (Silicon on Insu).
lator) structure is realized.

On the other hand, it is generally known that it is difficult to obtain a high-quality thermal oxide film from a compound semiconductor such as GaN. Therefore, when a high-resistance region is formed in a high-frequency device using a GaN-based semiconductor to perform device isolation, N, He
Techniques for implanting relatively light ions have been attempted. For example, Zolper et al, "Status of implantationd
oping and isolation of III-V nitrides ", ECS Proce
The edings volume 95-21,144 reports the change in sheet resistance associated with heat treatment after ion implantation for N ion implantation.
× 10 ⁶ Ω / □, 6 × 10 ⁹ Ω / □ at 750 ° C, 4 × 10 ^{8 at} 850 ° C
Ω / □, and although the sheet resistance once increases at 750 ° C, it can be as high as 10 ⁵ Ωc in terms of the specific resistance, which is an index of the separation between elements.
In addition to the low m, the resistance already started to drop at 850 ° C, indicating that the characteristics were not sufficient in terms of both the isolation resistance between elements and heat resistance. Also, Binari et. Al, "He and N i
mplant isolation of n-type GaN ", APL 78 (5) 3008
It has been reported that e-ion implantation yields 10 ¹⁰ Ωcm after 800 ° C annealing, but at higher temperatures the resistance decreases. Attempts have also been made to implant ions of O, Cr, Fe, Ti, etc., but after a thermal history of 800 ° C or more, the resistance value will decrease significantly due to annealing of ion implantation defects. It has been known.

For these reasons, an electronic device using a compound semiconductor containing gallium and nitrogen has high heat resistance required for miniaturization, high speed, high efficiency, integration, and integration with an optical device. There has been a demand for a technique for forming a high-resistance region.

[0006]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a high resistance region is formed by implanting ions into a substrate, a thin film, or a laminated structure of a compound semiconductor containing gallium and nitrogen. In this step, the ion species to be implanted is Zn or C.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the specific resistance of the high-resistance region is 10 ⁷ Ωcm.
It is characterized by the above.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the second aspect, wherein the high-resistance region has heat resistance of 700 ° C. or more.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein at least a part of a depth direction distribution of a volume concentration of the ion-implanted impurity is 1 × 10 ¹⁹ cm ^-3 or more. Features.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first, third, or fourth aspect, wherein the ion implantation is performed in a peripheral region of the device formed on the semiconductor substrate or in an inter-device region formed adjacently. Is implanted to form a high-resistance region to perform element isolation.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, the semiconductor element is a field-effect transistor, and the step of forming the same is performed by doping by ion implantation into a source / drain portion. The method includes one or both steps of forming a drain electrode, and forms a high-resistance region before either or both steps.

According to a seventh aspect of the present invention, in the method of forming a high-resistance layer on a semiconductor substrate according to the first, third, or fourth aspect, the semiconductor device is formed in a region deeper than a substrate surface portion on which the element is formed. It has a high resistance layer, and the high resistance layer is formed by ion implantation.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

The semiconductor material and the semiconductor element according to the present invention are compound semiconductors containing gallium and nitrogen, specifically,
Includes GaN and alloy semiconductors such as Al _x Ga _1-x N based on GaN. As GaN and its alloy semiconductors, those obtained by heteroepitaxial growth on a substrate such as sapphire or silicon carbide via a thin buffer layer such as AlN can be used. In this case, AlN, GaN, and G
As heteroepitaxy growth of alloy semiconductors such as Al _x Ga _1-x N based on aN, metal organic chemical vapor deposition (M
OCVD) or molecular beam epitaxy (MBE) can be used. In the MOCVD method, trimethyl aluminum, depending on the composition of the grown layer (TMA), trimethyl gallium (TMG), using the raw material such as ammonia (NH _3), 900 ℃ by known methods to 11
Crystal growth is performed at a temperature of about 00 ° C. In addition, in the MBE method, in addition to a metal source such as aluminum (Al) and gallium (Ga), for nitrogen (N), a method of exciting and supplying NH ₃ gas with an ECR ion source or the like is used, and a known method is used. By 800
Crystal growth is performed at a temperature of about 1000 ° C.

Next, when a high-resistance region is formed by ion implantation of Zn or C, in order to separate the element from the periphery or between the elements by the high-resistance region, a photoresist pattern is formed on the surface of the substrate by a photolithography process. After ion implantation, ion implantation is performed to selectively implant only desired ions into a desired region, and then heat is formed at a temperature of about 700 to 1150 ° C. When a high-resistance layer is formed in a portion deeper than the surface of the substrate, the acceleration voltage is selected so that the implanted ions stay in the substrate with a desired distribution in the depth direction. And then annealing at a temperature of about 850 ° C. to 1150 ° C. to recover crystal defects caused by ion implantation. The substrate obtained in this way can be directly used for device formation, but usually, on these substrates, an alloy semiconductor layer such as GaN or a GaN-based Al _x Ga _1-x N to serve as a device operation layer. Alternatively, a laminated structure composed of these is grown and used by a method such as MOCVD or MBE.

[0016]

1 and 2 show a device structure diagram for explaining a manufacturing process of a semiconductor device according to a first embodiment of the present invention, and show an annealing temperature dependency of a specific resistance obtained by a high resistance layer formed by the manufacturing process. FIGS. 3, 3, 4 and 5 show a second embodiment of the present invention.
Element structure diagram for explaining the manufacturing process of the semiconductor element of
FIGS. 6, 7, and 8 are device structure diagrams for explaining the manufacturing steps of the semiconductor devices according to the third, fourth, and fifth embodiments of the present invention, respectively.

Embodiment 1

As shown in FIG. 1, an AlN buffer (40 nm thick) / undoped GaN (3 μm thick) is formed on a sapphire (0001) substrate 1.
And a n-type GaN layer 3 (Si-doped, carrier concentration 4 × 10 ¹⁸ cm ⁻³ , 0.6 μm thick) formed by MOCVD using Zn and C under the conditions shown in Table 1. , N
Is ion-implanted at each of three energies, and the ion-implanted layer 4 has a peak concentration of about 1.0 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ²⁰ cm ⁻³ over a depth of about 300 nm from the surface. Was formed. Thereafter, in order to evaluate the resistance of the ion-implanted layer 4, Si ions were applied at 15 kV to 2 × 10 ¹⁴ cm ^−2.
Injection was performed to form a thin conductive layer 5 on the very surface of the sample. 1 minute The samples in the N ₂ atmosphere, respectively 700 ° C., 850
Heat treatment was performed at 1000C and 1000C. The sample implanted with Zn ions was also heat-treated at 1150 ° C. After forming concentric Ti / Ni electrodes 6 on these samples, an ultra-thin Si ion implanted layer 5 was formed.
The part exposed on the surface was removed by Ar ion etching to obtain the device structure of FIG.

[0019]

[Table 1]

In this device, the specific resistance of the ion-implanted layer was evaluated by measuring the current-voltage characteristics between the center electrode and the peripheral electrode. At this time, the current is (a)-(c)-in FIG.
Although the current flows through the path (b), the resistances of the paths (b) and (c) were negligible compared to the resistance of the path (a), and the specific resistance of the ion-implanted high-resistance layer below the center electrode could be evaluated. GaN obtained by such a method
The specific resistance of the layer is as shown in FIG.
As shown in the figure, even after annealing at 700 ° C, 850 ° C, 1000 ° C, and 1150 ° C, the temperature was extremely high at 10 ¹⁰ Ωcm or more, and showed extremely high thermal stability, showing no decrease to 1150 ° C. .
When C ions are implanted, the resistivity decreases at 1000 ° C. as shown in FIG. 2 (b), but the resistivity after annealing at 700 ° C. and 850 ° C. 90 inserted
The resistivity after annealing at 0 ° C. was 10 ⁸ Ωcm or more, and it was found that it had heat resistance of 900 ° C. or more. On the other hand, when N ions are implanted, FIG.
As shown in (c), in the range of 700 ° C. to 1000 ° C. annealing, almost no specific resistance of 10 ⁶ Ωcm or less was obtained. In addition, secondary ion mass spectrometry (SIMS)
As a result, the thermal diffusion distance was as small as 10 nm at most even after annealing up to 1150 ° C.

As a result, Zn and C have high specific resistance, and are capable of maintaining the element structure precisely and stably at high temperatures due to their low heat diffusion in addition to their being maintained at high temperatures. It was confirmed that it was suitable as an ionic species for forming the resistance region.

Further, instead of the n-type GaN layer, an n-type Al _x Ga _1-x N layer (x
= 0.3, Si doping, carrier concentration 4 × 10 ¹⁸ cm ^-3 , 0.6μm thickness)
Was formed a similar device structure using, the n-type Al _x Ga
_{Since the 1-x} N layer has a larger energy bandwidth than the n-type GaN layer, the specific resistance tends to be equal or larger.In the sample implanted with Zn ions, 700 ° C., 850 ° C., 1000 ° C., 1150 ℃
When C ions are implanted at 10 ¹⁰ Ωcm or more after annealing, the resistivity decreases at 1000 ° C.
The specific resistance after annealing at 850 ° C. and 850 ° C., and the specific resistance when annealing at 900 ° C. interpolated from these were 10 ⁸
Ωcm or more, and was found to have heat resistance of 900 ° C or more. On the other hand, when N ions are implanted, almost 1
0 ⁷ [Omega] cm or less and a low specific resistance had only.

Embodiment 2

As shown in FIG. 3, on an sapphire (0001) substrate 7, an AlN buffer layer (40 nm thick) 8 'and an undoped GaN layer (3
using a compound semiconductor substrate formed by MOCVD with an 8 μm thick) 8 and an n-type Al _x Ga ₁ -xN layer 9 (x = 0.3, Si-doped, carrier concentration 4 × 10 ¹⁸ cm ⁻³ , 20 nm thick) Zn or C ions are implanted through a photomask, and the device isolation regions 10, 10 ',
10 ″ was formed. The ion implantation of Zn or C is performed at three levels of energy according to the conditions shown in Table 1, and about 3
Approximately 1.0 × 10 ¹⁹ cm ^-3 , to 1.0 × over a depth of 00 nm
A concentration of 10 ²⁰ cm ^-3 was obtained. Furthermore, the source / drain electrodes Ti
/ Al / Ni / Au to form 12,12 'and 13,13', respectively, to obtain ohmic low contact resistance
After annealing in a nitrogen atmosphere for 5 minutes, the gate electrode Ni
/ Au11, 11 'was formed to produce a field effect transistor. In the plan view shown in the upper part of FIG. 3, the dimensions of the isolation region are I = 10 μm, W = 15
0 nm, and the dimensions of the source and drain electrodes are both
M = 20 μm, V = 100 μm, and the distance L between these electrodes L = 3
μm.

In this device structure, when the withstand voltage between the source 13 and the drain 12 ′ of two adjacent transistors was measured, the leakage current was 10 μA or less when 10 V was applied, and the non-linear current increased significantly up to 50 V. No high isolation performance was obtained, for example. In the above-mentioned field-effect transistor, high element-separation performance is obtained despite the fact that 850 ° C. annealing is performed to form source / drain electrodes and obtain ohmic low contact resistance after the element-separation ion implantation. It was confirmed that it was maintained.

As a comparison of element arrangement patterns, FIG. 4 shows that source and drain electrodes are formed first, annealing is performed to obtain low ohmic contact resistance, and then these ions are implanted into the gap between the electrodes. The case where separation is performed is shown. In this case, the heat resistance of the element isolation region may be low, but since the width I of the ion implantation region and the distance M between the source and drain electrodes have the same dimensions, the element size may be larger than that of FIG. This is inevitable and disadvantageous for miniaturizing the device. That is, by forming the element isolation region having high heat resistance before forming the electrodes as shown in FIG. 3, the element can be reduced in size.

In the device structure shown in FIGS. 3 and 4, the leak current flowing between the source electrode 12 ′ and the drain electrode 13 of two adjacent transistors flows through the path 14. In FIG. 5, the structure of the crystal growth layer is changed to an AlN buffer layer (40 nm thick) 8 ′ /
p-doped GaN layer 8 ″ (Mg-doped, carrier concentration 1 × 10 ¹⁷ cm)
⁻³ , 2.8 μm thickness) / undoped GaN layer 8 (0.1 μm thickness) / n-type Al _x Ga
The structure was changed to a _1-x N layer 9 (20 nm thick). Thus, p / i / n
Alternatively, the leak current could be reduced to about 1 nA by using a rectifying structure such as a p / n junction.

Embodiment 3

As shown in FIG. 6, on a sapphire (0001) substrate 7, an AlN buffer layer (40 nm thick) 15 'and an undoped GaN layer
(3 μm thickness) 15 and an n-type Al _x Ga ₁ -xN layer 16 (x = 0.3, Si doping, carrier concentration 4 × 10 ¹⁸ cm ⁻³ , 20 nm thickness) formed on a compound semiconductor substrate formed by MOCVD. Zn ions were implanted through a photomask into the device isolation regions 17,
17 ′ and 17 ″ were formed. Zn ion implantation is performed at three levels of energy under the conditions shown in Table 1, and approximately 300 times from the surface.
Approximately 1.0 × 10 ¹⁹ cm ^{−3 to} 1.0 × 10 over the depth of nm
A concentration of ²⁰ cm ^-3 was obtained. Then, first, the gate electrode Ni / Au2
0,20 ', and then the source / drain regions 18,
In order to reduce the parasitic resistance of 18 'and 19, 19',
Using the gate electrode pattern as a mask, Si ions were implanted in a self-aligned manner into these regions and the device isolation regions. The ion implantation conditions at this time are: acceleration voltage 30 kV, implantation amount:
5 is a × 10 ¹³ cm ^-2, 1100 ℃ in a nitrogen atmosphere in order to activate the Si after implantation, heat treatment was performed for one minute. After that, source / drain electrodes Ti / Al Ni / Au were 21 and 2 respectively.
1 ′ and 22, 22 ′ were formed to produce a field effect transistor. The dimensions of the element isolation portion were I = 10 μm, W = 150 nm, the dimensions of the source and drain electrodes were M = 20 μm, V = 100 μm, and the distance L = It was 3 μm.

In the present device structure, the breakdown voltage between adjacent transistors was measured.
Good isolation performance was obtained, including a small value of less than μA and no remarkable non-linear current increase up to 50V. In the above-mentioned field effect transistor, high element isolation performance was obtained despite heat treatment at 1100 ° C. for 1 minute after Si ions to the source and drain.

Embodiment 4

As shown in FIG. 7A, the SiC (0001) substrate 23
An AlN buffer layer (40 nm thick) 24 ′ and an undoped GaN layer (3
μm) 24 using a compound semiconductor substrate formed by the MOCVD method, Zn ions were implanted at three stages of energy under the conditions shown in Table 1 and approximately 1.0 × 10 ¹⁹ cm ^-3 , through a depth of about 300 nm from the surface. A Zn ion implanted layer 25 having a concentration of 1.0 × 10 ²⁰ cm ⁻³ was formed. After heat treatment at 1150 ° C. for 1 minute in a nitrogen atmosphere to recover the crystallinity of the ion-implanted layer, an n-type GaN layer (Si-doped, carrier concentration: 4 × 10 ¹⁸ cm ⁻³ ) 26 μm thick by MOCVD 26 Was formed by crystal growth at 1000 ° C. for 1 minute. Thereafter, as shown in FIG. 7 (b), Ti / Al / Ni /
An Au electrode 27 is formed, and the electrode pattern is used as a mask.
The Si-doped layers were removed by etching by Ar ion sputtering and separated from each other. In this device structure, the source and drain electrodes and the n-type G formed
The dimensions of the aN region were M = 20 μm and W = 100 μm. The distance between these electrodes was equal to the separation width of the adjacent n-type GaN layer, and L = I = 3 μm.

In this device structure, when the separation resistance between the adjacent n-type GaN regions was measured by measuring the current and voltage between the adjacent electrodes, a value of 10 ⁹ Ω was obtained. Despite the fact that the n-type GaN layer had undergone a thermal history of 1000 ° C. to grow, a high separation resistance was obtained. On the other hand, when the Zn ion implantation was not performed, the separation resistance was as low as 10 ⁴ Ω or less.

Embodiment 5

As shown in FIG. 8A, the SiC (0001) substrate 28
An AlN buffer layer (40 nm thick) 29 ′ and an undoped GaN layer (3
Using a compound semiconductor substrate formed by MOCVD method 29, C ions were implanted at three stages of energy under the conditions shown in Table 1 and approximately 300 nm deep from the surface.
A C ion implanted layer 30 having a concentration of 1.0 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ²⁰ cm ⁻³ was formed, and then heat treatment was performed at 900 ° C. for 1 minute in a nitrogen atmosphere to recover crystallinity. . Next, an n-type GaN layer 31 (Si-doped, carrier concentration: 4 × 10 ¹⁸ cm ⁻³ ) having a thickness of 0.1 μm was formed by MBE at a growth temperature of 850 ° C. for 15 minutes. Further, a resist pattern is formed by a photolithography process, and using this as a mask, C ions are implanted at three levels of energy under the conditions shown in Table 1,
By annealing in nitrogen at 900 ° C for 1 minute,
An element isolation region 33 was formed as shown in FIG. Thereafter, a Ti / Al / Ni / Au electrode 32 was formed. The dimensions of the ion implantation region were N = 20 μm, W = 100 μm, and the distance between adjacent ion implantation regions was I = 10 μm. The electrodes were formed so as to satisfy the relationship of N> M and W> V so as to be within the ion implantation regions.

In this device structure, when the separation resistance between the adjacent n-type GaN layers was measured by measuring the current and voltage between the electrodes, a value of 10 ⁷ Ω was obtained. High separation resistance was obtained despite the process of growing n-type GaN layer at 850 ° C for 15 minutes. On the other hand, when C ion implantation was not performed, the separation resistance was as low as 10 ⁴ Ω or less.

[0037]

The technique for forming a high-resistance region on a GaN-based compound substrate according to the present invention has a very high specific resistance.
The separation width for obtaining the same separation resistance can be reduced. Further, since the specific resistance is maintained up to a high temperature, an element isolation step can be performed prior to steps such as electrode formation and doping into the source / drain. Further, since the heat diffusion is extremely small, the element can be formed while maintaining the dimensional accuracy. For these reasons, miniaturization, integration,
It is a very high-resistance region formation technology that is required for miniaturization, integration, or integration of GaN-based semiconductor electronic devices with optical devices, such as the flexible configuration of the device formation process and the simplification of the process. Great effect.

[Brief description of the drawings]

FIG. 1 is an element structure diagram showing a manufacturing process of a semiconductor element of Example 1 of the present invention.

FIG. 2 is a diagram showing the annealing temperature dependence of the specific resistance of a high-resistance layer in the semiconductor device of Example 1 of the present invention.

FIG. 3 is an element structure diagram showing a manufacturing process of a first semiconductor element in Example 2 of the present invention.

FIG. 4 is an element structure diagram showing a manufacturing process of a second semiconductor element in Example 2 of the present invention.

FIG. 5 is an element structure diagram showing a manufacturing process of a third semiconductor element in Example 2 of the present invention.

FIG. 6 is an element structure diagram showing a manufacturing step of the semiconductor element of Example 3 of the present invention.

FIG. 7 is an element structure diagram showing a manufacturing process of a semiconductor element of Example 4 of the present invention.

FIG. 8 is an element structural view showing a manufacturing step of a semiconductor element of Example 5 of the present invention.

[Sign sharp] 1,7 Sapphire substrate 23,28 SiC substrate 2 AlN buffer / undoped Ga
N laminated structure 3, 26 n-type GaN layer (MOCVD layer) 31 n-type GaN layer (MBE layer) 4 Zn, C, or N ion implantation layer 25 Zn ion implantation layer 30 C ion implantation layer 5 Si ion implantation layer 6, 27,32 Ti / Al / Ni / Au electrode 8,15,24,29 Undoped GaN layer 8 ', 15', 24 ', 29' AlN buffer 8 "p-type GaN layer 9,16 n-type Al _x Ga _{1 -x} N layer 10,10 ′, 10 ″, 17,17 ′, 17 ″, 33
Element isolation region 11,11 ', 20,20' Gate electrode 12,12 ', 21,21' Source electrode 13,13 ', 22,22' Drain electrode 18,18 'n-type source region 19,19' n Drain region

Claims (7)

[Claims] In a step of forming a high-resistance region by implanting ions into a substrate, a thin film, or a laminated structure of a compound semiconductor containing gallium and nitrogen, an ion species to be implanted is Zn or C. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the high-resistance region has a specific resistance of 10 ⁷ Ωcm or more. 3. The method according to claim 2, wherein the high-resistance region has a heat resistance of 700 ° C. or higher. 4. The method according to claim 1, wherein at least a part of the depth distribution of the volume concentration of the ion-implanted impurity is 1 × 10 ¹⁹ cm ⁻³ or more. 5. A device according to claim 1, wherein ions are implanted into a peripheral region of the device formed on the semiconductor substrate or an inter-device region formed adjacently to form a high-resistance region to perform device isolation. Item 5. The method for manufacturing a semiconductor device according to item 1, 3, or 4. 6. The semiconductor device is a field-effect transistor, and the step of forming the transistor includes one or both of doping by ion implantation into a source / drain portion and formation of a source / drain electrode. 6. The method according to claim 5, wherein a high-resistance region is formed before the two steps. 7. A step of forming a high-resistance layer on a semiconductor substrate, wherein the high-resistance layer is formed in a region deeper than a substrate surface portion on which elements are formed, and the high-resistance layer is formed by ion implantation. The method for manufacturing a semiconductor device according to claim 1, 3, or 4.