WO2019151277A1

WO2019151277A1 - Semiconductor device and method for manufacturing semiconductor device

Info

Publication number: WO2019151277A1
Application number: PCT/JP2019/003060
Authority: WO
Inventors: 大悟菊田; 渡辺　行彦; 朋彦森; 真一星; 泳信陰; 謙佑畑; 松木　英夫; 大佑栗田
Original assignee: 株式会社デンソー
Priority date: 2018-01-31
Filing date: 2019-01-30
Publication date: 2019-08-08

Abstract

This semiconductor device comprises: a first film (32a, 132a) laminated over a nitride semiconductor; a second film (32b, 132b) laminated over the first film; a third film (32c, 132c) laminated over the second film; and a gate electrode (34, 134) laminated over the third film. The first film, the second film, the third film and the gate electrode constitute an insulated gate structure. The interface trap formed in the interface between the first film and the nitride semiconductor is small. The second film is a polycrystal, having a resistance of 1 × 10⁹ (Ωcm) or greater. The third film is an insulator having a breakdown field strength of 6 (MV/cm) or greater.

Description

Semiconductor device and manufacturing method of semiconductor device

Cross-reference of related applications

This application is based on Japanese Patent Application No. 2018-15538 filed on Jan. 31, 2018 and Japanese Patent Application No. 2019-12930 filed on Jan. 29, 2019. Incorporate content.

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Patent Document 1 discloses an insulated gate structure including a three-layer gate insulating film on a nitride semiconductor. The gate insulating film is, in order from the bottom, a silicon oxide film (first film), an aluminum-rich amorphous aluminum oxide (second film), and a silicon oxide film (third film).

In the technique of Patent Document 1, the film structure of the second film is amorphous. Amorphous has a chemical composition that deviates from the stoichiometric composition as compared to a crystal, and therefore has more defects and impurities in the film than the crystal. As a result of defects and impurities causing fluctuations in the amount of charge in the film, the controllability and reproducibility of the gate threshold voltage are degraded.

JP 2016-66641 A

This disclosure is intended to provide a highly reliable semiconductor device.

In accordance with an aspect of the present disclosure, a semiconductor device includes a first film stacked on a nitride semiconductor, a second film stacked on the first film, and a second film stacked on the second film. A third film and a gate electrode stacked on the third film. An insulated gate structure is formed by the first film, the second film, the third film, and the gate electrode. The first film is a film having few interface traps formed at the interface with the nitride semiconductor. The second film is a polycrystalline body and has a resistance value of 1 × 10 ⁹ (Ωcm) or more. The third film is an insulator having a breakdown electric field strength of 6 (MV / cm) or more.

In the above semiconductor device, the film structure of the second film is a polycrystalline body. Therefore, defects and impurities in the film can be reduced as compared with amorphous. As a result of suppressing the fluctuation of the charge amount in the film, the controllability and reproducibility of the gate threshold voltage can be improved.

According to another aspect of the present disclosure, a method for manufacturing a semiconductor device includes: forming a first film on a surface of a nitride semiconductor with few interface traps that can form an interface with the nitride semiconductor; Forming a second film having a resistance value of 1 × 10 ⁹ (Ωcm) or more on the surface, heat-treating the film at a temperature of 800 ° C. or more, and polycrystallizing the second film; Forming a third film as an insulator having a breakdown electric field strength of 6 (MV / cm) or more on the surface of the second film, and forming a gate electrode on the surface of the third film. Prepare.

In the semiconductor device manufacturing method, the film structure of the second film is a polycrystalline body. Therefore, defects and impurities in the film can be reduced as compared with amorphous. As a result of suppressing the fluctuation of the charge amount in the film, the controllability and reproducibility of the gate threshold voltage can be improved.

The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
The principal part sectional drawing of the semiconductor device of Example 1 is shown typically, It is a correlation diagram of on time and gate threshold voltage, It is a correlation diagram of the gate threshold voltage and the film thickness of the first film, It is a flowchart which shows the manufacturing method of the semiconductor device of Example 1, It is a figure which shows the manufacturing process of the semiconductor device of Example 1, It is a figure which shows the manufacturing process of the semiconductor device of Example 1, It is a figure which shows the equivalent circuit of the semiconductor device of Example 1, It is a figure which shows the comparative example of the semiconductor device of Example 1, The principal part sectional drawing of the semiconductor device of Example 2 is shown typically, It is a comparison figure of the amount of interface traps of aluminum oxide and silicon oxide.

(Structure of the semiconductor device 1)
As shown in the cross-sectional view of the main part in FIG. 1, the semiconductor device 1 is a vertical MOSFET. The semiconductor device 1 is a trench gate type. The semiconductor device 1 has a structure in which a drain electrode 22, an n ⁺ -type drain region 11, an n − -type drift region 12, and a p-type body region 13 are stacked. The drain region 11 is a GaN substrate. The drift region 12 is an epitaxially grown layer of GaN and has a Si concentration of 1 × 10 ¹⁶ cm ⁻³ . The body region 13 is a GaN epi-growth layer and has an Mg concentration of 1 × 10 ¹⁷ cm ⁻³ . An n ⁺ type source region 15 is formed on a part of the surface of the body region 13. The source region 15 is a region formed by implanting Si ions.

In the surface layer portion of the semiconductor device 1, a trench-type insulated gate portion 30 is formed. The insulated gate part 30 is provided in the trench 30T. The trench 30T passes through the insulating layer 16, the source region 15, and the body region 13 of the silicon oxide film and reaches a part of the drift region 12. The insulated gate unit 30 includes a gate insulating film 32 and a gate electrode 34.

The gate insulating film 32 has a structure in which the second film 32b is stacked above the first film 32a and the third film 32c is stacked above the second film 32b in the trench 30T. That is, the insulated gate portion 30 has a structure in which the first film 32a, the second film 32b, the third film 32c, and the gate electrode 34 are laminated in this order on the GaN surface such as the drift region 12 and the body region 13. Yes.

The first film 32a is a film with few interface traps (also referred to as interface states) formed at the interface between the first film 32a and GaN. Here, “there are few interface traps” means that the density of interface traps formed at the interface between the first film 32a and GaN is lower than the density of interface traps formed at the interface between aluminum oxide and GaN. Meaning. Examples of the first film 32a having such characteristics include a silicon oxide film, a silicon nitride film, a gallium oxide film, a laminated film of a gallium oxide film and a silicon oxide film, an aluminum oxynitride, and a silicon nitride film. Here, the gallium oxide film in the “laminated film of gallium oxide film and silicon oxide film” is a reaction layer generated at the interface between the silicon oxide film and GaN when the first film 32a is a silicon oxide film. There may be. In the present embodiment, the first film 32a is a silicon oxide film. The thickness of the first film 32a is 4 nm or less.

The second film 32b is a polycrystal and is a film having a resistance value of 1 × 10 ⁹ (Ωcm) or more. If the resistance value is 1 × 10 ⁹ (Ωcm) or more, the leakage current flowing through the gate insulating film 32 can be prevented. In other words, the second film 32b is a material having a crystal structure and a large band gap energy. Examples of such materials include aluminum oxide (Al ₂ O ₃ ), diamond, AlN, HfO ₂ , GaO, and the like. In the present embodiment, the second film 32b is aluminum oxide.

The third film 32c is an insulator having a breakdown electric field strength of 6 (MV / cm) or more. Examples of the third film 32c having such characteristics include a silicon oxide film and a silicon nitride film. In the present embodiment, the third film 32c is a silicon oxide film.

A source electrode 24 is disposed on a part of the surface of the source region 15. The source electrode 24 and the gate electrode 34 are insulated by the insulating layer 17. The gate electrode 34 is polysilicon doped with boron. The insulating layer 17 is a silicon oxide film. Al wiring 25 is disposed on the surfaces of the gate electrode 34 and the source electrode 24.

A channel is formed in a region in the body region 13 and in the vicinity of the interface between the body region 13 and the gate insulating film 32. When a positive voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 34, an inversion layer is formed in the channel, and the source electrode 24 and the drain electrode 22 become conductive. Therefore, the semiconductor device 1 is turned on.
(Effect of the second film 32b)
In Patent Document 1 described above, amorphous aluminum oxide is used for the intermediate layer of the gate insulating layer. Since the chemical composition of amorphous aluminum oxide deviates from the stoichiometric composition, there are more defects and impurities in the film than in the crystal. Therefore, an energy level (also referred to as a defect level or an impurity level) in which carriers are trapped is formed. When holes are trapped at a level, the trapped state of holes may be maintained even in a depletion state or an inversion state (also referred to as a positive fixed charge). That is, the amount of charge in the film varies. As a result, the depletion layer fluctuates or the charge amount of the inversion layer fluctuates to cancel the influence of the charge amount in the film. That is, the gate threshold voltage is lowered and the threshold reproducibility is lowered. On the other hand, the second film 32b of the present embodiment is polycrystalline aluminum oxide. Polycrystalline can bring the chemical composition closer to the stoichiometric composition compared to amorphous, so that defects and impurities in the film can be reduced compared to amorphous. Therefore, fluctuations in the charge amount in the film can be suppressed, so that the gate threshold voltage can be increased and the reproducibility of the threshold can be improved.

The second film 32b of this example is crystallized aluminum oxide. Aluminum oxide can increase the dielectric constant by being crystallized. When the dielectric constant is large, the gate drive capability can be increased, and thus the channel resistance can be reduced. In addition, since the dielectric constant of the gate insulating film increases, the effective electric field strength in the gate insulating film can be lowered, and the breakdown voltage of the gate insulating film can be improved.
(Effect of the first film 32a)
The interface state density at the interface between aluminum oxide and GaN is higher than the interface state density at the interface between silicon oxide and GaN. As the interface state density increases, carriers are easily trapped. Therefore, for example, when the second film 32b (aluminum oxide) is formed directly on the GaN surface, the gate threshold voltage fluctuates with respect to the on-time as shown in the graph G1 of FIG. Therefore, in the semiconductor device 1 of the present embodiment, the second film 32b is formed on the GaN surface via the first film 32a (silicon oxide). As a result, the interface state density in the vicinity of the GaN surface can be reduced, and as shown in the graph G2 of FIG.

In addition, when high-temperature heat treatment at 850 ^° C. or more is performed in a state where GaN and silicon oxide are in contact with each other, the gate threshold voltage decreases due to diffusion of Ga into the silicon oxide film. In the same manner as described above, by using aluminum oxynitride having a low interface state density, Ga diffusion can be suppressed, so that a reduction in gate threshold voltage can be suppressed.

FIG. 10 shows a comparison of the amount of interface trap at a position of 0.1 eV from the conduction band when the second film 32b (aluminum oxide) and the first film 32a (silicon oxide) are formed on GaN. When the second film 32b (aluminum oxide) is directly formed on the GaN surface, the interface trap amount becomes larger than 3.5 × 10 ¹² cm ⁻² eV ⁻¹ as shown in the graph G1 of FIG. On the other hand, when the first film 32a (silicon oxide) is formed on the GaN surface as in the semiconductor device 1 of the present embodiment, the interface trap amount is 0.9 × 10 as shown in the graph G2 of FIG. It can be seen that the voltage can be reduced to about ¹² cm ⁻² eV ⁻¹ . In other words, by forming aluminum oxide on the GaN surface via silicon oxide, the amount of interface traps in the vicinity of the GaN surface can be reduced to 3.5 × 10 12 cm ⁻² eV ⁻¹ or less.

FIG. 3 shows the correlation between the gate threshold voltage and the film thickness of the first film 32a, which is a silicon oxide film. As shown in FIG. 3, the gate threshold voltage is proportional to the thickness of the first film 32a. That is, the thinner the first film 32a, the higher the gate threshold voltage. This is due to the following reason. When the first film 32a of the silicon oxide film is formed on GaN, a positive fixed charge of 2.5 × 10 ¹² cm ⁻² is generated at the interface due to the interface reaction. This positive fixed charge lowers the gate threshold voltage. On the other hand, the thinner the first film 32a, the more the influence of the positive fixed charge amount in the film can be suppressed. Here, consider a case where the semiconductor device 1 is mounted on an in-vehicle device. In-vehicle devices generally require a gate threshold voltage of 1 V or higher. Then, as shown in FIG. 3, it is understood that the thickness of the first film 32a is preferably 4 nm or less.
(Effect of the third film 32c)
The second film 32b of this example is crystallized aluminum oxide. The crystallized aluminum oxide film has a lower dielectric breakdown voltage than the amorphous aluminum oxide film. This is considered because the crystal grain boundary of the crystallized aluminum oxide functions as a conductive path. Therefore, in the semiconductor device 1 of the present embodiment, the third film 32c of silicon oxide is disposed between the second film 32b and the gate electrode 34. Thereby, it becomes possible to maintain a dielectric breakdown voltage.
(Manufacturing method of the semiconductor device 1)
A method for manufacturing the semiconductor device 1 will be described with reference to FIGS. In step S1 of the flowchart of FIG. 4, a source region forming step is performed. Specifically, a substrate on which the drain region 11, the drift region 12, and the body region 13 are stacked is prepared.

A mask in which the source region 15 is opened is processed using a well-known photolithography technique and dry etching. By implanting Si ions through the mask, an n ⁺ type source region 15 is formed.

In step S2, an insulating layer 16 of about 200 nm is formed on the surface of the source region 15 and the body region 13. A trench 30T that penetrates the insulating layer 16, the source region 15, and the body region 13 and reaches the drift region 12 is processed by a known photolithography technique and dry etching. Thereby, the structure shown in FIG. 5 is formed.

In step S3, a first film 32a (silicon oxide film) is formed in the trench 30T and on the surface of the insulating layer 16. The first film 32a is formed by LP-CVD (low pressure CVD) or PE-CVD (plasma-enhanced CVD). In the LP-CVD method, for example, a film is formed in the vicinity of 800 ^° C. using SiH 4 and N 2 O source gases. In the PE-CVD method, for example, the film is formed at around 400 ^° C. using TEOS (tetraethoxysilane) source gas and O 2 plasma.

When aluminum oxynitride is formed as the first film 32a, aluminum nitride and aluminum oxide are alternately formed by ALD (Atomic Layer Deposition). For example, NH ₃ as a nitrogen source of aluminum nitride, as the aluminum source TMA (Trimethylaluminum), as the oxygen source of the aluminum oxide _{H 2} 0 or _{O 3,} 400 ~ 500 by using TMA as the aluminum source ^o C The film is formed.

In step S4, a second film 32b having a resistance value of 1 × 10 ⁹ (Ωcm) or more is formed on the surface of the first film 32a. In the present embodiment, the second film 32b is amorphous aluminum oxide. Aluminum oxide can be formed using an ALD (Atomic Layer Deposition) method. TMA (Trimethylaluminum) can be used as the source gas. A film can be formed in the vicinity of 300 ^° C. using any of O ₂ plasma, H ₂ O, and O ₃ .

In step S5, heat treatment is performed at a temperature of 800 ^° C. or higher in nitrogen. Preferably, the heat treatment is performed at a temperature of 950 ^° C. or higher. Thereby, the amorphous second film 32b can be polycrystallized.

In step S6, a third film 32c (silicon oxide film) which is an insulator having a breakdown electric field strength of 6 (MV / cm) or more is formed on the surface of the polycrystalline second film 32b. Thereby, the structure shown in FIG. 6 is formed.

That is, the heat treatment step (step S5) is performed between the step of forming the second film 32b (step S4) and the step of forming the third film 32c (step S6). Thereby, since the heat treatment can be performed in a state where the second film 32b is exposed, the crystallization of the second film 32b can be promoted.

In step S7, the gate electrode 34 is formed on the surface of the third film 32c. Specifically, polysilicon doped with boron is formed by LP-CVD. The film thickness of the polysilicon may be such that the trench 30T is sufficiently filled. In order to activate boron, a heat treatment of 900 ^° C. or more may be performed in nitrogen. The polysilicon around the trench 30T is removed using a well-known photolithography technique and dry etching. Thereby, the structure shown in FIG. 7 is formed.

In step S8, the source electrode 24 is formed. Specifically, the insulating layer 16 and the gate insulating film 32 in the region where the source electrode 24 is to be formed are removed using a well-known photolithography technique and dry etching. Next, a laminated film of a 20 nm Ti layer and a 200 nm Al layer is formed. The Ti layer and the Al layer are processed into the source electrode 24 using a well-known photolithography technique and dry etching processing. A heat treatment of 650 ^° C. may be performed in nitrogen for ohmic source formation. Thereby, the structure shown in FIG. 8 is formed.

In step S9, an Al wiring is formed. Specifically, the insulating layer 17 is formed using a well-known photolithography technique and dry etching. Next, an Al layer is laminated by 2 micrometers. The Al layer is processed into the Al wiring 25 by using a well-known photolithography technique and dry etching. In step S10, the drain electrode 22 is formed. Specifically, a 20 nm Ti layer and a 200 nm Al layer are formed on the back surface of the GaN substrate on which the drain region 11 is to be formed. Thereafter, heat treatment is performed at 400 ^° C. in nitrogen. Thereby, the semiconductor device 1 shown in FIG. 1 is completed.

FIG. 9 is a cross-sectional view of main parts of the semiconductor device 100 according to the second embodiment. The semiconductor device 100 according to Example 2 is a lateral GaN device. Specifically, it is HEMT (High Electron Mobility Transistor). The semiconductor device 100 has a structure in which a back electrode 122, a Si substrate 111, a GaN buffer layer 112, a high resistance GaN layer 141, an undoped GaN layer 142, and an AlGaN layer 143 are stacked. The surface of the Si substrate 111 is a (111) plane. The high resistance GaN layer 141 has a carbon doping concentration of 1 × 10 ¹⁹ cm ₋₃ . The AlGaN layer 143 has an Al ratio of 25% and a thickness of about 25 nm.

In the surface layer portion of the semiconductor device 100, a trench-type insulated gate portion 130 is formed. The insulated gate part 130 is provided in the trench 130T. The trench 130T penetrates the insulating layer 116 of the silicon nitride film and the AlGaN layer 143 and reaches a part of the undoped GaN layer 142. The insulated gate portion 130 has a gate insulating film 132 and a gate electrode 134. The gate electrode 134 is polysilicon doped with boron.

The gate insulating film 132 has a structure in which the second film 132b is stacked above the first film 132a and the third film 132c is stacked above the second film 132b in the trench 130T. The first film 132a, the second film 132b, and the third film 132c of Example 2 are the same as the first film 32a, the second film 32b, and the third film of Example 1 described above. Since it is the same as each of 32c, explanation is omitted.

A source electrode 124 and a drain electrode 144 are arranged on a part of the surface of the AlGaN layer 143. The source electrode 124, the drain electrode 144, and the gate electrode 134 are insulated from each other by an insulating layer 117 of a silicon oxide film. Al wiring 125 is disposed on the surfaces of the source electrode 124, the drain electrode 144, and the gate electrode 134.
(Method for Manufacturing Semiconductor Device 100)
A method for manufacturing the semiconductor device 100 according to the second embodiment will be described with reference to the flowchart of FIG. In the flowchart of FIG. 4, portions that need to be modified in order to manufacture the semiconductor device 100 of the second embodiment will be described. Description of parts common to the method for manufacturing the semiconductor device 1 of the first embodiment is omitted.

First, a substrate on which a Si substrate 111, a GaN buffer layer 112, a high-resistance GaN layer 141, an undoped GaN layer 142, an AlGaN layer 143, and an insulating layer 116 are stacked is prepared. The source region forming step (step S1) in the flowchart of FIG. 4 is skipped, and the process proceeds to the trench forming step of step S2. In step S2, the trench 130T that penetrates the insulating layer 116 and the AlGaN layer 143 and reaches the undoped GaN layer 142 is processed by a known photolithography technique and dry etching. Since the processing contents of the subsequent steps S3 to S10 are the same as those in the first embodiment, description thereof is omitted. The effects of the semiconductor device 100 according to the second embodiment are the same as those of the semiconductor device 1 according to the first embodiment described above.

(Modification)
In the present embodiment, the case where the first film 32a is a silicon oxide film has been described, but the present invention is not limited to this form. For example, the first film 32a may be aluminum oxynitride. Aluminum oxynitride is a film that can make the interface state density at the interface with GaN as low as that of a silicon oxide film. The effect additionally obtained by making the 1st film | membrane 32a into aluminum oxynitride is demonstrated. For example, when a silicon oxide film is used for the first film 32a, if a high temperature heat treatment at 850 ° C. or higher is performed in a state where GaN and the silicon oxide film are in contact with each other, a Ga oxide is formed into the silicon oxide film as the first film 32a. May diffuse and as a result, the gate threshold may decrease. On the other hand, when aluminum oxynitride is used for the first film 32a, Ga diffusion into the aluminum oxynitride film, which is the first film 32a, can be suppressed even when high-temperature heat treatment at 850 ° C. or higher is performed. This is because the aluminum oxynitride film can be denser than the silicon oxide film. By making the first film 32a aluminum oxynitride, it is possible to suppress a decrease in the gate threshold value.

In the case where aluminum oxynitride is formed as the first film 32a, an aluminum nitride film and an aluminum oxide film may be alternately formed using an ALD (Atomic Layer Deposition) method in step S3 of FIG. NH ₃ can be used as the nitrogen source of aluminum nitride, and TMA (Trimethylaluminum) can be used as the aluminum source. H ₂ O or O ₃ can be used as the oxygen source of aluminum oxide, and TMA can be used as the aluminum source. The film forming temperature can be 400 to 500 ° C. The ratio of stacking the aluminum nitride film and the aluminum oxide film is not limited to 1: 1. It is possible to freely set the lamination ratio so that the ratio of oxygen atoms to nitrogen atoms in aluminum oxynitride becomes a desired ratio.

The first film 32a may be a silicon nitride film. The silicon nitride film is a film whose interface state density at the interface with GaN is as low as that of the silicon oxide film. The silicon nitride film is a dense film as compared with the silicon oxide film. Therefore, it is possible to suppress a decrease in the gate threshold value by making the first film 32a a silicon nitride film.

The timing for executing the heat treatment step (step S5) in FIG. 4 is not limited to between steps S4 and S6. The heat treatment process may be performed at any stage as long as it is between the process of forming the second film 32b (step S4) and the gate electrode formation process (step S7).

The method for forming aluminum oxynitride in step S3, the method for forming aluminum oxynitride in step S4, and the method for forming aluminum oxide are not limited to the ALD method. An MOCVD method, a sputtering method, or the like may be used.

The

second films

32b and 132b are not limited to aluminum oxide as long as they are polycrystalline and have a resistance value of 1 × 10 ⁹ (Ωcm) or more. For example, the

second films

32b and 132b may be diamond, AlN, HfO ₂ , BN, or the like. Diamond may be formed by a microwave plasma CVD method. Methane may be used as a raw material. AlN may be formed by an ALD method. TMA may be used as a source gas, and NH ₃ plasma may be used to form a film near 300 ^° C. HfO ₂ may be formed by ALD. TEMAH (tetrakis (ethylmethylamino) hafnium) may be used as the source gas. The film may be formed in the vicinity of 300 ^° C. using any of O ₂ plasma, H ₂ O, and O ₃ . BN may be formed by a microwave plasma CVD method. Alternatively, TMB (Trimethyl Borate) may be used as a source gas and a film may be formed using N ₂ plasma.

The gate insulating film 32 is not limited to the structure described in this specification. For example, a stacked structure of four or more layers may be used, such as further including a fourth film. Further, a structure in which another film is interposed at any position between the first film and the third film may be employed.

As the aluminum oxide, AlN, diamond, BN and the like used for the

second films

32b and 132b, a film that has already been crystallized may be formed by a CVD method or a sputtering method. In this case, the heat treatment for crystallization of the second film can be eliminated.

The material of the

semiconductor devices

1 and 100 is not limited to GaN. A material such as SiC, Si, or GaAs may be used.

In one embodiment of the semiconductor device disclosed in the above example, a first film is stacked above the nitride semiconductor, a second film is stacked above the first film, and a first film is stacked above the second film. A semiconductor device having an insulated gate structure in which three films are stacked and a gate electrode is stacked above the third film.

The first film is a film with few interface traps formed at the interface with the nitride semiconductor. The second film is a polycrystal and has a resistance value of 1 × 10 ⁹ (Ωcm) or more. The third film is an insulator having a breakdown electric field strength of 6 (MV / cm) or more.

In the semiconductor device of the above embodiment, the film structure of the second film is a polycrystalline body. Therefore, defects and impurities in the film can be reduced as compared with amorphous. As a result of suppressing the fluctuation of the charge amount in the film, the controllability and reproducibility of the gate threshold voltage can be improved.

The first film may be a film having an interface trap amount of 3.5 × 10 ¹² cm ⁻² eV ⁻¹ or less. Details of the effect will be described in the above embodiment.

The first film may be a silicon oxide film, a gallium oxide film, or a laminated film of a gallium oxide film and a silicon oxide film. Details of the effect will be described in the above embodiment.

The thickness of the first film may be 4 nm or less. Details of the effect will be described in the above embodiment.

The second film may be aluminum oxide. Details of the effect will be described in the above embodiment.

The third film may be a silicon oxide film. Details of the effect will be described in the above embodiment.

The method for manufacturing a semiconductor device disclosed in the above embodiment includes a step of forming a first film on the surface of a nitride semiconductor with few interface traps formed at the interface with the nitride semiconductor. Forming a second film having a resistance value of 1 × 10 ⁹ (Ωcm) or more on the surface of the first film; A heat treatment step for polycrystallizing the second film by performing heat treatment at a temperature of 800 ^° C. or higher is provided. Forming a third film which is an insulator having a breakdown electric field strength of 6 (MV / cm) or more on the surface of the polycrystallized second film; Forming a gate electrode on the surface of the third film; Details of the effect will be described in the above embodiment.

The heat treatment step may be performed between the step of forming the second film and the step of forming the third film. In the step of forming the third film, the third film may be formed on the surface of the polycrystalline second film. Details of the effect will be described in the above embodiment.

The heat treatment step may be performed between the step of forming the second film and the step of forming the gate electrode.

Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims

A first film (32a, 132a) stacked on the upper side of the nitride semiconductor;
A second film (32b, 132b) stacked above the first film;
A third film (32c, 132c) laminated on the second film;
A semiconductor device comprising a gate electrode (34, 134) stacked above the third film,
Forming an insulated gate structure by the first film, the second film, the third film and the gate electrode;
The first film is a film having few interface traps formed at the interface with the nitride semiconductor,
The second film is polycrystalline and has a resistance value of 1 × 10 9 (Ωcm) or more,
The third film is a semiconductor device which is an insulator having a breakdown electric field strength of 6 (MV / cm) or more.
2. The semiconductor device according to claim 1, wherein the first film is a film having an amount of the interface trap of 3.5 × 10 12 cm −2 eV −1 or less.
3. The first film according to claim 1, wherein the first film is a silicon oxide film, a gallium oxide film, a laminated film of a gallium oxide film and a silicon oxide film, an aluminum oxynitride, or a silicon nitride film. Semiconductor device.
The semiconductor device according to claim 3, wherein a thickness of the first film is 4 nm or less.
5. The semiconductor device according to claim 1, wherein the second film is aluminum oxide.
The semiconductor device according to any one of claims 1 to 5, wherein the third film is a silicon oxide film.
Forming a first film on the surface of the nitride semiconductor with few interface traps formed at the interface with the nitride semiconductor;
Forming a second film having a resistance value of 1 × 10 9 (Ωcm) or more on the surface of the first film;
Polycrystallizing the second film by heat treatment at a temperature of 800 ° C. or higher;
Forming a third film which is an insulator having a breakdown electric field strength of 6 (MV / cm) or more on the surface of the polycrystalline second film;
Forming a gate electrode on the surface of the third film;
A method for manufacturing a semiconductor device.
The heat treatment is performed between forming the second film and forming the third film,
The method of manufacturing a semiconductor device according to claim 7, wherein the third film is formed on the surface of the polycrystallized second film by forming the third film.
The method of manufacturing a semiconductor device according to claim 7, wherein the heat treatment is performed between forming the second film and forming the gate electrode.