JP2009099691A - Method of manufacturing field-effect semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it is difficult to reduce variations of characteristics of a HEMT (High Electron Mobility Transistor) having a recess. <P>SOLUTION: A first electron supply layer 4 which is relatively thin is formed on an electron traveling layer 3 to manufacture the HEMT. Then a semiconductor growth stopping mask layer 6 is formed selectively on the first electron supply layer 4. A second electron supply layer 7 is formed by selectively growing a semiconductor on a portion of the first electron supply layer 4 which is not covered with the semiconductor growth stopping mask layer 6. A source electrode 10 and a drain electrode 11 are formed on the second electron supply layer 7, and a gate electrode 12 is formed on the semiconductor growth stopping mask layer 6 in a recess 9 of the second electron supply layer 7. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a field effect semiconductor device such as a HEMT (High Electron Mobility Transistor) and a MESFET (Metal Semiconductor Field Effect Transistor) having a recess structure.

  A typical conventional HEMT includes an electron transit layer made of a nitride semiconductor such as undoped GaN formed on a substrate such as silicon or sapphire via a buffer layer, and an nGaN doped or undoped AlGaN. An electron supply layer or barrier layer made of a nitride semiconductor such as a source electrode, a drain electrode, and a gate electrode (Schottky electrode) formed on the electron supply layer. The band gap of the electron supply layer made of AlGaN or the like is larger than that of the electron transit layer made of GaN or the like, and the lattice constant of the electron supply layer made of AlGaN or the like is smaller than the lattice constant of the electron transit layer made of GaN or the like. When an electron supply layer having a smaller lattice constant than this is disposed on the electron transit layer, an extensible strain, that is, a tensile stress, is generated in the electron supply layer, resulting in piezoelectric polarization. Since the electron supply layer also spontaneously polarizes, a well-known two-dimensional electron gas layer, that is, a 2DEG layer, is formed in the vicinity of the heterojunction surface between the electron transit layer and the electron supply layer by the action of an electric field based on piezoelectric polarization and spontaneous polarization. As is well known, the 2DEG layer is used as a current path (channel) between the drain electrode and the source electrode, and the current flowing through the current path is controlled by a bias voltage applied to the gate electrode.

By the way, a HEMT having a general configuration has a characteristic that a current flows between a source electrode and a drain electrode in a state where a gate control voltage is not applied to the gate electrode (normal state), that is, a normally-on characteristic. In order to keep the normally-on HEMT in an off state, a negative power source for setting the gate electrode to a negative potential is required, and the electric circuit is necessarily expensive. Therefore, the ease of use of a conventional normally-on HEMT is not good.

Thus, development of a heterojunction field effect semiconductor device having normally-off characteristics has been underway. As a typical method for obtaining normally-off characteristics,
(1) For example, as disclosed in Japanese Patent Application Laid-Open No. 2005-183733 (Patent Document 1), a method of forming a recess, that is, a recess in an electron supply layer and thinning a portion under the gate electrode of the electron supply layer ,
(2) As disclosed, for example, in WO2003 / 071607 (Patent Document 2), a method of removing a part of the electron supply layer and forming an insulated gate there is known.

When the portion under the gate electrode of the electron supply layer is formed thin according to the method of (1) above, the electric field due to piezo polarization and spontaneous polarization of the electron supply layer becomes weak, and this electric field is built-in potential (built-in potential based on the gate electrode). The 2DEG layer is not formed immediately below the gate electrode, and normally-off characteristics are obtained. As is well known, the built-in potential is a potential difference generated between the gate electrode and the electron supply layer based on Schottky contact with the electron supply layer of the gate electrode. However, the method (1) has a problem that when the recess is formed in the electron supply layer by etching, the depth of the recess varies and it is difficult to obtain a predetermined threshold value.

When the insulated gate structure is employed in accordance with the method (2) above, a normally-off characteristic is obtained because the 2DGE layer is not formed in a normally state immediately below the gate electrode of the electron transit layer. However, since the removal of a part of the electron supply layer for forming the insulated gate structure is performed by etching (for example, dry etching), the etching depth is similar to the formation of the recess in the recessed gate structure of (1) above. Variation and deterioration (damage) of the electron transit layer occur.
Note that the MESFET also has a problem of variation in characteristics due to variation in the depth of the recess.
JP 2005-183733 A WO2003 / 071607 Publication

  An object of the present invention is to provide a method capable of easily forming a field effect semiconductor device having a recess.

The present invention for solving the above problems is as follows.
Forming a first semiconductor layer by crystal growth (eg, vapor phase growth) of a first semiconductor material on a substrate;
A second semiconductor material having a property of generating a two-dimensional carrier gas layer in the first semiconductor layer based on a heterojunction with the first semiconductor layer is formed on the first semiconductor layer. Forming a second semiconductor layer by crystal growth;
Forming a semiconductor growth blocking mask layer on a third portion located between the first portion and the second portion of the second semiconductor layer;
On the first and second portions of the second semiconductor layer that are not covered with the semiconductor growth blocking mask layer, a two-dimensional carrier gas layer is formed on the first semiconductor layer, which is the same as the second semiconductor material. Forming a third semiconductor layer by crystal growth of another semiconductor material having properties to be generated;
A source electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the first semiconductor layer and the first portion of the second semiconductor layer; A drain electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the second semiconductor layer and the second portion of the second semiconductor layer, and the semiconductor growth blocking mask And a step of forming a gate electrode disposed on the layer. The present invention relates to a method of manufacturing a heterojunction field effect semiconductor device.

According to a second aspect of the present invention, a continuous growth prevention mask layer is provided instead of the semiconductor growth prevention mask layer, and an amorphous layer is formed on the continuous growth prevention mask layer. Then, after that, it can be removed to form a recess.
Further, as shown in claims 3 and 4, the semiconductor growth blocking mask layer or the continuous growth blocking mask layer can be removed and a gate electrode made of a Schottky electrode can be provided.
Further, as shown in claims 5 and 6, the semiconductor growth blocking mask layer or the continuous growth blocking mask layer can be removed, and then a new gate insulating film can be provided, and a gate electrode can be provided thereon.
According to another aspect of the present invention, a semiconductor growth blocking mask layer, a continuous growth blocking mask layer, or a new gate insulating film can be provided on the first semiconductor layer, and a gate electrode can be provided thereon. .
Further, as shown in claims 11 and 12, the present invention can also be applied to MESFETs.

According to the first, third, fifth, seventh, ninth, and eleventh aspects of the present invention, the semiconductor is selectively grown on a portion that is not covered with the semiconductor growth blocking mask layer, and is covered with the semiconductor growth blocking mask layer. Does not grow on the part where For this reason, a recess is formed on the semiconductor growth prevention mask layer without any special process. The control of the thickness of the semiconductor growth film is easier than the conventional control of the etching depth, and the variation in the thickness of the semiconductor growth film can be made smaller than the variation in the etching depth. Thereby, the variation of the threshold value of the field effect semiconductor device at the time of mass production of the field effect semiconductor device can be easily reduced as compared with the conventional case.
According to the inventions of claims 2, 4, 6, 8, 10, and 12 of the present application, the semiconductor is selectively grown on a portion not covered with the continuous growth blocking mask layer, and is formed on the continuous growth blocking mask layer. An amorphous layer grows. Thereafter, the amorphous layer is removed. The amorphous layer is easier to etch than the semiconductor layer, and the continuous growth blocking mask layer functions as an etching stopper layer. Therefore, the amorphous layer can be removed more easily than when the conventional semiconductor layer is etched. Moreover, since the depth of the recess (recess) generated by etching the amorphous layer depends on the thickness of the semiconductor layer and the amorphous layer, this variation is relatively small. Thereby, the variation of the threshold value of the field effect semiconductor device at the time of mass production of the field effect semiconductor device can be easily reduced as compared with the conventional case.

  Next, a field effect semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a heterojunction field effect semiconductor device according to a first embodiment of the present invention in the order of manufacturing steps. Although the heterojunction field effect semiconductor device according to the first embodiment has a structure different from a typical conventional HEMT, the basic configuration is the same as that of the conventional HEMT, and therefore, it will be referred to as a HEMT. When manufacturing a HEMT according to the first embodiment, first, a substrate 1 shown in FIG. The substrate 1 has one main surface 1a and the other main surface 1b opposite thereto, and functions as a growth substrate for epitaxially growing a semiconductor material and support for mechanically supporting the grown semiconductor layer. It has the function of a substrate. In this embodiment, the substrate 1 is made of silicon in order to reduce costs. However, the substrate 1 can be formed of a semiconductor such as silicon carbide (SiC) other than silicon, GaN, or an insulator such as sapphire or ceramic. Further, a conductivity-determining impurity can be added to the substrate 1 to obtain a conductive semiconductor substrate.

Next, a buffer nitride semiconductor is epitaxially grown (crystal growth) on one main surface 1a of the substrate 1 by a well-known vapor phase growth method such as MOCVD to form the buffer layer 2. In FIG. 1, the buffer layer 2 is shown as a single layer for the sake of simplicity, but actually, it is formed of a plurality of layers. In other words, the buffer layer 2 has alternating first sublayers (first sublayer) made of AlN (aluminum nitride) and second sublayers (second sublayer) made of GaN (gallium nitride). Is a multi-layered buffer laminated on the substrate. Since the buffer layer 2 is not directly related to the operation of the HEMT, it can be omitted. Further, the semiconductor material of the buffer layer 2 can be replaced with a Group 3-5 compound semiconductor other than AlN and GaN, or a buffer layer having a single layer structure can be formed. Further, the buffer layer 2 and the substrate 1 can be regarded as a semiconductor growth substrate in the present invention.

Next, the first semiconductor material is epitaxially grown (crystal growth) on the buffer layer 2 by a known vapor deposition method such as MOCVD, so that the electron transit layer 3 as the first semiconductor layer has a thickness of 1 to 5 μm, for example. Form to thickness. The first semiconductor material is preferably a first nitride semiconductor containing at least Ga and N. In addition, the first nitride semiconductor is
Al _a In _b Ga _1-ab N,
Here, a is a nitride semiconductor that can be expressed by a numerical value that satisfies 0 ≦ a <1, b is a numerical value that satisfies 0 ≦ b <1, and a + b is a numerical value that satisfies 0 ≦ a + b <1. Is desirable. The electron transit layer 3 of this embodiment is made of undoped GaN (gallium nitride) formed by an atmosphere composed of TMG (trimethylgallium) gas and NH ₃ (ammonia) gas. The electron transit layer 3 can also be formed by an epitaxial growth method (vapor phase growth method) other than the MOCVD method.

Next, a second semiconductor material is epitaxially grown on the main surface of the electron transit layer 3 by a well-known vapor phase growth (crystal growth) method such as MOCVD, so that the first electron supply layer 4 as a second semiconductor layer is formed. Form. The first electron supply layer 4 can also be called a spacer layer or an auxiliary electron supply layer, and is heterojunction with the electron transit layer 3 at the interface 5. The first electron supply layer 4 is formed in a process that is continuous with the process of forming the electron transit layer 3. That is, the electron transit layer 3 and the first electron supply layer 4 are sequentially formed by changing only the vapor phase growth atmosphere.
The second semiconductor material forming the first electron supply layer 4 is a two-dimensional electron as a two-dimensional carrier gas layer in the electron transit layer 3 based on a heterojunction with the electron transit layer 3 made of the first semiconductor material. Selected from a semiconductor material having the property of producing a gas layer, ie, a 2DEG layer, having a larger band gap than the first semiconductor material forming the electron transit layer 3 and smaller than the first semiconductor material Has a lattice constant. This second semiconductor material is preferably a nitride semiconductor material, for example,
Al _a Ga _1-a N,
Here, a is a value satisfying 0 <a ≦ 1 and larger than x in the formula representing the first nitride semiconductor material, preferably 0.2 to 0.4, more preferably 0.3. , Or a nitride semiconductor represented by Al _a In _b Ga _1-ab N,
Here, a is a numerical value satisfying 0 <a <1 and larger than x in the formula showing the first nitride semiconductor material, b is a numerical value satisfying 0 ≦ b <1, and a + b is larger than zero. And a nitride semiconductor represented by a value smaller than 1, or In _b Ga _1-b N,
Here, b is a numerical value satisfying 0 <b <1,
It is a nitride semiconductor shown by. In short, it is desirable that the second semiconductor material forming the first electron supply layer 4 is one selected from AlN, AlGaN, AlInGaN, and InGaN. The first electron supply layer 4 of this embodiment is made of Al _0.3 Ga _0.7 N formed in an atmosphere composed of TMA (trimethylaluminum) gas, TMG (trimethylgallium) gas, and NH ₃ (ammonia) gas.

The thickness of the first electron supply layer 4 is such that when no voltage is applied to the gate electrode 12 of FIG. 1C described later, that is, when the voltage between the gate electrode 12 and the source electrode 10 is normally zero, 3 is set to a value at which a 2DEG layer cannot be formed in a portion facing the gate electrode 12, and is preferably 1 to 10 nm, more preferably 3 to 7 nm. When the thickness of the first electron supply layer 4 becomes thinner than 1 nm, for example, the heterojunction interface between the electron transit layer 3 and the first electron supply layer 4 may be deteriorated in an atmosphere in a later process. If the thickness of the first electron supply layer 4 is greater than 10 nm, for example, a 2DEG layer may be formed in a portion of the electron transit layer 3 that faces the gate electrode 12 during normal operation.

Instead of forming the first electron supply layer 4 with an undoped second nitride semiconductor, a second nitride semiconductor to which an n-type (first conductivity type) impurity is added, or another nitride semiconductor, Alternatively, it can be formed of another compound semiconductor.

Next, the semiconductor growth prevention mask layer 6 is formed on the third portion 4c between the first and second portions 4a and 4b of the first electron supply layer 4 which are separated from each other. The first, second and third portions 4a, 4b and 4c of the first electron supply layer 4 are partitioned by broken lines. In this embodiment, a silicon oxide (SiO ₂ ) film having a thickness of 10 to 700 nm is formed on the entire main surface of the first electron supply layer 4 by CVD, for example, and then AlGaN and silicon oxide (SiO ₂ ). ₂ ) by selectively wet-etching using hydrofluoric acid having a large selection ratio with respect to ₂ ), and leaving the SiO ₂ film only on the third portion 4c of the first electron supply layer 4, the semiconductor growth prevention mask layer 6 was formed. The crystal deterioration of the first electron supply layer 4 made of AlGaN due to wet etching is much smaller than the crystal deterioration of the electron supply layer made of AlGaN due to dry etching. The semiconductor growth blocking mask layer 6 is made of silicon oxide represented by SiO _x (x is a numerical value of 1 to 2) other than SiO ₂ , or Si ₃ N _4, SiN _x (where x is a value of N relative to Si. Any numerical value indicating the ratio), silicon nitride (insulator) such as SiN and Si ₂ N ₃ , or aluminum oxide (insulator) such as AlO _x (x is any numerical value indicating the ratio of O), or Polycrystalline AlN (nitride semiconductor) formed in the low temperature epitaxial growth process, or P-type metal oxide semiconductor such as nickel oxide, iron oxide, cobalt oxide, manganese oxide, or HfO (hafnium oxide) it can.

Next, the same semiconductor material as the second semiconductor material is epitaxially grown (crystal growth) on the first and second portions 4a and 4b of the first electron supply layer 4 by a known vapor deposition method such as MOCVD. ) To form a second electron supply layer 7 as a third semiconductor layer. That is, the second electron supply layer 7 made of Al _0.3 Ga _0.7 N is formed in an atmosphere containing TMA (trimethylaluminum) gas, TMG (trimethylgallium) gas, and NH ₃ (ammonia) gas introduced into the reaction chamber. The semiconductor material forming the second electron supply layer 7 is a 2DEG layer on the electron transit layer 3 based on a heterojunction with the electron transit layer 3 made of the first semiconductor material via the first electron supply layer 4. The semiconductor material is selected from semiconductor materials having properties to be generated, has a larger band gap than the first semiconductor material forming the electron transit layer 3, and has a lattice constant smaller than that of the first semiconductor material.
A semiconductor growth condition when forming the second electron supply layer 7 is that the semiconductor grows on the first and second portions 4a and 4b of the first electron supply layer 4, but the semiconductor growth blocking mask layer. It is determined so that the semiconductor does not grow on 6.
The second electron supply layer 7 can also be formed of a third semiconductor material different from the second semiconductor material forming the first electron supply layer 4. The third semiconductor material for the second electron supply layer 7 is, for example,
Al _a Ga _1-a N,
Here, a is a value satisfying 0 <a ≦ 1 and larger than x in the formula representing the first nitride semiconductor material, preferably 0.2 to 0.4, more preferably 0.3. , Or a nitride semiconductor represented by Al _a In _b Ga _1-ab N,
Here, a is a numerical value satisfying 0 <a <1 and larger than x in the formula showing the first nitride semiconductor material, b is a numerical value satisfying 0 ≦ b <1, and a + b is larger than zero. And a nitride semiconductor represented by a value smaller than 1, or In _b Ga _1-b N,
Here, b is a numerical value satisfying 0 <b <1,
Is selected from the nitride semiconductors shown in FIG. In short, it is desirable that the third semiconductor material forming the second electron supply layer 7 is one nitride semiconductor selected from AlN, AlGaN, AlInGaN, and InGaN. Instead of forming the second electron supply layer 7 with an undoped nitride semiconductor, the second electron supply layer 7 can also be formed with a nitride semiconductor to which an n-type (first conductivity type) impurity is added, or another compound semiconductor. .

When the semiconductor material is epitaxially grown on the first and second portions 4a and 4b of the first electron supply layer 4 by vapor deposition to obtain the second electron supply layer 7, the second electron supply layer 7 is obtained. Is formed in contact with the side surface of the semiconductor growth blocking mask layer 8, but no semiconductor layer is formed on the semiconductor growth blocking mask layer 6. For this reason, a recess (recess) 9 is formed between the first portion 7a and the second portion 7b of the second electron supply layer 7 without the step of etching the semiconductor layer.
In FIG. 1, the second electron supply layer 7 is shown not to extend on the semiconductor growth prevention mask layer 6, but by adjusting the ratio between the vertical growth rate and the lateral growth rate of the semiconductor. As shown by a chain line in FIG. 1B, the second electron supply layer 7 can be extended on a part of the semiconductor growth blocking mask layer 6.

The second electron supply layer 7 preferably has a thickness of 10 to 50 nm. The total thickness of the first electron supply layer 4 and the second electron supply layer 7 is 2DEG indicated by a dotted line in FIG. 1B along the interface between the first electron supply layer 4 and the electron transit layer 3. It is set to a value that can generate the layer 8 (for example, 20 to 50 nm), and preferably set to be thinner than the electron transit layer 3. As is well known, the 2DEG layer 8 has a structure in which the first and second electron supply layers 4 and 7 have spontaneous polarization and piezoelectricity based on the heterojunction between the first and second electron supply layers 4 and 7 and the electron transit layer 3. Polarization occurs in an electric field based on these polarizations.

Next, as shown in FIG. 1C, the source electrode 10 and the drain electrode 11 are formed on the first and second portions 7a and 7b of the second electron supply layer 7, and the semiconductor on the bottom surface of the recess 9 is formed. A gate electrode 12 is formed on the growth inhibition mask layer 6. In FIG. 1C, the gate electrode 12 extends to the side surface or the upper surface of the second electron supply layer 7. For the source electrode 10 and the drain electrode 11, for example, titanium (Ti) is deposited on the second electron supply layer 7 to a desired thickness (for example, 25 nm), and then aluminum (Al) is deposited to a desired thickness (for example, 500 nm). Each is formed by vapor deposition and then forming a desired pattern by a photolithographic technique.
The source electrode 10 and the drain electrode 11 of this embodiment are each formed of a laminate of titanium (Ti) and aluminum (Al), but are formed of a metal capable of low resistance contact (ohmic contact) other than this. You can also The source electrode 10 and the drain electrode 11 are electrically coupled to the 2DEG layer 8 through very thin first and second electron supply layers 4 and 7.
The gate electrode 12 is formed of an electrode material that is in Schottky contact with the second electron supply layer 7, for example, Ni / Al. The gate electrode 12 can be formed only on the semiconductor growth blocking mask layer 6 so as not to contact the second electron supply layer 7. As described above, when the second electron supply layer 7 is not contacted, the gate electrode 12 can be formed of a metal material such as aluminum (Al) or a semiconductor such as conductive polysilicon.

When a voltage is not applied to the gate electrode 12 of the HEMT shown in FIG. 1C (normal state), a 2DEG layer is not generated in the region along the semiconductor growth blocking mask layer 6 of the electron transit layer 3 or Alternatively, a channel having an electron concentration that can serve as a current path does not occur. As a result, the 2DEG layer 8 is divided under the gate electrode 12. Therefore, even if the potential of the drain electrode 11 is higher than the potential of the source electrode 10, no current flows between the source electrode 10 and the drain electrode 11, and the source electrode 10 and the drain electrode 11 are electrically connected. The HEMT exhibits normally-off characteristics while being kept off.

When a voltage higher than a predetermined threshold is applied between the gate electrode 12 and the source electrode 10, a channel (current) is formed in a portion of the electron transit layer 3 facing the gate electrode 12 (near the main surface of the electron transit layer 3). A passage) is generated, and the source electrode 10 and the drain electrode 11 are turned on. Therefore, when the potential of the drain electrode 11 is made higher than the potential of the source electrode 10 and a voltage higher than the threshold is applied to the gate electrode 12, electrons are supplied to the source electrode 10 and the first portion of the second electron supply layer 7. 7a, the first portion 4a of the first electron supply layer 4, the 2DEG layer 8, the channel immediately below the gate electrode 12, the 2DEG layer 8, the second portion 4b of the first electron supply layer 4, the second electrons It flows along the path of the second portion 7 b of the supply layer 7 and the drain electrode 11.

The HEMT of Example 1 in FIG. 1 has the following effects.
(1) The second electron supply layer 7 is obtained by selectively growing a semiconductor on the first and second portions 4a and 4b of the first electron supply layer 4 that is not covered with the semiconductor growth blocking mask layer 6. The first and second portions 7a and 7b are obtained, and a recess 9 is formed between them. That is, the recess 9 can be obtained without an etching process. In the case of forming a recess in a conventional electron supply layer by an etching process, it is difficult to control the depth of the recess, and the variation in the depth of the recess and the recess in the electron supply layer ( A variation in the thickness of the remaining portion under the recess) occurred, resulting in a relatively large variation in the HEMT threshold. On the other hand, the control of the thickness of the first electron supply layer 4 formed by vapor deposition is easier than the conventional control of the etching depth. Therefore, the variation in the thickness of the first electron supply layer 4 and the variation in the threshold value of the HEMT during mass production of the HEMT having normally-off characteristics can be easily reduced as compared with the conventional case.
(2) Since the semiconductor growth blocking mask layer 6 is used as a gate insulating film, an HEMT having an insulated gate structure can be provided without providing a process for forming the gate insulating film, thereby reducing costs. Can do.
(3) The interface 5 between the electron transit layer 3 and the first electron supply layer 4 has a great influence on device characteristics such as leakage current and current collapse. In this embodiment, since the first electron supply layer 4 is formed by vapor phase growth that is continuous with the vapor phase growth for forming the electron transit layer 3, the interface 5 is formed of the semiconductor growth blocking mask layer 6 and the second layer. The electron supply layer 7 and the electrodes 10, 11, 12 are protected from the atmosphere when they are formed, and do not deteriorate. Therefore, a HEMT with good device characteristics can be provided.
(4) In this embodiment, since the first electron supply layer 4 and the second electron supply layer 7 are formed of the same semiconductor, homoepitaxial growth occurs, and the second electron supply layer 7 is made of high quality. A HEMT with good characteristics can be provided.

Next, a HEMT according to Example 2 shown in FIG. 2 and a method for manufacturing the HEMT will be described. However, in FIG. 2 and FIGS. 3 to 7 described later, substantially the same parts as in FIG.
In Example 2, as shown in FIG. 2A, the buffer layer 2, the electron transit layer 3, and the first electron supply layer 4 are formed on the substrate 1 in the same manner as in FIG. Further, a continuous growth blocking mask layer 6 a made of the same material as that of the semiconductor growth blocking mask layer 6 is formed on the third portion 4 c of the first electron supply layer 4. The continuous growth blocking mask layer 6a of this embodiment contributes to growing the semiconductor material in an amorphous state.

Next, the first electron supply layer 4 is formed on the first and second portions 4a and 4b of the first electron supply layer 4 and the continuous growth prevention mask layer 6a by a known MOCVD method. The first and second portions 7a and 7b of the second electron supply layer 7 as the third semiconductor layer and the amorphous layer 7c are grown by vapor phase growth of the same semiconductor material as the semiconductor material 2 of FIG. ) Get as shown. When a semiconductor material is grown on the first and second portions 4a and 4b of the first electron supply layer 4 and the continuous growth blocking mask layer 6a by a well-known MOCVD method, the first electron supply layer 4 has a first thickness. On the first and second portions 4a and 4b, the first and second portions 7a and 7b of the second electron supply layer 7 having relatively good crystallinity and grown continuously, that is, in a lattice matching state, are obtained. As a result, a two-dimensional carrier gas layer (two-dimensional electron gas layer) functioning as a current path is formed in the electron transit layer 3 in a normally-on state (a state where no voltage is applied to the gate electrode) on the continuous growth inhibition mask layer 6a An amorphous layer 7c having a property that is not allowed to be obtained is obtained.
When forming the second electron supply layer 7, a semiconductor with good crystallinity grows on the first and second portions 4a and 4b of the first electron supply layer 4, but the continuous growth blocking mask layer 6a. The growth conditions are determined so that a semiconductor with good crystallinity does not grow on the substrate. As a result, an AlGaN amorphous layer 7c is obtained on the continuous growth inhibition mask layer 6a.

Next, the amorphous layer 7c is removed by wet etching. Since the etching rate of the amorphous layer 7c is faster than the etching rate of the second electron supply layer 7, the amorphous layer 7c is removed by performing wet etching without providing a selective etching mask. At this time, the second electron supply layer 7 is also slightly etched, but is much smaller than the etching of the amorphous layer 7c, so that most of the second electron supply layer 7 in FIG. 2B remains. Further, the continuous growth inhibition mask layer 6a made of SiO ₂ functions as an etching stopper when the amorphous layer 7c is etched, and the amorphous layer 7c can be easily removed.

Next, the source electrode 10 and the drain electrode are formed on the first and second portions 7a and 7b of the second electron supply layer 7 as shown in FIG. 11 is formed, and a gate electrode 12 is formed on the continuous growth inhibition mask layer (insulating layer) 6a on the bottom surface of the recess 9.

  The HEMT of Example 2 in FIG. 2 and the manufacturing method thereof are essentially the same as those of Example 1 in FIG. 1, and thus have the same effects as those of Example 1 in FIG.

Next, a HEMT and a manufacturing method thereof according to Example 3 shown in FIG. 3 will be described. The steps in FIGS. 3A and 3B are the same as the steps in FIGS. 1A and 1B. In Example 3, as shown in FIG. 3B, after the second electron supply layer 7 is formed, the semiconductor growth blocking mask layer 6 is removed, and the third electron supply layer 4 in the recess 9 is removed. The portion 4c is exposed. Thereafter, as shown in FIG. 3C, a gate electrode 12a made of a Schottky electrode that is in Schottky contact with the third portion 4c of the first electron supply layer 4 is formed. The gate electrode 12a functions as an electrode for controlling the number of electrons in the 2DEG layer 8. Further, the source electrode 10 and the drain electrode 11 are formed in the same manner as in FIG.

Although the first electron supply layer 4 is interposed between the gate electrode 12a made of a Schottky electrode and the electron transit layer 3, the first electron supply layer 4 is extremely thin, for example, 5 nm, and has already been described. As described above, in the normal state, the electric field based on the heterojunction between the electron transit layer 3 and the third portion 4c of the first electron supply layer 4 is canceled by the built-in potential based on the gate electrode 12a, and the electron transit layer 3 And the 2DEG layer functioning as a current path is not formed along the heterojunction between the first portion 3c and the third portion 4c of the first electron supply layer 4. As a result, a HEMT having normally-off characteristics is obtained.

In Example 3 shown in FIG. 3, a special etching process for forming the recess 9 is not necessary. Therefore, the third embodiment shown in FIG. 3 has the same effect as the first embodiment shown in FIG. In the third embodiment shown in FIG. 3, a step for removing the semiconductor growth prevention mask layer 6 is required. However, since the semiconductor growth prevention mask layer 6 is an insulating film, the first and second electron supplies made of AlGaN are used. It can be easily removed by wet etching in distinction from the layers 4 and 7.

The HEMT according to the fourth embodiment and the manufacturing method thereof are modifications of the second embodiment in FIG. 2 and the third embodiment in FIG. Therefore, Embodiment 4 will be described with reference to FIGS. In Example 4, the same one as shown in FIG. 2B is formed. That is, the amorphous layer 7 c is formed simultaneously with the second electron supply layer 7. In FIG. 3B, the amorphous layer 7c is indicated by a chain line. Next, the amorphous layer 7c is removed as in the second embodiment of FIG. In Example 4, the continuous growth inhibition mask layer 6a shown in FIG. 2B is also removed by etching. Thereafter, similarly to FIG. 3C, the gate electrode 12a, the source electrode 10 and the drain electrode 11 made of a Schottky electrode which are in Schottky contact with the third portion 4c of the first electron supply layer 4 are formed. The gate electrode 12a functions as an electrode for controlling the number of electrons of the 2DEG layer 8.

Since the completed HEMT according to the fourth embodiment is the same as FIG. 3C, it has the same effect as the third embodiment of FIG.

The HEMT according to the fifth embodiment shown in FIG. 4 and the manufacturing method thereof are a modification of the first embodiment shown in FIG. 4A and 4B are the same as FIGS. 1A and 1B. In Example 5 shown in FIG. 4, after the second electron supply layer 7 shown in FIG. 4B is formed, the semiconductor growth blocking mask layer 6 is gradually removed, and the first electron supply layer 7 shown in FIG. A new gate insulating film 6 ′ is provided on the third portion 4 c of the electron supply layer 4, and the gate electrode 12 is provided on the gate insulating film 6 ′.

The fifth embodiment shown in FIG. 4 is the same as the first embodiment shown in FIG. 1 except that a new gate insulating film 6 ′ is provided, and thus has the same effect as the first embodiment.

The HEMT according to the sixth embodiment and the manufacturing method thereof are modifications of the second embodiment in FIG. 2 and the fifth embodiment in FIG. Accordingly, the sixth embodiment will be described with reference to FIGS. In Example 6, first, the same one as shown in FIG. 2B is formed. That is, the amorphous layer 7 c is formed simultaneously with the second electron supply layer 7. In FIG. 4B, the amorphous layer 7c is indicated by a chain line. Next, the amorphous layer 7c is removed as in the second embodiment of FIG. In Example 6, the continuous growth inhibition mask layer 6a shown in FIG. 2B is also removed by etching. Thereafter, as shown in FIG. 4C, a new gate insulating film 6 ′ is provided on the third portion 4c of the first electron supply layer 4, and the gate electrode 12 is formed on the gate insulating film 6 ′. Provide.

Since the completed HEMT according to the sixth embodiment is the same as FIG. 4C, it has the same effect as the fifth embodiment of FIG.

The HEMT according to the seventh embodiment shown in FIG. 5 and the method for manufacturing the HEMT have the semiconductor growth blocking mask layer 6 according to the first embodiment shown in FIG. 1 instead of being provided on the third portion 4 c of the first electron supply layer 4. It is provided on the third portion 3c of the traveling layer 3, and the other portions correspond to those formed substantially the same as the embodiment 1 of FIG. That is, in FIG. 5, the semiconductor growth blocking mask layer 6 is formed on the electron transit layer 3. In FIG. 5, the electron transit layer 3 includes a first and second portions 3a and 3b where the semiconductor growth blocking mask layer 6 is not provided for convenience of explanation, and a third portion between the first and second portions 3a and 3b. And part 3c.

Next, the electron supply layer 7 as the second semiconductor layer on the first and second portions 3a and 3b of the electron transit layer 3 is formed by vapor phase growth. The electron supply layer 7 in FIG. 5 is the same as the second electron supply layer 7 in FIG. 1 and is formed in the same manner. Thereby, a recess 9 is obtained on the semiconductor growth inhibition mask layer 6. 5, a known spacer layer 40 such as AlN or AlInGa may be interposed between the electron transit layer 3 and the electron supply layer 7 as indicated by a chain line.
Next, as shown in FIG. 5C, the source electrode 10 and the drain electrode 11 are formed on the first and second portions 7a and 7b of the electron supply layer 7, and a semiconductor growth blocking mask layer made of an insulator is formed. A gate electrode 12 is formed on 6.

When no voltage is applied to the gate electrode 12 of the HEMT shown in FIG. 5C (normal state), the 2DEG layer is formed on the third portion of the electron transit layer 3 covered with the semiconductor growth blocking mask layer 6. Does not occur. As a result, the 2DEG layer 8 generated along the interface 5 between the first and second portions 3 a and 3 b of the electron transit layer 3 and the electron supply layer 7 is divided under the gate electrode 12. Therefore, even if the potential of the drain electrode 11 is higher than the potential of the source electrode 10, no current flows between the source electrode 10 and the drain electrode 11, and the source electrode 10 and the drain electrode 11 are electrically connected. The HEMT exhibits normally-off characteristics while being kept off.

When a voltage higher than a predetermined threshold is applied between the gate electrode 12 and the source electrode 10, a channel (current) is formed in a portion of the electron transit layer 3 facing the gate electrode 12 (near the main surface of the electron transit layer 3). A passage) is generated, and the source electrode 10 and the drain electrode 11 are turned on. Therefore, when the potential of the drain electrode 11 is made higher than the potential of the source electrode 10 and a voltage higher than the threshold is applied to the gate electrode 12, electrons are supplied to the source electrode 10 and the first portions 7a and 2DEG of the electron supply layer 7. It flows through the path of the layer 8, the channel immediately below the gate electrode 12, the 2 DEG layer 8, the second portion 7 b of the electron supply layer 7, and the drain electrode 11.

Also in Example 7 of FIG. 5, since the recess 9 is obtained by selective growth of the electron supply layer 7, Example 7 of FIG. 5 has the same effect as Example 1 of FIG.

The HEMT and the manufacturing method thereof according to the eighth embodiment are modified from the second embodiment in FIG. 2 and the seventh embodiment in FIG. Therefore, Example 8 will be described with reference to FIGS. In Example 8, the semiconductor growth blocking mask layer 6 of FIG. 5 is used as the continuous growth blocking mask layer 6a of FIG. 2, and the amorphous layer 7c is formed simultaneously with the electron supply layer 7 as in the case of FIG. In FIG. 5B, the amorphous layer 7c is indicated by a chain line. Next, the amorphous layer 7c is removed as in the second embodiment of FIG. Thereafter, similarly to FIG. 5C, the source electrode 10, the drain electrode 11, and the gate electrode 12 are provided. Since the completed HEMT according to the eighth embodiment is the same as FIG. 5C, it has the same effect as the seventh embodiment of FIG.

The HEMT and its manufacturing method according to the ninth embodiment are modified from the fifth embodiment in FIG. 4 and the seventh embodiment in FIG. Therefore, Embodiment 9 will be described with reference to FIGS. In Example 9, after the step of FIG. 5B, the semiconductor growth prevention mask layer 6 is removed, and a portion corresponding to the new gate insulating film 6 ′ of FIG. After the formation, the source electrode 10, the drain electrode 11, and the gate electrode 12 are provided. Since the completed HEMT according to the ninth embodiment is substantially the same as FIG. 5C, it has the same effect as the seventh embodiment of FIG.

The HEMT according to the tenth embodiment and the manufacturing method thereof are modifications of the second embodiment in FIG. 2, the fifth embodiment in FIG. 4, and the seventh embodiment in FIG. Accordingly, the tenth embodiment will be described with reference to FIGS. In Example 10, an amorphous layer similar to the amorphous layer 7c of FIG. 2B is formed simultaneously with the formation of the electron supply layer 7 as in Example 2 of FIG. In FIG. 5B, the amorphous layer 7c is indicated by a chain line. Next, the amorphous layer 7c and the layer corresponding to the continuous growth prevention mask layer 6a in FIG. 2 are removed, and the layer corresponding to the new gate insulating film 6 ′ in FIG. 4 is formed on the third portion 3c of the electron transit layer 3. After that, the source electrode 10, the drain electrode 11, and the gate electrode 12 are provided. Since the completed HEMT according to the tenth embodiment is substantially the same as FIG. 5C, it has the same effect as the seventh embodiment of FIG.

The HEMT according to the eleventh embodiment shown in FIG. 6 and the manufacturing method thereof are a modification of the first embodiment shown in FIG. 6A and 6B are the same as FIGS. 1A and 1B. In Example 11 shown in FIG. 6, after the step of FIG. 6 (B), an n-type impurity implantation region indicated by hatching under the source electrode 10 and the drain electrode 11 is formed as shown in FIG. 6 (C). Contact layers 21 and 22 are provided. Thereafter, as shown in FIG. 6C, the source electrode 10 and the drain electrode 11 are provided on the contact layers 21 and 22, and the gate electrode 12 is provided on the semiconductor growth prevention mask layer 6. Since the HEMT according to the eleventh embodiment shown in FIG. 6 is substantially the same as that shown in FIG. 1C, the HEMT has the same effect as the first embodiment shown in FIG.

Next, a MESFET according to Example 12 shown in FIG. 7 and a method for manufacturing the MESFET will be described.
First, as shown in FIG. 7A, the same buffer layer 2 as in FIG. 1 is formed on the same substrate 1 as in FIG. Next, an auxiliary semiconductor layer 3 ′ is formed on the buffer layer 2. The auxiliary semiconductor layer 3 ′ in FIG. 7 is formed, for example, with the same material and the same method as the electron transit layer 3 in FIG. Since the buffer layer 2 and the auxiliary semiconductor layer 3 ′ are not directly related to the operation of the MESFET, they can be omitted or they can be regarded as a part of the substrate.

Next, the first semiconductor layer 4 ′ is formed by epitaxially growing the first semiconductor material on the auxiliary semiconductor layer 3 ′ by a vapor phase growth method such as a well-known MOCVD method. The first semiconductor layer 4 ′ functions as a channel layer of the MESFET, and is made of, for example, the same nitride semiconductor as the auxiliary semiconductor layer 3 ′ with an n-type impurity added, and has a thickness of, for example, 5 to 20 nm. Have.

Next, as shown in FIG. 7A, the embodiment is formed on the third portion 4c ′ positioned between the first portion 4a ′ and the second portion 4b ′ of the first semiconductor layer 4 ′. The semiconductor growth prevention mask layer 6 is formed by the same method as in FIG.

Next, as shown in FIG. 7B, the first semiconductor is formed on the first and second portions 4a ′ and 4b ′ that are not covered with the semiconductor growth blocking mask layer 6 of the first semiconductor layer 4 ′. A second semiconductor layer 7 ′ is formed by vapor phase growth of the same or different semiconductor material as the material. The second semiconductor layer 7 ′ desirably has a higher n-type impurity concentration than the first semiconductor layer 4 ′ in order to reduce the on-resistance of the MESFET. The second semiconductor layer 7 ′ is composed of first and second portions 7a ′ and 7b ′ grown on the first and second portions 4a ′ and 4b ′ of the first semiconductor layer 4 ′. There is a recess 9 between them.

Next, as shown in FIG. 7C, the semiconductor growth blocking mask layer 6 is removed. Thereafter, a gate electrode 12a ′ made of a Schottky electrode that is in Schottky contact with the third portion 4c ′ of the first semiconductor layer 4 ′ is formed. Note that the gate electrode 12a ′ may be formed so as to extend on the second semiconductor layer 7 ′ as indicated by a dotted line. Further, the source electrode 10 and the drain electrode 11 are formed in ohmic contact with the first and second portions 7a ′ and 7b ′ of the second semiconductor layer 7 ′.

In this MESFET, a depletion layer is generated in the third portion 4c ′ of the first semiconductor layer 4 ′ where the gate electrode 12a ′ is in Schottky contact, and the current flowing through the first semiconductor layer 4 ′ is controlled. . In order to fill the portion immediately below the gate electrode 12a ′ of the first semiconductor layer 4 ′ with a depletion layer, it is required to reduce the thickness of the third portion 4c ′ of the first semiconductor layer 4 ′. Conventionally, by selectively etching the first semiconductor layer 4 ′, a recess is formed in a portion immediately below the gate electrode 12a ′ of the first semiconductor layer 4 ′ to selectively thin the first semiconductor layer 4 ′. Therefore, the variation in the depth of the recess becomes the variation in the thickness of the portion immediately below the gate electrode 12a ′ of the first semiconductor layer 4 ′, resulting in variations in the characteristics of the MESFET. On the other hand, in the MESFET according to Example 12 shown in FIG. 7, a special etching step for forming the recess 9 is unnecessary, and the recess (by the selective growth of the second semiconductor layer 7 ′, which can easily control the thickness, Recess 9 is formed. For this reason, manufacture of MESFET which has the recessed part (recess) 9 becomes easy.

The MESFET according to the thirteenth embodiment and the manufacturing method thereof are modified from the second embodiment in FIG. 2 and the twelfth embodiment in FIG. Accordingly, the thirteenth embodiment will be described with reference to FIGS. Also in the embodiment 13, the semiconductor growth blocking mask layer 6 having the same function as the continuous growth blocking mask layer 6a in FIG. 2B is formed on the semiconductor growth blocking mask layer 6 in the same manner as in the embodiment 2 in FIG. The amorphous layer 7c is formed as indicated by a chain line. Next, the amorphous layer 7c is removed as in the second embodiment of FIG. Further, the semiconductor growth inhibition mask layer 6 corresponding to the continuous growth inhibition mask layer 6a in FIG. 2 is also removed by etching. Thereafter, a gate electrode 12a made of a Schottky electrode is formed in Schottky contact with the third portion 4c ′ of the first semiconductor layer 4 ′ as in FIG. 7C. Further, the source electrode 10 and the drain electrode 11 are formed in ohmic contact with the first and second portions 7a ′ and 7b ′ of the second semiconductor layer 7 ′.

Since the completed MESFET according to the thirteenth embodiment has the same configuration as that of FIG. 7C, the thirteenth embodiment can obtain the same effects as those of the twelfth embodiment of FIG.

The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) The electron supply layers 4 and 7 of each embodiment can be replaced with a hole supply layer made of a p-type semiconductor. In this case, a two-dimensional hole gas layer is generated as a two-dimensional carrier gas layer in a region corresponding to the 2DEG layer 8.
(2) In the second to thirteenth embodiments, a layer corresponding to the contact layers 21 and 22 in FIG. 6 can be provided.
(3) In the HEMTs of Examples 1 to 11, the electron supply layers 4 and 7 under the source electrode 10 and the drain electrode 11 are removed to expose the electron transit layer 3 or the thickness of the electron supply layers 4 and 7 is increased. An extremely thin digging is formed, and the source electrode 10 and the drain electrode 11 are formed in the digging, and the connection resistance between the source electrode 10 and the drain electrode 11 and the 2DEG layer 8 can be reduced. Further, in the MESFETs of Examples 12 to 13, a dig may be formed in the second semiconductor layer 7 ′, and the source electrode 10 and the drain electrode 11 may be formed in this dig.
(4) One or more of known gate field plates, source field plates, and drain field plates can be provided.
(5) A cap layer made of, for example, undoped GaN or AlGaN can be provided on the electron supply layer 7 for the purpose of controlling surface charge.
(6) Although one source electrode 10, one drain electrode 11, and one gate electrode 12 or 12a are shown in FIGS. 1 to 7, a plurality of each can be provided in one semiconductor chip. That is, a plurality of minute HEMTs (unit HEMT) or minute MESFETs (unit MESFET) can be provided in one semiconductor chip, and these can be connected in parallel.
(7) Instead of the gate electrode 12a made of the Schottky electrode in FIG. 7C, a gate electrode can be provided on the first semiconductor layer 4 ′ via a gate insulating film.
(8) The semiconductor growth blocking mask layer 6 can also be formed thicker than the second electron supply layer 7 or the second semiconductor layer 7 ′ of FIG.

It is sectional drawing which shows HEMT of Example 1 of this invention in order of a manufacturing process. It is sectional drawing which shows HEMT of Example 2 of this invention in order of a manufacturing process. It is sectional drawing which shows HEMT of Example 3 and 4 of this invention in order of a manufacturing process. It is sectional drawing which shows HEMT of Example 5 and 6 of this invention in order of a manufacturing process. It is sectional drawing which shows HEMT of Examples 7-10 of this invention in order of a manufacturing process. It is sectional drawing which shows HEMT of Example 11 of this invention in order of a manufacturing process. It is sectional drawing which shows MESFET of Example 12 and 13 of this invention in order of a manufacturing process.

Explanation of symbols

1 Substrate 2 Buffer layer 3 Electron travel layer (first semiconductor layer)
4 First electron supply layer (second semiconductor layer)
6 Semiconductor growth blocking mask layer 7 Second electron supply layer (third semiconductor layer)
10 Source electrode 11 Drain electrode 12 Gate electrode

Claims (12)

Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
A second semiconductor material having a property of generating a two-dimensional carrier gas layer in the first semiconductor layer based on a heterojunction with the first semiconductor layer is crystallized on the first semiconductor layer. Forming a second semiconductor layer by growing;
Forming a semiconductor growth blocking mask layer on a third portion located between the first portion and the second portion of the second semiconductor layer;
On the first and second portions of the second semiconductor layer that are not covered with the semiconductor growth blocking mask layer, a two-dimensional carrier gas layer is formed on the first semiconductor layer, which is the same as the second semiconductor material. Forming a third semiconductor layer by crystal growth of another semiconductor material having properties to be generated;
A source electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the first semiconductor layer and the first portion of the second semiconductor layer; A drain electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the second semiconductor layer and the second portion of the second semiconductor layer, and the semiconductor growth blocking mask Forming a gate electrode disposed on the layer, and a method for manufacturing a heterojunction field effect semiconductor device. Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
A second semiconductor material having a property of generating a two-dimensional carrier gas layer in the first semiconductor layer based on a heterojunction with the first semiconductor layer is crystallized on the first semiconductor layer. Forming a second semiconductor layer by growing;
Continuous growth having a property of preventing a semiconductor material from continuously growing on a third portion located between the first portion and the second portion of the second semiconductor layer. Forming a blocking mask layer;
A two-dimensional carrier gas layer is formed on the first and second portions of the second semiconductor layer and on the continuous growth blocking mask layer, the same as the second semiconductor material, or a two-dimensional carrier gas layer on the first semiconductor layer. Crystal growth of another semiconductor material having the properties to be generated to obtain a third semiconductor layer on the first and second portions of the second semiconductor layer, while simultaneously preventing the continuous growth Obtaining an amorphous layer on the mask layer;
Removing the amorphous layer;
A source electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the first semiconductor layer and the first portion of the second semiconductor layer; A drain electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the second semiconductor layer and the second portion of the second semiconductor layer, and the continuous growth inhibition And a step of forming a gate electrode disposed on the mask layer. A method of manufacturing a heterojunction field effect semiconductor device, comprising: Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
A second semiconductor material having a property of generating a two-dimensional carrier gas layer in the first semiconductor layer based on a heterojunction with the first semiconductor layer is crystallized on the first semiconductor layer. Forming a second semiconductor layer by growing;
Forming a semiconductor growth blocking mask layer on a third portion located between the first portion and the second portion of the second semiconductor layer;
Another semiconductor having the same property as the second semiconductor material on the first and second portions of the second semiconductor layer or a property of generating a two-dimensional carrier gas layer in the first semiconductor layer Forming a third semiconductor layer by crystal growth of the material;
Removing the semiconductor growth blocking mask layer;
A source electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the first semiconductor layer and the first portion of the second semiconductor layer; A drain electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the second semiconductor layer and the second portion of the second semiconductor layer, and the second semiconductor Forming a gate electrode in Schottky contact with the third portion of the layer. A method of manufacturing a heterojunction field effect semiconductor device, comprising: Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
A second semiconductor material having a property of generating a two-dimensional carrier gas layer in the first semiconductor layer based on a heterojunction with the first semiconductor layer is crystallized on the first semiconductor layer. Forming a second semiconductor layer by growing;
Continuous growth having a property of preventing a semiconductor material from continuously growing on a third portion located between the first portion and the second portion of the second semiconductor layer. Forming a blocking mask layer;
A two-dimensional carrier gas layer is formed on the first and second portions of the second semiconductor layer and on the continuous growth blocking mask layer, the same as the second semiconductor material, or a two-dimensional carrier gas layer on the first semiconductor layer. Crystal growth of another semiconductor material having the properties to be generated to obtain a third semiconductor layer on the first and second portions of the second semiconductor layer, while simultaneously preventing the continuous growth Obtaining an amorphous layer on the mask layer;
Removing the amorphous layer and the continuous growth inhibition mask layer;
A source electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the first semiconductor layer and the first portion of the second semiconductor layer; A drain electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the second semiconductor layer and the second portion of the second semiconductor layer, and the second semiconductor Forming a gate electrode in Schottky contact with the third portion of the layer. A method of manufacturing a heterojunction field effect semiconductor device, comprising: Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
A second semiconductor material having a property of generating a two-dimensional carrier gas layer in the first semiconductor layer based on a heterojunction with the first semiconductor layer is crystallized on the first semiconductor layer. Forming a second semiconductor layer by growing;
Forming a semiconductor growth blocking mask layer on a third portion located between the first portion and the second portion of the second semiconductor layer;
On the first and second portions of the second semiconductor layer that are not covered with the semiconductor growth blocking mask layer, a two-dimensional carrier gas layer is formed on the first semiconductor layer, which is the same as the second semiconductor material. Forming a third semiconductor layer by crystal growth of another semiconductor material having properties to be generated;
Removing the semiconductor growth blocking mask layer;
Forming a gate insulating film on the third portion of the second semiconductor layer;
A source electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the first semiconductor layer and the first portion of the second semiconductor layer; A drain electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the second semiconductor layer and the second portion of the second semiconductor layer, and the gate insulating film And a step of forming a gate electrode disposed on the heterojunction field effect semiconductor device. Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
A second semiconductor material having a property of generating a two-dimensional carrier gas layer in the first semiconductor layer based on a heterojunction with the first semiconductor layer is crystallized on the first semiconductor layer. Forming a second semiconductor layer by growing;
Continuous growth having a property of preventing a semiconductor material from continuously growing on a third portion located between the first portion and the second portion of the second semiconductor layer. Forming a blocking mask layer;
A two-dimensional carrier gas layer is formed on the first and second portions of the second semiconductor layer and on the continuous growth blocking mask layer, the same as the second semiconductor material, or a two-dimensional carrier gas layer on the first semiconductor layer. Crystal growth of another semiconductor material having the properties to be generated to obtain a third semiconductor layer on the first and second portions of the second semiconductor layer, while simultaneously preventing the continuous growth Obtaining an amorphous layer on the mask layer;
Removing the amorphous layer and the continuous growth inhibition mask layer;
Forming a gate insulating film on the third portion of the second semiconductor layer;
A source electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the first semiconductor layer and the first portion of the second semiconductor layer; A drain electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the second semiconductor layer and the second portion of the second semiconductor layer, and the gate insulating film And a step of forming a gate electrode disposed on the heterojunction field effect semiconductor device. Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
Forming a semiconductor growth blocking mask layer on a third portion located between the first portion and the second portion of the first semiconductor layer;
Two-dimensionally in the first semiconductor layer based on a heterojunction with the first semiconductor layer on the first and second portions of the first semiconductor layer not covered with the semiconductor growth blocking mask layer Forming a second semiconductor layer by crystal growth of a second semiconductor material having the property of generating a carrier gas layer;
A source electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the first portion of the first semiconductor layer and the second semiconductor layer; A drain electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the second portion of the semiconductor layer and the second semiconductor layer, and the semiconductor growth blocking mask Forming a gate electrode disposed on the layer, and a method for manufacturing a heterojunction field effect semiconductor device. Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
Forming a continuous growth inhibition mask layer on a third portion located between the first portion and the second portion of the first semiconductor layer;
Having a property of generating a two-dimensional carrier gas layer in the first semiconductor layer on the first and second portions of the first semiconductor layer based on a heterojunction with the first semiconductor layer; A second semiconductor material is grown by crystal growth to obtain a second semiconductor layer, and simultaneously, the second semiconductor material is vapor-phase grown on the continuous growth blocking mask layer to obtain an amorphous layer;
Removing the amorphous layer;
A source electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the first portion of the first semiconductor layer and the second semiconductor layer; A drain electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the second portion of the semiconductor layer and the second semiconductor layer, and the continuous growth inhibition Forming a gate electrode disposed on the layer, and a method for manufacturing a heterojunction field effect semiconductor device. Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
Forming a semiconductor growth blocking mask layer on a third portion located between the first portion and the second portion of the first semiconductor layer;
Two-dimensionally in the first semiconductor layer based on a heterojunction with the first semiconductor layer on the first and second portions of the first semiconductor layer not covered with the semiconductor growth blocking mask layer Forming a second semiconductor layer by crystal growth of a second semiconductor material having the property of generating a carrier gas layer;
Removing the semiconductor growth blocking mask layer;
Forming a gate insulating film on the third portion of the first semiconductor layer;
A source electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the first portion of the first semiconductor layer and the second semiconductor layer; A drain electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the second portion of the semiconductor layer and the second semiconductor layer, and the gate insulating film And a step of forming a gate electrode disposed on the heterojunction field effect semiconductor device. Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
Forming a continuous growth inhibition mask layer on a third portion located between the first portion and the second portion of the first semiconductor layer;
Having a property of generating a two-dimensional carrier gas layer in the first semiconductor layer on the first and second portions of the first semiconductor layer based on a heterojunction with the first semiconductor layer; A second semiconductor material is grown by crystal growth to obtain a second semiconductor layer, and simultaneously, the second semiconductor material is vapor-phase grown on the continuous growth blocking mask layer to obtain an amorphous layer;
Removing the amorphous layer and the continuous growth inhibition mask layer;
Forming a gate insulating film on the third portion of the first semiconductor layer;
A source electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the first portion of the first semiconductor layer and the second semiconductor layer; A drain electrode electrically connected to a two-dimensional carrier gas layer formed along a heterojunction surface between the second portion of the semiconductor layer and the second semiconductor layer, and the gate insulating film And a step of forming a gate electrode disposed on the heterojunction field effect semiconductor device. Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
Forming a semiconductor growth blocking mask layer on a third portion located between the first portion and the second portion of the first semiconductor layer;
A second semiconductor material is grown by crystal growth of the same or different semiconductor material as the first semiconductor material on the first and second portions of the first semiconductor layer that are not covered with the semiconductor growth blocking mask layer. Forming a semiconductor layer;
Removing the semiconductor growth blocking mask layer;
A source electrode electrically connected to the first portion of the first semiconductor layer, a drain electrode electrically connected to the second portion of the first semiconductor layer, and the first semiconductor Forming a gate electrode in Schottky contact with the first portion of the layer. A method of manufacturing a field effect semiconductor device, comprising: Forming a first semiconductor layer by crystal growth of a first semiconductor material on a substrate;
Forming a continuous growth inhibition mask layer on a third portion located between the first portion and the second portion of the first semiconductor layer;
Crystal growth of the same semiconductor material as or different from the first semiconductor material on the first and second portions of the first semiconductor layer and on the continuous growth blocking mask layer. Obtaining a second semiconductor layer comprising crystals on the first and second portions of the layer, and simultaneously obtaining an amorphous layer on the continuous growth blocking mask layer;
Removing the amorphous layer and the continuous growth inhibition mask layer;
A source electrode electrically connected to the first portion of the first semiconductor layer, a drain electrode electrically connected to the second portion of the first semiconductor layer, and the first semiconductor And a step of forming a gate electrode in Schottky contact with the first portion of the layer.

Images