KR101952175B1 - Nitride semiconductor device and method for manufacturing the same - Google Patents

Abstract

A nitride semiconductor device and a manufacturing method thereof are disclosed. Embodiments of the present invention can provide a nitride semiconductor device, particularly an HFET, as a horizontal device, having advantages such as a vertical device, widening the area of the drain electrode, and forming electrodes below the GaN layer, . Embodiments of the present invention make it possible to reduce the element area due to an increase in current, by allowing the nitride semiconductor to grow on the n-type GaN so that the electrons flow in the vertical direction from the source to the drain, thereby maximizing the advantage of the nitride semiconductor device . Embodiments of the present invention implement a normally-off by forming a nitride semiconductor device vertically.

Description

[0001] NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [0002]

The present invention relates to a nitride semiconductor device having a vertical structure and a method of manufacturing the same.

The nitride semiconductor is a broadband bandgap compound semiconductor and is capable of emitting light up to a visible range and broadly to the ultraviolet range. Blue-violet laser diodes and blue light-emitting diodes are used in a wide range of fields ranging from optical pickup devices, traffic lights, public displays, liquid crystal backlights, and lighting.

Nitride semiconductors are attracting attention due to their high critical electric field, low on resistance, high temperature and high frequency operation characteristics compared to silicon and are being studied as materials for next generation semiconductor devices.

BACKGROUND ART [0002] Metal-oxide semiconductor field-effect-transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) are generally used for high output power devices. In addition, devices such as a high electron mobility transistor (HEMT), a heterojunction field-effect transistor (HFET), and a MOSFET are studied as a gallium nitride (GaN) .

HEMTs are used for high frequency communication devices and the like by using high mobility of electrons. On the other hand, in the case of a MOSFET, due to the absence of a good gate oxide film and the difficulty of ion implantation and thermal diffusion process to selectively form a P-type or N-type region, The effect is not prominent.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET). Referring to FIG. 1, a general HFET includes a substrate 1, a first GaN layer 2 formed on the substrate, an AlGaN layer 3 formed on the first GaN layer, 2 GaN layer 4, a gate electrode 5, a source electrode 6 and a drain electrode 7 formed on the second GaN layer.

A typical HFET operates to switch a two-dimensional electron gas (2DEG) current flowing from a drain electrode to a source electrode through a schottky gate electrode.

In the case of a general HFET device, the quality of the Schottky characteristic using the gate operation can have a large influence on the switching characteristics of the device. Therefore, the role of minimizing leakage on the gate side and expanding the depletion region is of the utmost importance. Also, there is a need for a technique of moving the threshold voltage (supply voltage) in the positive direction so that the current flow of the 2DEG channel in the heterojunction structure is normally turned off.

On the other hand, since the high-voltage GaN HFET device is a horizontal type device, all three electrodes of the gate, source, and drain are formed on the surface of the substrate, and the size of the electrode determines the size of the device. However, for the high breakdown voltage, the distance between the electrodes must be secured to a certain extent, and in order to reduce the area, the source and drain which occupy a relatively large area must be reduced.

In addition, many devices are manufactured by connecting a field plate for field relaxation to a source or gate for high voltage resistance. This is for the purpose of alleviating the electric field at the device surface side, and therefore, it is possible to fabricate a structure that alleviates the electric field at the substrate side or at the drain side.

Because of the horizontal characteristics of the HFET structure, all three electrodes of gate, source, and drain are fabricated on the surface of the substrate. In order to fabricate a large current device, the device area is widened, Also, a 2DEG layer used as a channel of the HFET is formed in the horizontal direction.

Embodiments of the present invention have an object to provide a nitride semiconductor device and a method of manufacturing the same, which can increase a current and reduce a device size.

Embodiments of the present invention are directed to a nitride semiconductor device having a vertical structure that reduces the area of the horizontal-type device and increases the amount of current, and a method of manufacturing the same.

A nitride semiconductor device according to an embodiment includes a low resistance layer formed on a substrate and formed of a nitride semiconductor, a channel layer formed on the low resistance layer, a barrier layer formed on the channel layer, A source electrode formed on the barrier layer, a channel layer and a barrier layer, and a recess region formed to include a partial region of the low-resistance layer, the drain electrode being formed below the low-resistance layer, And a gate electrode formed on the substrate.

The gate electrode further includes a gate insulating film layer formed in the recess region. Here, the gate metal layer is formed on the gate insulating film layer.

The recessed region may be in the form of one or more of a trench shape, a V-groove shape, a semicircular shape, and a stepped shape.

The source electrode is formed in a portion where the gate electrode is not formed, and is made of metal. The gate electrode and the source electrode may be alternately formed. In addition, the two source electrodes may share one gate electrode.

A method of fabricating a nitride semiconductor device according to one embodiment includes forming a low resistance layer on a substrate, forming a channel layer on the low resistance layer, forming a barrier layer on the channel layer, Forming a source electrode on the barrier layer; etching the channel layer, the barrier layer, and a portion of the low-resistance layer to form a recess region; forming a gate electrode in the recess region; And forming a drain electrode on the back surface of the substrate or under the low resistance layer.

According to another embodiment of the present invention, there is provided a method of manufacturing a nitride semiconductor device, comprising: forming a low-resistance layer on a substrate; selectively growing a channel layer on the low-resistance layer; forming a barrier layer on the channel layer Forming a source electrode on the barrier layer; forming a gate electrode in a recessed region in which the barrier layer and the channel layer are not formed; forming a gate electrode on the backside of the substrate, And forming a second electrode.

The above embodiments are further comprised of forming a gate insulating film layer on the barrier layer. The step of forming the source electrode may include defining a source region by selectively etching the gate insulating layer, and forming the source electrode on the source region.

In the above embodiments, the step of forming the gate electrode may include a step of forming a gate insulating film layer in the recess region, and a step of forming the gate electrode on the gate insulating film layer.

Embodiments of the present invention can provide a nitride semiconductor device, particularly an HFET, as a horizontal device, having advantages such as a vertical device, widening the area of the drain electrode, and forming electrodes below the GaN layer, .

Embodiments of the present invention make it possible to reduce the element area due to an increase in current, by allowing the nitride semiconductor to grow on the n-type GaN so that the electrons flow in the vertical direction from the source to the drain, thereby maximizing the advantage of the nitride semiconductor device .

Embodiments of the present invention implement a normally-off by forming a nitride semiconductor device vertically.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET);
FIG. 2 illustrates a structure of a nitride semiconductor device according to an embodiment; FIG.
3 is a flow chart schematically illustrating a method of manufacturing a nitride semiconductor device according to an embodiment;
FIGS. 4A to 4F are illustrations for explaining an operation of manufacturing a nitride semiconductor according to an embodiment; FIGS.
FIG. 5 is a flowchart schematically showing a method of manufacturing a nitride semiconductor device according to another embodiment; FIG.
Figures 6A-6D illustrate various forms of recessed regions according to embodiments of the present invention;
FIGS. 7A and 7B schematically show a nitride semiconductor device having gate electrodes of different types; FIG. And
8 is a view showing the arrangement of the respective electrodes according to the fabrication of a plurality of nitride semiconductor devices.

Referring to FIG. 2, the nitride semiconductor device according to one embodiment includes a low-resistance layer, a channel layer, a barrier layer, and a gate electrode, a source electrode, and a drain electrode.

The low-resistance layer 10 is formed on the substrate 1 and is made of a nitride-based semiconductor. The channel layer 20 is formed on the low resistance layer 10 and the barrier layer 30 is formed on the channel layer 20. The drain electrode 60 is formed under the low resistance layer 10, . A gate electrode 40 and a source electrode 50 are formed on the barrier layer 30, respectively.

The substrate 1 may be an insulating substrate such as a sapphire substrate or the like. The substrate 1 may be formed of one of a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and a silicon (Si) substrate. The substrate 1 may be removed after fabrication of the nitride semiconductor device. In this case, the structure of the final device may be a structure in which the substrate 1 is not provided. For example, as shown in FIG. 4E, in the case of an insulating substrate, it is necessary to remove the substrate before the drain electrode 60 is deposited. On the other hand, when the substrate is a gallium nitride substrate or the like, the substrate may be removed or not removed before the drain electrode 60 is deposited.

The low-resistance layer 10 is made of an n-type gallium nitride (n-GaN). The thickness of the low-resistance layer 10 is 0.01 to 10 micrometers (占 퐉). Preferably, the low resistance layer 10 is grown to a thickness of 0.1 to 2 μm.

The low resistance layer 10 can be formed in various ways. A metal organic chemical vapor deposition (MOCVD), a molecular beam epitaxy (MBE), a hydride vapor phase epitaxy (HVPE), a plasma enhanced chemical vapor deposition (PECVD), Sputtering, and Atomic Layer Deposition (ALD). However, considering the crystallinity of the low-resistance layer 10, the low-resistance layer 10 is generally fabricated by metal-organic chemical vapor deposition. TMGa as a raw material of Ga, and NH ₃ as a raw material of N are synthesized at a high temperature in a reactor to perform epitaxial growth.

The channel layer 20 is made of gallium nitride (GaN). A two-dimensional electron gas (2DEG) is formed in the channel layer 20. [ The thickness of the channel layer 20 is 0.01 to 0.5 micrometers ([mu] m). Preferably 0.05 to 0.2 mu m. The channel layer 20 may also be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, or the like, in the same manner as the low resistance layer 10.

The barrier layer 30 is made of aluminum gallium nitride (AlGaN), i.e., Al _x Ga _{1 - x} N. The thickness of the barrier layer 30 is 0 to 100 nanometers (nm). Preferably 0 to 10 nm. The Al composition of AlGaN is preferably 1 to 100%, and more preferably 10 to 50%. The barrier layer 30 may also be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, or the like, similar to the channel layer 20 or the low-

For example, as shown in FIGS. 4A to 4C, an N-type GaN layer is grown to a thickness of 0.01 to 10 μm, preferably 0.05 to 0.2 μm on a substrate 1, and then a GaN channel layer, The nitride semiconductor device according to the embodiments of the present invention is manufactured by growing AlGaN at 0 to 100 nm, preferably 0 to 10 nm.

After the epitaxial growth, the source electrode 50 is formed on the surface side as shown in Fig. 4D. The source electrode 50 is formed in a portion where the gate electrode 40 is not formed, and is made of metal. Referring to the drawings, the nitride semiconductor device according to embodiments of the present invention can be implemented to have an integration degree of twice or more than that of a conventional structure that is deposited on the surface up to the drain electrode 60. By doing so, the size of the device is remarkably reduced, resulting in a structure suitable for mass production.

The source electrode 50 is formed of an ohmic contact. For example, the source electrode 50 may be formed by depositing Ti / Al / Ti / Au with a thickness of 30/100/20/200 nm using an electron beam evaporator to form a pattern by a lift- do.

As shown in Fig. 8, in the present invention, the gate electrode 40 and the source electrode 50 are formed alternately. By doing so, the two source electrodes share one gate electrode.

Next, as shown in FIG. 4D, a portion where a gate electrode is to be formed is etched so that a vertical channel is formed. That is, the channel layer 20 and a part of the barrier layer 30 are etched. At this time, the etching depth passes through the portion where the channel layer 20 and the n-GaN low-resistance layer 10 contact.

The gate electrode 40 is formed in the etched recessed region 70 of the barrier layer 30 and channel layer 20, as shown in Figure 4F. The gate electrode 40 includes a gate metal layer 43 made of a metal. That is, as shown in FIG. 7B, the nitride semiconductor device may have a MES (Metal-Semiconductor) structure. Here, FIGS. 7A and 7B are views showing a nitride semiconductor device in a unit unit.

The gate electrode 40 may further include a gate insulating film layer 41 formed in the recess region. The gate insulating film layer 41 is made of at least one of silicon oxide (SiO ₂ ), hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), and silicon nitride (SiN).

A gate metal layer 43 is formed on the gate insulating film layer 41. That is, as shown in FIG. 7A, the nitride semiconductor device may have a MIS (Metal-Insulator-Semiconductor) structure.

The gate insulating film layer 41 may be formed by various methods. For example, based on at least one of metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, sputtering, and atomic layer deposition. The thickness of the gate insulating film layer 41 is 0.1 to 300 nanometers (nm). Preferably, the gate insulating film layer 41 is deposited to a thickness of 1 to 100 nm.

6A to 6D are views showing various forms of the recess region. 6A to 6D, the recessed region 70 may have a trench shape (FIG. 6A), a V-groove shape (FIG. 6B), a semicircular shape (Fig. 6C), and a stepped configuration (Fig. 6D).

It is preferable that the recessed region 70 is etched so as to have a depth greater than a portion where the channel layer 20 and the low-resistance layer 10 are in contact with each other. The gate electrode formed on the recessed region may enlarge the depletion region near the 2DEG to provide the advantage of the threshold voltage (supply voltage) being shifted in the positive direction (or the normally-off characteristic). If only the channel layer 20 and the barrier layer 30 are removed, some channel layer 20 may remain in the recess region during the etching process. In this case, the channel layer 20 has a high resistance, . ≪ / RTI > When the channel layer 20 operates as an insulating layer, it does not have an advantage of a vertical structure because vertical channel formation can not be achieved by blocking the flow of electricity in the drain direction. Therefore, in the present invention, a recess region is formed by including a partial region of the low-resistance layer 10. However, the depth of the recessed region is controlled not to exceed 1/3 of the thickness of the low-resistance layer 10. When the depth of the recessed region exceeds 1/3 of the thickness, the distance between the gate and the drain electrode becomes close to each other, and the possibility of dielectric breakdown may occur.

Finally, as shown in FIG. 4F, when the drain electrode 60 is deposited under the low-resistance layer 10, the nitride semiconductor device is fabricated. The drain electrode 60 is also made to be an ohmic contact like the source electrode 50. If the substrate is not removed, the drain electrode 60 may be formed on the backside of the substrate instead of the bottom of the low-resistance layer.

By doing so, the nitride semiconductor device realizes a normally off-state, and becomes a vertical type device, thereby remarkably reducing the size of the device, and has a structure suitable for mass production. That is, the nitride semiconductor device has an integration degree of twice or more as compared with the conventional structure in which the nitride semiconductor device is deposited on the surface up to the drain electrode.

(-) charge is collected on the opposite side of the gate insulating film layer when the (+) voltage is applied to the gate electrode 40. Electrons emitted from the source electrode 50 by this accumulation phenomenon are transferred to the low resistance layer ). The electrons entering the low resistance layer 10 escape to the drain electrode 60 and the current flows.

4A to 4F, the recess region is formed by successively growing a low-resistance layer, a channel layer, and a barrier layer on a substrate and then selectively etching the substrate. However, a channel layer, Layer may be selectively grown to form the gate electrode. This will be described later.

Referring to FIG. 3, a method of fabricating a nitride semiconductor device according to an embodiment includes forming a low-resistance layer on a substrate (S110), forming a channel layer on the low-resistance layer (S120) (S140) forming a barrier layer on the channel layer, forming a source electrode on the barrier layer (S140), etching the channel layer, the barrier layer, and a part of the low-resistance layer to form a recessed region A step S160 of forming a gate electrode in the recess region S160, and a step S170 of forming a drain electrode in a bottom surface of the substrate or under the low-resistance layer.

For example, as shown in FIGS. 4A to 4C, an N-type GaN layer is grown by 0.01 to 10 μm, preferably 0.05 to 0.2 μm on the substrate to form a low resistance layer (S110) The channel layer is grown by 0.01 to 0.5 탆, preferably 0.05 to 0.2 탆, to form a channel layer (S120), and then a barrier layer is formed by growing AlGaN at 0 to 100 nm, preferably 0 to 10 nm.

The low-resistance layer is made of an n-type gallium nitride (n-GaN). The low resistance layer can be formed in various ways. For example, based on at least one of metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, sputtering, and atomic layer deposition. However, in consideration of the crystallinity of the low-resistance layer, the low-resistance layer is generally fabricated by metal-organic chemical vapor deposition. TMGa as a raw material of Ga, and NH ₃ as a raw material of N are synthesized at a high temperature in a reactor to perform epitaxial growth.

The channel layer is made of gallium nitride (GaN). A two-dimensional electron gas (2DEG) is formed in the channel layer. The channel layer may also be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, etc., as well as the low resistance layer.

The barrier layer is made of aluminum gallium nitride (AlGaN), i.e., Al _x Ga _{1 - x} N. The barrier layer can also be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition or the like, as well as the channel layer or the low resistance layer.

The method for fabricating the nitride semiconductor device may further include forming a gate insulating layer on the barrier layer (not shown).

For example, the step of forming the source electrode (S140) comprises the steps of defining a source region by selectively etching the gate insulating layer, and forming the source electrode on the source region.

As another example, when the gate insulating film layer is not formed, the step of forming the source electrode (S140) forms the source electrode on the barrier layer.

After epitaxial growth, a source electrode is formed on the surface side as shown in FIG. 4D (S140). The source electrode is formed at a portion where no gate electrode is formed, and is made of metal.

The source electrode is formed of an ohmic contact. For example, the source electrode can be patterned by a lift-off process by depositing Ti / Al / Ti / Au with a thickness of 30/100/20/200 nm using an electron beam evaporator.

For example, the step of forming the gate electrode (S160) includes a step of forming a gate insulating film layer in the recess region, and a step of forming the gate electrode on the gate insulating film layer.

As another example, in the step of forming the gate electrode (S160), the gate metal layer may be formed in the recessed region without forming the gate insulating film layer.

Next, as shown in FIG. 4D, a portion where a gate electrode is to be formed is etched so that a vertical channel is formed (S150). At this time, the etching depth is made to be in contact with or more than n-GaN.

6A to 6D are views showing various forms of the recess region. 6A to 6D, the recessed region 70 may have a trench shape (FIG. 6A), a V-groove shape (FIG. 6B), a semicircular shape (Fig. 6C), and a stepped configuration (Fig. 6D).

The recess region is preferably etched so as to have a depth greater than a portion where the channel layer and the low-resistance layer are in contact with each other. The gate electrode formed on the recessed region may enlarge the depletion region near the 2DEG to provide the advantage of the threshold voltage (supply voltage) being shifted in the positive direction (or the normally-off characteristic). If only the channel layer and the barrier layer are to be removed, some channel layers may remain in the recess region during the etching process. In this case, the channel layer has a high resistance and can operate as an insulating layer. When the channel layer operates as an insulating layer, the channel formation may not be performed vertically by blocking the flow of electricity in the drain direction. Therefore, the recessed region is formed by etching a part of the low-resistance layer. However, the depth of the recessed region should not exceed 1/3 of the thickness of the low-resistance layer. When etching is performed beyond 1/3 of the thickness of the low-resistance layer, the distance between the gate and the drain electrode becomes close to each other, which may cause dielectric breakdown.

A gate electrode is formed in the etched recessed region of the barrier layer and the channel layer and a part of the low-resistance layer, as shown in Fig. 4F. The gate electrode comprises a gate metal layer made of metal. That is, as shown in FIG. 7B, the nitride semiconductor device may have a MES (Metal-Semiconductor) structure. Here, FIGS. 7A and 7B are views showing a nitride semiconductor device in a unit unit.

The gate electrode may further include a gate insulating film layer formed in the recess region. The gate insulating film layer 41 is made of at least one of silicon oxide (SiO ₂ ), hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), and silicon nitride (SiN).

The gate metal layer is formed on the gate insulating film layer. That is, as shown in FIG. 7A, the nitride semiconductor device may have a MIS (Metal-Insulator-Semiconductor) structure.

The gate insulating film layer may be formed by various methods. For example, based on at least one of metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, sputtering, and atomic layer deposition. The thickness of the gate insulating film layer is 0.1 to 300 nanometers (nm). Preferably, the gate insulating layer is deposited to a thickness of 1 to 100 nm.

Finally, as shown in FIG. 4F, a drain electrode is deposited under the low-resistance layer (S170). The drain electrode is also made to be an ohmic contact like the source electrode. If the substrate is not removed, a drain electrode may be formed on the rear surface of the substrate.

Referring to FIG. 5, a method of fabricating a nitride semiconductor device according to another embodiment includes forming a low-resistance layer on a substrate (S210), and selectively forming a channel layer on the low-resistance layer (S220 (S230) forming a barrier layer on the channel layer, forming a source electrode on the barrier layer (S240), forming a gate electrode in the recess region where the barrier layer and the channel layer are not formed (S250), and forming a drain electrode on the bottom surface of the substrate or under the low-resistance layer (S260).

The manufacturing method may further include forming a gate insulating layer on the barrier layer. The step of forming the source electrode (S240) comprises the steps of defining a source region by selectively etching the gate insulating layer, and forming the source electrode on the source region.

The step of forming the gate electrode (S250) includes the steps of forming a gate insulating film layer in the recess region, and forming the gate electrode on the gate insulating film layer. Of course, the gate metal layer may be formed without forming the gate insulating film layer.

A manufacturing method according to another embodiment selectively grows a channel layer and a barrier layer. At this time, an oxide film or a nitride film of silicon is formed in the growth inhibiting region (S220, S230).

In the case of forming the channel layer and the barrier layer by the selective growth as described above, there is no possibility that the channel formation from the source electrode to the drain electrode occurs because there is no possibility that the channel layer remains in the recessed region.

The manufacturing methods may further include a step of removing the substrate (not shown). The substrate can be removed after fabrication of the nitride semiconductor device. In this case, the final device structure may be a substrate-free structure. For example, as shown in FIG. 4E, in the case of an insulating substrate, it is necessary to remove the substrate before depositing the drain electrode. On the other hand, when the substrate is a gallium nitride substrate or the like, the substrate may be removed or not removed before the drain electrode is deposited. In this case, the drain electrode is formed not on the lower surface of the low-resistance layer but on the back surface of the substrate and has a vertical structure.

As described above, the nitride semiconductor device according to the embodiments of the present invention and its manufacturing method have advantages such as a vertical device, a wider area of the drain electrode, and a larger area of the GaN layer An electrode is formed on the lower side to reduce the chip size of the entire device. Embodiments of the present invention make it possible to reduce the element area due to an increase in current, by allowing the nitride semiconductor to grow on the n-type GaN so that the electrons flow in the vertical direction from the source to the drain, thereby maximizing the advantage of the nitride semiconductor device . Embodiments of the present invention implement a normally-off by forming a nitride semiconductor device vertically.

10: low resistance layer 20: channel layer
30: barrier layer 40: gate electrode
41: Gate insulating film layer 43: Gate metal layer
50: source electrode 60: drain electrode

Claims (19)

In the nitride semiconductor device,
A low-resistance layer formed on the substrate and made of a nitride-based semiconductor;
A channel layer formed on the low-resistance layer;
A barrier layer formed on the channel layer;
A drain electrode formed on the rear surface of the substrate and made of metal;
A source electrode formed on the barrier layer; And
And a gate electrode formed in the recessed region including the channel layer, the barrier layer, and a part of the low-resistance layer, the gate electrode being made of metal,
The nitride semiconductor device has a metal-semiconductor structure,
Wherein:
Wherein the nitride semiconductor substrate is one of a gallium nitride substrate, a silicon carbide substrate, and a silicon substrate. delete delete The method according to claim 1,
Wherein the recessed region comprises:
A trench shape, a V-groove shape, a semicircular shape, and a stepped shape. 5. The method of claim 4,
Wherein the recessed region comprises:
Resistance layer is formed so as to include at least a portion of the low-resistance layer, and the depth is an etched region that is less than 1/3 of the low-resistance layer. delete The method according to claim 1,
Wherein the two source electrodes share one gate electrode. delete The method according to any one of claims 1, 4, 5, and 7,
The low-
Type gallium nitride and has a thickness of 0.01 to 10 micrometers. The method according to any one of claims 1, 4, 5, and 7,
Wherein the channel layer comprises:
Gallium nitride, a two-dimensional electron gas channel is formed, and a thickness of the nitride semiconductor is 0.01 to 0.5 micrometer. delete delete delete delete delete delete delete delete delete

Images