JP6437381B2 - Nitride semiconductor device and manufacturing method thereof - Google Patents

Description

  The technology disclosed in this specification relates to a nitride semiconductor device and a method for manufacturing the same.

  A nitride semiconductor device including a nitride semiconductor multilayer body having a heterojunction has been developed. This nitride semiconductor device uses a two-dimensional electron gas layer formed near the heterojunction surface as a channel. In this nitride semiconductor device, a gate electrode is provided between the drain electrode and the source electrode, and the amount of current flowing between the drain electrode and the source electrode is controlled in accordance with the potential of the gate electrode.

  As disclosed in Non-Patent Document 1 and Non-Patent Document 2, in this type of nitride semiconductor device, a technique for interposing a p-type nitride semiconductor layer between a gate electrode and a nitride semiconductor stacked body has been developed. Yes. When the p-type nitride semiconductor layer is provided, when the gate electrode is grounded, the depletion layer extending from the p-type nitride semiconductor layer becomes an electron in the two-dimensional electron gas layer below the p-type nitride semiconductor layer. Can be depleted. On the other hand, when a positive potential is applied to the gate electrode, the depletion layer shrinks, a two-dimensional electron gas layer is formed below the p-type nitride semiconductor layer, and the drain electrode and the source electrode pass through the two-dimensional electron gas layer. And conduct. Thus, the nitride semiconductor device provided with the p-type nitride semiconductor layer can operate normally off.

  Further, in this type of nitride semiconductor device, the occurrence of a current collapse phenomenon in which the on-state drain current decreases during switching is a problem. The current collapse phenomenon is considered to be caused by the accumulation of electric charges at the surface level of the nitride semiconductor multilayer body or at the interface level between the nitride semiconductor multilayer body and the passivation film. Patent Document 1 discloses a technique for forming a surface layer of an i-type or n-type nitride semiconductor on a nitride semiconductor multilayer body in order to suppress a current collapse phenomenon. Since the surface layer is provided on the nitride semiconductor multilayer body, the surface state or interface state of the nitride semiconductor multilayer body is reduced, charge accumulation is suppressed, and current collapse phenomenon is suppressed.

Injun Hwang et.al., ISPSD (2012), p.41 Y. Uemoto et.al., IEEE Transaction on Electron Devices, Vol.54 (2007), p.3393

JP 2014-72258 A

  The film thickness of the surface layer formed on the nitride semiconductor stacked body needs to be thin in order to avoid a current path for gate leakage current. For this reason, the method for manufacturing a nitride semiconductor device disclosed in Patent Document 1 includes a step of forming a p-type nitride semiconductor layer on a nitride semiconductor stack, and a titanium layer on the p-type nitride semiconductor layer other than the gate formation region. A step of reacting the p-type nitride semiconductor layer and the titanium layer by heat treatment to form titanium nitride, and a step of removing the titanium nitride by wet etching. In this manufacturing method, an unreacted p-type nitride semiconductor layer is formed in a region other than the gate formation region by adjusting the heat treatment time when the titanium layer and the p-type nitride semiconductor layer are reacted to form titanium nitride. Remain. The unreacted p-type nitride semiconductor layer becomes i-type or n-type by sucking up nitrogen when titanium nitride is formed. Through these steps, a thick p-type nitride semiconductor layer is formed in the gate formation region, and a thin surface layer is formed in regions other than the gate formation region.

  However, it is difficult to form a thin surface layer with high accuracy by adjusting the heat treatment time. The present specification provides a nitride semiconductor device in which a current collapse phenomenon is suppressed and a method for manufacturing the nitride semiconductor device.

  The method for manufacturing a nitride semiconductor device disclosed in this specification includes a step of forming a p-type nitride semiconductor layer on a nitride semiconductor multilayer body having a heterojunction, and etching a part of the p-type nitride semiconductor layer. A step of exposing the nitride semiconductor multilayer body, a step of forming a surface layer of an i-type or n-type nitride semiconductor on the exposed nitride semiconductor multilayer body, and forming a gate electrode on the p-type nitride semiconductor layer And a step of forming a drain electrode on one side of the nitride semiconductor multilayer body facing the p-type nitride semiconductor layer and forming a source electrode on the other side.

  According to the above manufacturing method, the p-type nitride semiconductor layer is etched to expose the nitride semiconductor stacked body, and then the surface layer is formed. For this reason, a thin surface layer can be formed with high accuracy.

  The nitride semiconductor device disclosed in this specification includes a nitride semiconductor stacked body having a heterojunction, a drain electrode, a source electrode, a p-type nitride semiconductor layer, a surface layer of an i-type or n-type nitride semiconductor, and a gate electrode. Is provided. The drain electrode is provided on the nitride semiconductor multilayer body. The source electrode is provided on the nitride semiconductor stacked body and is arranged away from the drain electrode. The p-type nitride semiconductor layer is provided on the nitride semiconductor stacked body, and is disposed between the drain electrode and the source electrode and away from both the drain electrode and the source electrode. The surface layer is provided on the nitride semiconductor stacked body between the p-type nitride semiconductor layer and the drain electrode. The gate electrode is provided on the p-type nitride semiconductor layer.

  In one embodiment of the nitride semiconductor device disclosed in this specification, the surface layer is also provided on the p-type nitride semiconductor layer. Furthermore, the gate electrode is provided on the p-type nitride semiconductor layer via the surface layer. In the nitride semiconductor device of this embodiment, since a surface layer having a high electrical resistance value is interposed between the gate electrode and the p-type nitride semiconductor layer, gate leakage current can be suppressed.

  In another embodiment of the nitride semiconductor device disclosed in this specification, the surface layer is also provided on the p-type nitride semiconductor layer. An opening that exposes the upper surface of the p-type nitride semiconductor layer is formed in the surface layer. Further, the gate electrode is provided on the p-type nitride semiconductor layer through the opening in the surface layer. In the nitride semiconductor device of this embodiment, a layer having a high electrical resistance value is formed in the upper layer portion of the p-type nitride semiconductor layer due to processing damage when the opening is formed in the surface layer. It can be suppressed.

The principal part sectional drawing of the nitride semiconductor device of an Example is typically shown. FIG. 2 schematically shows a cross-sectional view of a main part in one process for manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of a main part in one process for manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of a main part in one process for manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of a main part in one process for manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of a main part in one process for manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of a main part in one process for manufacturing the nitride semiconductor device shown in FIG. 1. The principal part sectional drawing of the nitride semiconductor device of a modification is shown typically. FIG. 9 schematically shows a cross-sectional view of a main part of one step in manufacturing the nitride semiconductor device shown in FIG. 8. FIG. 9 schematically shows a cross-sectional view of a main part of one step in manufacturing the nitride semiconductor device shown in FIG. 8.

  The technical features disclosed in this specification will be summarized below. The items described below have technical usefulness independently.

  The method for manufacturing a nitride semiconductor device disclosed in this specification includes a step of forming a p-type nitride semiconductor layer on a nitride semiconductor multilayer body having a heterojunction, and etching a part of the p-type nitride semiconductor layer. A step of exposing the nitride semiconductor stack, a step of forming a surface layer of an i-type or n-type nitride semiconductor on the exposed nitride semiconductor stack, and a gate electrode on the p-type nitride semiconductor layer And a step of forming a drain electrode on one side of the p-type nitride semiconductor layer opposite to each other on the nitride semiconductor multilayer body and a source electrode on the other side. Good. The step of forming the gate electrode may be performed before or after the step of forming the drain electrode and the source electrode. The drain electrode and the source electrode may be formed at the same time or may be formed in separate steps. The drain electrode and the source electrode may be formed so as to be in contact with the upper surface of the nitride semiconductor multilayer body, or may be formed on the nitride semiconductor multilayer body via a surface layer.

  The step of forming the surface layer of the manufacturing method may be performed such that the surface layer is also formed on the p-type nitride semiconductor layer. In this case, the step of forming the gate electrode may be performed such that the gate electrode is formed on the p-type nitride semiconductor layer through the surface layer. In the nitride semiconductor device manufactured by this manufacturing method, since a surface layer having a high electrical resistance value is interposed between the gate electrode and the p-type nitride semiconductor layer, gate leakage current can be suppressed.

  The step of forming the surface layer of the manufacturing method may be performed such that the surface layer is also formed on the p-type nitride semiconductor layer. In this case, in the step of forming the gate electrode, an opening is formed in the surface layer formed on the p-type nitride semiconductor layer to expose the upper surface of the p-type nitride semiconductor layer, and the gate electrode passes through the opening. You may implement so that it may form on a p-type nitride semiconductor layer. In the nitride semiconductor device manufactured by this manufacturing method, a layer having a high electrical resistance value is formed in the upper layer portion of the p-type nitride semiconductor layer due to processing damage when the opening is formed in the surface layer. Leakage current can be suppressed.

  The nitride semiconductor device disclosed in this specification includes a nitride semiconductor stacked body having a heterojunction, a drain electrode, a source electrode, a p-type nitride semiconductor layer, a surface layer of an i-type or n-type nitride semiconductor, and a gate electrode. May be provided. The drain electrode is provided on the nitride semiconductor multilayer body. The source electrode is provided on the nitride semiconductor stacked body and is arranged away from the drain electrode. The drain electrode and the source electrode may be formed so as to be in contact with the upper surface of the nitride semiconductor multilayer body, or may be formed on the nitride semiconductor multilayer body via a surface layer. The p-type nitride semiconductor layer is provided on the nitride semiconductor stacked body, and is disposed between the drain electrode and the source electrode and away from both the drain electrode and the source electrode. The surface layer is provided on the nitride semiconductor stacked body between the p-type nitride semiconductor layer and the drain electrode. The gate electrode is provided on the p-type nitride semiconductor layer.

  In one embodiment of the nitride semiconductor device disclosed in this specification, the surface layer may also be provided on the p-type nitride semiconductor layer. In this case, the gate electrode may be provided on the p-type nitride semiconductor layer via the surface layer. In the nitride semiconductor device of this embodiment, since a surface layer having a high electrical resistance value is interposed between the gate electrode and the p-type nitride semiconductor layer, gate leakage current can be suppressed.

  In another embodiment of the nitride semiconductor device disclosed in this specification, the surface layer may also be provided on the p-type nitride semiconductor layer. In this case, an opening that exposes the upper surface of the p-type nitride semiconductor layer may be formed in the surface layer. Furthermore, the gate electrode may be provided on the p-type nitride semiconductor layer through the opening in the surface layer. In the nitride semiconductor device of this embodiment, a layer having a high electrical resistance value is formed in the upper layer portion of the p-type nitride semiconductor layer due to processing damage when the opening is formed in the surface layer. It can be suppressed.

In the nitride semiconductor device and the manufacturing method thereof disclosed in this specification, the nitride semiconductor multilayer body may have an electron transit layer and a barrier layer. Semiconductor material of the electron transit _{layer, In Xa Al Ya Ga 1-} Xa-Ya N (0 ≦ Xa ≦ 1,0 ≦ Ya ≦ 1,0 ≦ Xa + Ya ≦ 1) a and the semiconductor material of the barrier layer, _{an In Xb} Al _Yb Ga _1-Xb—Yb N (0 ≦ Xb ≦ 1, 0 ≦ Yb ≦ 1, 0 ≦ Xb + Yb ≦ 1), and the band gap of In _Xb Al _Yb Ga _1-Xb—Yb N is In _Xa Al _Ya It is desirable that it is larger than the band gap of Ga _{1 -Xa-Yan} . the semiconductor material of p-type nitride semiconductor layer _is an _{In Xc Al Yc Ga 1-Xc} -Yc N (0 ≦ Xc ≦ 1,0 ≦ Yc ≦ 1,0 ≦ Xc + Yc ≦ 1). The composition of the p-type nitride semiconductor layer may be the same as the composition of the barrier layer. The semiconductor material of the surface layer _{is In Xd Al Yd Ga 1-Xd} -Yd N (0 ≦ Xd ≦ 1,0 ≦ Yd ≦ 1,0 ≦ Xd + Yd ≦ 1).

  Embodiments will be described below with reference to the drawings. Constituent elements common to the embodiments are denoted by common reference numerals, and description thereof is omitted.

  As shown in FIG. 1, the nitride semiconductor device 1 is of a type called HFET (Heterostructure Field Effect Transistor) or HEMT (High Electron Mobility Transistor), and includes a substrate 12, a buffer layer 14, and a nitride semiconductor multilayer body. 16, a p-type nitride semiconductor layer 22, a surface layer 24, a passivation film 26, a drain electrode 32, a source electrode 34, and a gate electrode 36.

  As the material of the substrate 12, a material capable of crystal growth of a nitride semiconductor-based semiconductor material is used. For example, gallium nitride, sapphire, silicon carbide, or silicon is used as the material of the substrate 12.

  The buffer layer 14 is provided in contact with the upper surface of the substrate 12. For example, non-doped gallium nitride (i-GaN), non-doped aluminum nitride (i-AlN), and non-doped aluminum gallium nitride (i-AlGaN) are used as the material of the buffer layer 14. The buffer layer 14 is laminated on the substrate 12 at a low temperature by using metal organic chemical vapor deposition (MOCVD).

  The nitride semiconductor multilayer body 16 includes an electron transit layer 15 and a barrier layer 17. The electron transit layer 15 is provided in contact with the upper surface of the buffer layer 14. For example, non-doped gallium nitride (i-GaN) is used as the material of the electron transit layer 15. The electron transit layer 15 is stacked on the buffer layer 14 using a metal organic chemical vapor deposition method. The barrier layer 17 is provided in contact with the upper surface of the electron transit layer 15. For example, non-doped aluminum gallium nitride (i-AlGaN) is used as the material of the barrier layer 17. The composition ratio of aluminum in the barrier layer 17 is about 5 to 30%, and the thickness is preferably about 5 to 30 nm. The barrier layer 17 is laminated on the electron transit layer 15 using metal organic vapor phase epitaxy. The band gap of the barrier layer 17 is larger than the band gap of the electron transit layer 15. Therefore, a two-dimensional electron gas layer is formed on the heterojunction surface between the electron transit layer 15 and the barrier layer 17.

The p-type nitride semiconductor layer 22 is provided in contact with the upper surface of the barrier layer 17 and is disposed between the drain electrode 32 and the source electrode 34 and away from both the drain electrode 32 and the source electrode 34. . As an example of the material of the p-type nitride semiconductor layer 22, aluminum gallium nitride (p-AlGaN) doped with magnesium is used. In one example, the dopant concentration of magnesium in the p-type nitride semiconductor layer 22 is 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . The composition of the p-type nitride semiconductor layer 22 is the same as that of the barrier layer 17. The thickness of the p-type nitride semiconductor layer 22 is preferably about 30 to 100 nm. In one example, the aluminum composition ratio of the p-type nitride semiconductor layer 22 is about 18% and the thickness thereof is about 30 nm. The p-type nitride semiconductor layer 22 is stacked on the upper surface of the barrier layer 17 using metal organic vapor phase epitaxy.

The surface layer 24 is provided in contact with the upper surface of the barrier layer 17 between the p-type nitride semiconductor layer 22 and the drain electrode 32 and the upper surface of the barrier layer 17 between the p-type nitride semiconductor layer 22 and the source electrode 34. It has been. The surface layer 24 is further provided in contact with the side surface on the drain side, the side surface on the source side, and the upper surface of the p-type nitride semiconductor layer 22. For example, non-doped gallium nitride (i-GaN) is used as the material of the surface layer 24. The thickness of the surface layer 24 is desirably about 2 to 5 nm. In one example, the thickness of the surface layer 24 is about 2 nm. The material of the surface layer 24 may be gallium nitride (n-GaN) doped with silicon. In this case, the silicon dopant concentration of the surface layer 24 is desirably 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ in one example.

  Each of the drain electrode 32 and the source electrode 34 is provided in contact with the upper surface of the barrier layer 17 through the openings 24 a and 24 b of the surface layer 24. The drain electrode 32 and the source electrode 34 are disposed at positions facing each other with the p-type nitride semiconductor layer 22 interposed therebetween. The drain electrode 32 is preferably made of a material capable of making ohmic contact with a nitride semiconductor material. As an example of the material of the drain electrode 32, a laminated electrode of titanium and aluminum is used. It is desirable that the source electrode 34 be made of a material that can make ohmic contact with the nitride semiconductor material. As a material of the source electrode 34, for example, a laminated electrode of titanium and aluminum is used. Accordingly, each of the drain electrode 32 and the source electrode 34 is configured to be in ohmic contact with the two-dimensional electron gas layer formed on the heterojunction surface between the electron transit layer 15 and the barrier layer 17. Each of the drain electrode 32 and the source electrode 34 is laminated on the upper surface of the barrier layer 17 using an electron beam evaporation technique. In this example, since each of the drain electrode 32 and the source electrode 34 passes through the openings 24a and 24b of the surface layer 24 and is in contact with the upper surface of the barrier layer 17, the contact resistance is low. Instead of this example, each of the drain electrode 32 and the source electrode 34 may be formed on the barrier layer 17 via the surface layer 24.

  The gate electrode 36 is provided on the p-type nitride semiconductor layer 22 via the surface layer 24. In other words, the gate electrode 36 and the p-type nitride semiconductor layer 22 are separated by the surface layer 24. The material of the gate electrode 36 is preferably a material that can make ohmic contact with a nitride semiconductor material. As an example of the material of the gate electrode 36, a laminated electrode of nickel and gold is used. Thereby, the gate electrode 36 is configured to be in ohmic contact with the surface layer 24. The gate electrode 36 is laminated on the upper surface of the surface layer 24 using an electron beam evaporation technique. The material of the gate electrode 36 may be a material that can make a Schottky contact with a nitride semiconductor material.

The passivation film 26 is provided in contact with the upper surface of the surface layer 24. The passivation film 26 covers regions other than these electrodes so that the drain electrode 32, the source electrode 34, and the gate electrode 36 are exposed. For example, silicon oxide (SiO ₂ ) is used as the material of the passivation film 26. The passivation film 26 is coated on the upper surface of the surface layer 24 using a plasma CVD technique. The material of the passivation film 26 is silicon nitride (SiN) formed using a plasma CVD technique, aluminum oxide (Al ₂ O ₃ ) formed using an atomic layer stacking method, sputtering, or MOCVD. It may be aluminum nitride (AlN) formed using technology.

  Next, the operation of the nitride semiconductor device 1 will be described. The nitride semiconductor device 1 is used with a positive potential applied to the drain electrode 32 and a ground potential applied to the source electrode 34. When the gate electrode 36 is grounded, a depletion layer extending from the p-type nitride semiconductor layer 22 is two-dimensional near the heterojunction surface of the electron transit layer 15 and the barrier layer 17 below the p-type nitride semiconductor layer 22. The electrons in the electron gas layer are depleted. For this reason, the current path between the drain electrode 32 and the source electrode 34 is cut off at the heterojunction surface where the p-type nitride semiconductor layer 22 faces, and the nitride semiconductor device 1 is turned off.

  When a positive potential is applied to the gate electrode 36, the depletion layer extending from the p-type nitride semiconductor layer 22 is reduced, and the electron transit layer 15 and the barrier layer 17 are also below the p-type nitride semiconductor layer 22. A two-dimensional electron gas layer is generated in the vicinity of the heterojunction surface. Electrons injected from the source electrode 34 flow to the drain electrode 32 through the two-dimensional electron gas layer, and the nitride semiconductor device 1 is turned on. Thus, nitride semiconductor device 1 operates normally off.

  In the nitride semiconductor device 1, the surface layer 24 is provided between the gate electrode 36 and the drain electrode 32. The surface layer 24 is provided in contact with the upper surface of the barrier layer 17 and is interposed between the barrier layer 17 and the passivation film 26. As will be described later in the manufacturing method, when the p-type nitride semiconductor layer 22 is processed by dry etching, processing damage remains on the upper surface of the barrier layer 17. For example, when the barrier layer 17 in which such processing damage remains is in contact with the passivation film 26, the interface level between the barrier layer 17 and the passivation film 26 increases, and a current is generated by the charge accumulated in the interface state. Collapse phenomenon will occur. However, in the nitride semiconductor device 1, since the high-quality surface layer 24 with few crystal defects is provided between the barrier layer 17 and the passivation film 26, such interface states are reduced and charge accumulation is reduced. The current collapse phenomenon is suppressed. In order to suppress current collapse, the semiconductor material of the surface layer 24 is preferably GaN. On the other hand, when the semiconductor material of the surface layer 24 contains aluminum or indium, particularly when the surface layer 24 contains more aluminum than the aluminum contained in the barrier layer 17, the electron transit layer 15 and the barrier are provided below the surface layer 24. The electron density of the two-dimensional electron gas layer between the layers 17 increases, and the on-resistance decreases. The semiconductor material of the surface layer 24 can be adjusted according to desired characteristics.

  In the nitride semiconductor device 1, a parasitic diode exists at the junction between the p-type nitride semiconductor layer 22 and the barrier layer 17. Therefore, when a positive potential is applied to the gate electrode 36 when the nitride semiconductor device 1 is turned on, the parasitic diode is forward-biased. However, in the nitride semiconductor device 1, the surface layer 24 is interposed between the gate electrode 36 and the p-type nitride semiconductor layer 22. Since the electrical resistance value of the surface layer 24 is large, gate leakage current via the parasitic diode is suppressed, and increase in power consumption is suppressed.

  Next, a method for manufacturing the nitride semiconductor device 1 will be described. First, as shown in FIG. 2, the buffer layer 14, the electron transit layer 15, and the barrier layer 17 are stacked on the substrate 12. The buffer layer 14, the electron transit layer 15, and the barrier layer 17 are sequentially grown on the substrate 12 using a metal organic vapor phase epitaxy method.

  Next, as shown in FIG. 3, a p-type nitride semiconductor layer 22 is crystal-grown on the upper surface of the barrier layer 17 using metal organic vapor phase epitaxy.

  Next, as shown in FIG. 4, the barrier layer 17 is exposed by removing a part of the p-type nitride semiconductor layer 22 using a dry etching technique.

  Next, as shown in FIG. 5, the surface layer 24 is crystal-grown on the upper surface of the barrier layer 17 using metal organic vapor phase epitaxy. The surface layer 24 is also formed on the side surface and the upper surface of the p-type nitride semiconductor layer 22.

  Next, as shown in FIG. 6, openings 24a and 24b are formed in a part of the surface layer 24 by using a dry etching technique. The upper surface of the barrier layer 17 is exposed at the openings 24 a and 24 b of the surface layer 24.

  Next, as shown in FIG. 7, the drain electrode 32 and the source electrode 34 are formed on the upper surface of the barrier layer 17 exposed to the openings 24 a and 24 b of the surface layer 24 by using an electron beam evaporation technique. Next, the gate electrode 36 is formed on the surface layer 24 in a range where the p-type nitride semiconductor layer 22 is provided using an electron beam evaporation technique. Finally, when the passivation film 26 is formed, the nitride semiconductor device 1 shown in FIG. 1 is completed.

  The manufacturing method is characterized in that the surface layer 24 is formed after the p-type nitride semiconductor layer 22 is dry-etched. In order to suppress the current collapse phenomenon, the surface layer 24 may be formed on the barrier layer 17 between the gate electrode 36 and the drain electrode 32. Therefore, for example, a manufacturing method in which the surface layer 24 and the p-type nitride semiconductor layer 22 are formed in this order and then only the p-type nitride semiconductor layer 22 is dry-etched to leave the surface layer 24 is also conceivable. Yeah. However, in this manufacturing method, it is necessary to dry-etch only the p-type nitride semiconductor layer 22 while leaving the thin surface layer 24, and high processing accuracy is required. For example, if the surface layer 24 is also removed by dry etching, the current collapse phenomenon cannot be suppressed. On the other hand, in the above manufacturing method, since the surface layer 24 is formed after the p-type nitride semiconductor layer 22 is dry-etched, the surface layer 24 having a desired film thickness can be formed with high accuracy.

  FIG. 8 shows a modified nitride semiconductor device 2. In the nitride semiconductor device 2, an opening 24 c is formed in the surface layer 24 on the p-type nitride semiconductor layer 22, and the gate electrode 36 passes through the opening 24 c and contacts the upper surface of the p-type nitride semiconductor layer 22. Is provided.

  Next, a method for manufacturing the nitride semiconductor device 2 will be described. The manufacturing process shown in FIG. 5 is the same as the manufacturing method of nitride semiconductor device 1.

  Next, as shown in FIG. 9, openings 24a, 24b, and 24c are formed in a part of the surface layer 24 by using a dry etching technique. The upper surface of the barrier layer 17 is exposed at the openings 24 a and 24 b of the surface layer 24. The upper surface of the p-type nitride semiconductor layer 22 is exposed in the opening 24 c of the surface layer 24.

  Next, as shown in FIG. 10, the drain electrode 32 and the source electrode 34 are formed on the upper surface of the barrier layer 17 exposed to the openings 24 a and 24 b of the surface layer 24 by using an electron beam evaporation technique. Next, the gate electrode 36 is formed on the upper surface of the p-type nitride semiconductor layer 22 exposed in the opening 24c of the surface layer 24 by using an electron beam evaporation technique. Finally, when the passivation film 26 is formed, the nitride semiconductor device 2 shown in FIG. 8 is completed.

  The manufacturing method is characterized in that an opening 24c is formed in a part of the surface layer 24 in a range where the p-type nitride semiconductor layer 22 is provided to expose the upper surface of the p-type nitride semiconductor layer 22. When the opening 24c is formed in a part of the surface layer 24, the processing damage of the dry etching process remains on the upper surface of the p-type nitride semiconductor layer 22, and the electric resistance value of the upper layer portion of the p-type nitride semiconductor layer 22 is Increase resistance. For this reason, when the nitride semiconductor device 2 is turned on, the gate leakage current through the parasitic diode existing at the junction between the p-type nitride semiconductor layer 22 and the barrier layer 17 is suppressed, and the increase in power consumption is suppressed. .

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1: nitride semiconductor device, 12: substrate, 14: buffer layer, 15: electron transit layer, 16: nitride semiconductor laminate, 17: barrier layer, 22: p-type nitride semiconductor layer, 24: surface layer, 26 : Passivation film, 32: Drain electrode, 34: Source electrode, 36: Gate electrode

Claims (8)

A method for manufacturing a nitride semiconductor device, comprising:
Forming a p-type nitride semiconductor layer on the nitride semiconductor stack having a heterojunction;
Etching a portion of the p-type nitride semiconductor layer to expose the nitride semiconductor stack;
Forming an i-type or n-type nitride semiconductor surface layer on the exposed nitride semiconductor laminate;
Forming a gate electrode on the p-type nitride semiconductor layer;
Forming a drain electrode on one side of the nitride semiconductor laminate and facing the p-type nitride semiconductor layer therebetween, and forming a source electrode on the other;
Forming a passivation film on the surface layer in a state in which the gate electrode, the drain electrode, and the source electrode are exposed . A method for manufacturing a nitride semiconductor device, comprising:
Forming a p-type nitride semiconductor layer on the nitride semiconductor stack having a heterojunction;
Etching a portion of the p-type nitride semiconductor layer to expose the nitride semiconductor stack;
Forming an i-type or n-type nitride semiconductor surface layer on the exposed nitride semiconductor laminate;
Forming a gate electrode on the p-type nitride semiconductor layer;
Forming a drain electrode on one side of the nitride semiconductor stacked body and facing the p-type nitride semiconductor layer, and forming a source electrode on the other side,
The step of forming the surface layer is performed such that the surface layer is also formed on the p-type nitride semiconductor layer,
Step, the gate electrode is Ru is performed as formed on the p-type nitride semiconductor layer through the surface layer, manufacturing method of forming the gate electrode. The step of forming the surface layer is performed such that the surface layer is also formed on the p-type nitride semiconductor layer,
In the step of forming the gate electrode, an opening is formed in the surface layer formed on the p-type nitride semiconductor layer to expose the p-type nitride semiconductor layer, and the gate electrode passes through the opening. The manufacturing method according to claim 1, wherein the manufacturing method is performed so as to be formed on the p-type nitride semiconductor layer. The manufacturing method according to claim 2 , further comprising: forming a passivation film on the surface layer in a state where the gate electrode, the drain electrode, and the source electrode are exposed. A nitride semiconductor device comprising:
A nitride semiconductor laminate having a heterojunction; and
A drain electrode provided on the nitride semiconductor laminate;
A source electrode provided on the nitride semiconductor multilayer body and disposed away from the drain electrode;
A p-type nitride semiconductor layer provided on the nitride semiconductor stacked body and disposed between the drain electrode and the source electrode and apart from both the drain electrode and the source electrode;
A surface layer of an i-type or n-type nitride semiconductor provided on the nitride semiconductor stack between the p-type nitride semiconductor layer and the drain electrode;
A gate electrode provided on the p-type nitride semiconductor layer,
The surface layer is also provided on the p-type nitride semiconductor layer;
The nitride semiconductor device, wherein the gate electrode is provided on the p-type nitride semiconductor layer via the surface layer. A nitride semiconductor device comprising:
A nitride semiconductor laminate having a heterojunction; and
A drain electrode provided on the nitride semiconductor laminate;
A source electrode provided on the nitride semiconductor multilayer body and disposed away from the drain electrode;
A p-type nitride semiconductor layer provided on the nitride semiconductor stacked body and disposed between the drain electrode and the source electrode and apart from both the drain electrode and the source electrode;
A surface layer of an i-type or n-type nitride semiconductor provided on the nitride semiconductor stack between the p-type nitride semiconductor layer and the drain electrode;
A gate electrode provided on the p-type nitride semiconductor layer;
A passivation film provided on the surface layer in a state where the gate electrode, the drain electrode, and the source electrode are exposed ,
The surface layer is also provided on the p-type nitride semiconductor layer;
In the surface layer, an opening exposing the upper surface of the p-type nitride semiconductor layer is formed,
The nitride semiconductor device, wherein the gate electrode is provided on the p-type nitride semiconductor layer through the opening of the surface layer. The nitride semiconductor device according to claim 5 , further comprising a passivation film provided on the surface layer in a state where the gate electrode, the drain electrode, and the source electrode are exposed. A method for manufacturing a nitride semiconductor device, comprising:
Forming a p-type nitride semiconductor layer on the nitride semiconductor stack having a heterojunction;
Etching a portion of the p-type nitride semiconductor layer to expose the nitride semiconductor stack;
Forming an i-type or n-type nitride semiconductor surface layer on the exposed nitride semiconductor laminate;
Forming a gate electrode on the p-type nitride semiconductor layer;
Forming a drain electrode on one side of the nitride semiconductor stacked body and facing the p-type nitride semiconductor layer, and forming a source electrode on the other side,
The step of forming the surface layer is performed such that the surface layer is also formed on the p-type nitride semiconductor layer,
The step of forming the gate electrode is carried out such that the gate electrode is formed on the p-type nitride semiconductor layer via the surface layer.

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