JP5638225B2 - Heterojunction field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a structure of a heterojunction field effect transistor made of a semiconductor containing nitride and a method for manufacturing the same.

  In a conventional heterojunction field effect transistor (HFET) made of a semiconductor containing nitride, in a structure in which a gate electrode is formed directly on the semiconductor surface, a drain current is large when operated by applying a pulse voltage to the gate electrode. A phenomenon (current collapse) that decreases is generated, and as a result, when an actual high frequency operation is performed, the output and efficiency that can be predicted from the DC characteristics are greatly reduced. Since current collapse is caused by trap levels formed on the semiconductor surface, to suppress this, it is effective to keep the gate electrode / semiconductor interface where the electric field is most strongly applied away from the semiconductor surface. A recess gate structure in which a gate electrode is formed after etching only a region to be formed is desirable.

  However, in order to apply the recess gate structure, it is necessary to etch the etching depth of the semiconductor layer directly under the gate electrode with good controllability, and it is difficult to control only by the etching rate. As a countermeasure, for example, in the case of a heterojunction FET using an AlGaN / GaN heterostructure, a GaN cap layer having an etching depth equal to the etching depth is formed on the outermost surface to obtain a GaN / AlGaN / GaN structure, and etching of GaN and AlGaN. A technique of selectively etching only the GaN cap layer using the difference in rate is employed. As described above, in order to suppress the current collapse, it is necessary to move the gate electrode end where the electric field is concentrated from the trap level formed on the semiconductor surface, and thus a remarkable improvement can be obtained with a deep recess structure. For example, a heterojunction FET made of a nitride semiconductor described in Non-Patent Document 1 corresponds to the above structure.

IEEE Electron Device Letters, vol.29, p303, 2008

  As described in Non-Patent Document 1, when a deep recessed gate structure is applied to a heterojunction FET made of a nitride semiconductor to suppress current collapse, the effect of polarization of the AlGaN barrier layer does not reach the vicinity of the surface, The n-type impurity present in the nitride semiconductor layer in which the recess is formed is activated to induce electrons and increase the gate leakage current.

  The present invention has been made to prevent the above-described characteristic deterioration, and an object thereof is to provide a heterojunction FET having a recessed gate structure made of a nitride semiconductor and suppressing the increase in gate leakage current, and a method for manufacturing the same. To do.

The heterojunction field effect transistor of the present invention is a heterojunction field effect transistor made of a nitride semiconductor, and includes a barrier layer, a cap layer provided on the barrier layer, and a source electrode and a drain provided separately from each other. and electrodes, provided so as to bury the lower the cap layer on the cap layer between the source electrode and the drain electrode, and a gate electrode thereon overhangs at least the drain electrode side, of the gate electrode and the drain electrode of the second region is between the first region and the gate electrode and the source electrode is between at least a cap layer odor Te preparative wrench first region is formed, a trench in the first region, a gate electrode and its end single trench der formed aligned with the end of the overhanging upper portion of the end and the drain electrode Ru.

Furthermore, the manufacturing method of the heterojunction field-effect transistor of the present invention is a method for manufacturing a heterojunction field effect transistor made of a nitride semiconductor, forming a cap layer on the barrier layer, the cap layer gate Forming a source electrode and a drain electrode on both sides of a region where an electrode is to be formed; forming a first trench in a region where a gate electrode of a cap layer is to be formed; and forming a gate electrode in the first trench Forming a second trench by etching the cap layer using the gate electrode, the drain electrode, and the source electrode as a mask.

The heterojunction field effect transistor of the present invention is a heterojunction field effect transistor made of a nitride semiconductor, and includes a barrier layer, a cap layer provided on the barrier layer, and a source electrode and a drain provided separately from each other. and electrodes, provided so as to bury the lower the cap layer on the cap layer between the source electrode and the drain electrode, and a gate electrode thereon overhangs at least the drain electrode side, of the gate electrode and the drain electrode of the second region is between the first region and the gate electrode and the source electrode is between at least a cap layer odor Te preparative wrench first region is formed, a trench in the first region, a gate electrode and its end single trench der formed aligned with the end of the overhanging upper portion of the end and the drain electrode Ru. The trench provided in the cap layer physically blocks the path through which the gate leakage current flows, thereby reducing the gate leakage current in the heterojunction field effect transistor having a recessed gate structure.

Furthermore, the manufacturing method of the heterojunction field-effect transistor of the present invention is a method for manufacturing a heterojunction field effect transistor made of a nitride semiconductor, forming a cap layer on the barrier layer, the cap layer gate Forming a source electrode and a drain electrode on both sides of a region where an electrode is to be formed; forming a first trench in a region where a gate electrode of a cap layer is to be formed; and forming a gate electrode in the first trench Forming a second trench by etching the cap layer using the gate electrode, the drain electrode, and the source electrode as a mask. Since it is not necessary to form a pattern with a resist mask in forming the second trench, the second trench can be easily formed.

It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is the figure which showed the electrical property of the heterojunction FET of a normal recessed gate structure. It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is sectional drawing which shows the structure of the heterojunction FET of this invention. It is sectional drawing which shows the manufacturing process of the heterojunction FET of this invention. It is sectional drawing which shows the manufacturing process of the heterojunction FET of this invention. It is sectional drawing which shows the manufacturing process of the heterojunction FET of this invention. It is sectional drawing which shows the manufacturing process of the heterojunction FET of this invention. It is sectional drawing which shows the manufacturing process of the heterojunction FET of this invention. It is sectional drawing which shows the manufacturing process of the heterojunction FET of this invention. It is sectional drawing which shows the manufacturing process of the heterojunction FET of this invention.

(Embodiment 1)
<Configuration>
FIG. 1 shows an example of the structure of a heterojunction FET made of a nitride semiconductor according to the first embodiment. The heterojunction FET according to the first embodiment includes a semi-insulating SiC substrate 1, a buffer layer 2 formed on the SiC substrate 1, a channel layer 3 made of GaN formed on the buffer layer 2, and a channel layer. 3, a barrier layer 4 made of Al _0.28 Ga _0.72 N formed on 3, a gate electrode 10 made of Ni / Au formed on the barrier layer 4, and a cap layer 5 made of GaN.

  Furthermore, the heterojunction FET of the present embodiment is provided with a drain electrode 8 and a source electrode 9 made of Ti / Nb / Pt on both sides of the gate electrode 10, and below the region where the drain electrode 8 and the source electrode 9 are formed. Includes Si implanted regions 6 and 7 doped with Si as an n-type impurity to obtain an ohmic contact.

  Further, a trench structure in which the GaN cap layer 5 is removed is formed between the drain electrode 8 and the gate electrode 10 (first region) and between the source electrode 9 and the gate electrode 10 (second region), respectively. The surface of the GaN cap layer 5 is covered with a surface protective film 11. Here, the trench only needs to be formed at least at one location between the drain electrode 8 and the gate electrode 10. For example, a plurality of trench structures may be formed between the drain electrode 8 and the gate electrode 10. The same applies to the trench structure between the gate electrode 10 and the source electrode 9.

  Further, it is not always necessary to form a trench between the source electrode 9 and the gate electrode 10, and as shown in FIG. 4, a trench is formed only between the drain electrode 8 and the gate electrode 10 to which a larger voltage is applied during transistor operation. If so, it is effective in reducing the gate leakage current.

  That is, the heterojunction FET of the present embodiment is a heterojunction FET made of a nitride semiconductor, and the barrier layer 4, the cap layer 5 provided on the barrier layer 4, and the lower part thereof is buried in the cap layer 5. Thus, the gate electrode 10 provided on the cap layer 5, and the source electrode 9 and the drain electrode 8 provided separately on both sides of the gate electrode 10, respectively, between the gate electrode 10 and the drain electrode 8 are provided. Among the first region and the second region between the gate electrode 10 and the source electrode 9, at least one trench is formed in the cap layer 5 in the first region. By adopting such a structure, the trench structure physically cuts off the path through which the gate leakage current transmitted through the GaN cap layer 5 flows, so that the film thickness of the GaN cap layer 5 is increased in order to suppress current collapse, That is, even when a deep recess gate structure is used, the gate leakage current can be reduced.

  Alternatively, the trench of the GaN cap layer 5 is formed in both the first region and the second region. Even with such a structure, the trench structure physically cuts off the path through which the gate leakage current transmitted through the GaN cap layer 5 flows, so that the film thickness of the GaN cap layer 5 is increased, that is, deep to suppress current collapse. Even in the case of the recess gate structure, the gate leakage current can be reduced and the current collapse can be suppressed.

  The above structure is an example showing a cross section of the heterojunction FET of the present embodiment. However, in view of the role of the trench structure, the cross section similar to that shown in FIG. It is desirable that In this case, a trench structure having a length equivalent to the length in the depth direction of the drain electrode 8 and the source electrode 9 is formed. However, even if the trench structure is longer than the length of the drain electrode 8 and the source electrode 9 in the depth direction, the effect of the present invention is exhibited.

<GaN cap layer>
Next, the film thickness of the GaN cap layer will be considered. FIG. 2 shows the magnitude of the gate leakage current with respect to the change in the thickness of the cap layer and the strength of the electric field applied to the end of the gate electrode on the drain side in a normal junction gate heterojunction FET without forming a trench. ing.

  First, the magnitude of the gate leakage current is obtained by performing fitting by the logical calculation described below for the points actually measured with four types of cap film thicknesses. That is, 1) The carrier concentration on the semiconductor surface side is obtained using the Poisson equation. 2) The probability of tunneling the depletion layer formed by the determined concentration of electrons is determined by WKB (Wentzel-Kramers-Brillouin) approximation to the Schottky potential. 3) Multiply the obtained tunnel probability by the free electron concentration of the gate metal to obtain the tunnel current value for tunneling in the semiconductor. 4) The gate leakage current value in the case where the cap layer is not formed is obtained from the actual measurement value assuming that the current value is caused by factors other than the tunnel. 5) Superimpose the tunnel current value obtained in 3) on the current value obtained in 4) to obtain the total gate leak current.

  As a result of the fitting by the above theoretical calculation, the theoretical value almost coincides with the actually measured value, and the magnitude of the gate leakage current can be estimated from this fitting curve.

  Next, current collapse increases or decreases depending on the magnitude of the electric field at the drain side tip of the gate electrode where the electric field is most concentrated during transistor operation, so the electric field at the drain side tip of the gate electrode is used as an index of the magnitude of current collapse. We will use it. The electric field at the drain side tip of the gate electrode was obtained by solving the Poisson equation. As a result, it was found that the electric field at the drain side tip of the gate electrode decreases exponentially as the thickness of the cap layer increases.

  Looking at the dependency on the film thickness of the cap layer with respect to the above two types of parameters, the effect of improvement is greater as the cap film thickness increases with respect to current collapse. On the other hand, regarding the gate leakage current, the thickness of the cap layer hardly flows up to 27 nm and increases by about two orders of magnitude between 28 nm and 35 nm. Thereafter, the gate leakage current is saturated at a film thickness of 36 nm or more and does not increase any more.

  Since the gate leakage current increases by an order of magnitude when the thickness of the cap layer is 30 nm, in this embodiment, if the thickness of the cap layer 5 is 30 nm or more, a great effect of preventing an increase in the gate leakage current can be obtained. .

<Modification>
In FIG. 1, the trench formed in the GaN cap layer 5 completely removes the GaN cap layer 5 until the barrier layer 4 is exposed. However, the thickness of 28 nm or less to which the polarization effect of AlGaN forming the barrier layer 4 is affected. Then, even if the cap layer 5 remains, induction of electrons does not occur and the gate leakage current does not increase. Therefore, as shown in FIG. 3, it is sufficient that the trench is formed so that the GaN cap layer 5 remaining on the barrier layer 4 is 28 nm or less. From the viewpoint of suppressing current collapse, the cap layer 5 is preferably left at the bottom of the trench. The same applies when a trench is formed only in the cap layer 5 between the drain electrode 8 and the gate electrode 10 shown in FIG. 4, and the cap layer 5 of 28 nm or less may be left at the bottom of the trench as shown in FIG. .

  That is, the trench is formed so as to leave the cap layer 5 of 28 nm or less at the bottom. As a result, current collapse can be suppressed while reducing gate leakage current.

Further, when the band gaps of the channel layer 3, the barrier layer 4 and the cap layer 5 are B ₃ , B ₄ and B ₅ , respectively, if these are in the relationship of B ₃ <B ₄ and B ₅ <B ₄ , Sufficient to operate the junction FET. Therefore, as described above, the channel layer 3 and the cap layer 5 are not necessarily made of GaN, and the barrier layer 4 is not necessarily made of Al _0.28 Ga _0.72 N. N of Al, Ga, and N having different constituent compositions is used. What is necessary is just to be comprised with the compound semiconductor which consists of at least 2 element containing. For example, if the compound semiconductors constituting the channel layer 3, the barrier layer 4, and the cap layer 5 are Al _x Ga _1-x N, Al _y Ga _1-y N, and Al _z Ga _1-z N, respectively, 0 ≦ x < What is necessary is just to be comprised with the compound semiconductor which satisfy | fills the relationship of 1, 0 <= y <1, 0 <= z <1, x <y _, z <y.

  Furthermore, it is not necessary to be composed of a compound composed of at least two elements including N out of Al, Ga, and N. For example, it is composed of a compound semiconductor composed of at least two elements including N among In, Al, Ga, and N. May be.

  However, when the channel layer 3, the barrier layer 4, and the cap layer 5 are composed of a compound semiconductor composed of at least two elements including N among Al, Ga, and N, a large polarization effect is generated in the barrier layer 4. A high-concentration two-dimensional electron gas can be generated on the barrier layer 4 side of the channel layer 3. Therefore, it is advantageous for increasing the current and further increasing the output of the transistor, which is a more preferable structure.

The heterojunction FET has a higher breakdown voltage as the dielectric breakdown electric field of the semiconductor material used for the channel layer 3 is higher. Since Al _x Ga _1-x N is higher as the band gap is large dielectric breakdown field having a high Al composition, if the channel layer 3 as described above consist of Al _x Ga _1-x N, more high Al composition (Where x is close to 1) is preferred. In addition, since the gate leakage current flowing from the gate electrode 9 to the hetero interface through the barrier layer 4 is suppressed as the band gap of the semiconductor material used for the barrier layer 4 is larger, Al _y Ga _1-y used as the barrier layer 4. Similarly, it is preferable that N has a higher Al composition.

  Further, the channel layer 3, the barrier layer 4, and the cap layer 5 do not necessarily have a single-layer structure with the same composition, and the In composition, the Al composition, and the Ga composition satisfy the above-described band gap conditions. It may vary spatially or may be a multilayer film consisting of several different layers. These layers may contain n-type and p-type impurities.

  The semi-insulating SiC substrate 1 may be Si, sapphire, GaN, AlN, or the like. When GaN is used for the substrate 1, the channel layer 3, the barrier layer 4, etc. can be formed without forming the buffer layer 2. Therefore, it is not necessary to form the buffer layer 20 on the substrate 1, and it is not necessary to form it.

  1 and 3 to 5, the drain electrode 8 and the source electrode 9 are formed on the Si implantation regions 6 and 7, respectively, and these electrodes are generated on the channel layer 3 on the barrier layer 4 side. If the two-dimensional electron gas 12 and the ohmic contact are formed, the Si implantation regions 6 and 7 do not necessarily have to be present under the electrodes. For example, the drain electrode 8 and the source electrode 9 may be in contact with the surface of the barrier layer 4 as shown in FIG. 6, or may be in contact with the surface of the channel layer 3 as shown in FIG. However, the resistance between the two-dimensional electron gas 12 generated on the barrier layer 4 side of the channel layer 3 and the source / drain electrode can be reduced when the Si injection regions 6 and 7 are formed under the electrodes 8 and 9. Therefore, it is advantageous for increasing the current and output of the transistor, and can be said to be a more preferable structure. Note that it is not always necessary to implant Si, and it is a condition that an n-type impurity is doped at a high concentration, and a material that forms an n-type impurity level in the nitride semiconductor (O, C, N vacancy). It is only necessary that the hole or the like is doped.

  Further, the source electrode 9 and the drain electrode 8 are not necessarily made of Ti / Al, and metals such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, and W can be obtained if ohmic characteristics are obtained. Alternatively, it may be formed of a multilayer film composed of these.

The gate electrode 10 does not necessarily have a T-shaped cross section, and may be rectangular, trapezoidal, or Y-shaped. Furthermore, the material does not necessarily need to be Ni / Au, metal such as Ti, Al, Pt, Au, Ni and Pd, silicide such as IrSi, PtSi and NiSi ₂ , nitride metal such as TiN and WN, or these You may form with the multilayer film comprised from these.

  In the structure of the gate electrode 10 shown in FIG. 1, at least one of Al, Ga, Si, Hf, and Ti is formed between the flange of the T-type gate electrode 10 and the cap layer 5 or on the surface protective film 11. A structure as shown in FIG. 8 in which an insulating film 13 made of oxide, nitride, oxynitride or the like of more than one kind of atoms may be formed. With such a structure, the electric field concentrated on the edge portion of the gate electrode 10 on the drain electrode 8 side during high voltage operation can be relaxed, and current collapse can be suppressed and the breakdown voltage can be increased. Furthermore, by forming the insulating film 13 only on the lower side of the gate electrode 10 as shown in FIG. 9, the capacitance generated between the source electrode 9 and the gate electrode 10 or between the gate electrode 10 and the drain electrode 8 can be reduced. The gain and efficiency at the time of high frequency operation can be improved.

  The width of the trench formed in the cap layer 5 is not particularly limited, and as long as the cap layer 5 is in close contact with the side surface of the gate electrode 10 on the drain side for the purpose of suppressing current collapse, FIG. As shown in FIG. 6, any width trench may be used. Further, as shown in FIG. 10, it is not necessary to cover the entire surface of the cap layer 5 with the surface protective film 11, and it is sufficient that the surface protective film 11 is formed so as to cover at least the exposed barrier layer 4.

  Since the width of the trench is arbitrary, a trench as shown in FIG. 11 may be formed in the cap layer 5. FIG. 12 shows the structure of FIG. 11 in which the cap layer 5 is left at 28 nm or less at the bottom of the trench.

  That is, the trench in the first region, which is a region between the gate electrode 10 and the drain electrode 8, is a single trench formed with its end portion aligned with the end portions of the gate electrode and the drain electrode 8. With such a structure, trenches can be formed by performing self-aligned dry etching using the gate electrode 10 and the drain electrode 8 as a mask, and the process of forming a resist mask is omitted, thus improving the simplicity of the process. effective.

  In addition, the trench in the second region, which is a region between the gate electrode 10 and the source electrode 9, is a single trench formed with its ends aligned with the ends of the gate electrode 10 and the source electrode 9. With such a structure, trenches can be formed by performing self-aligned dry etching using the gate electrode 10 and the source electrode 9 as a mask, and the process of forming a resist mask is omitted, which is effective in improving process simplicity. There is.

  However, when a trench is formed by such a process, a part of the Si implantation region 7 that forms an ohmic contact on the source electrode 9 side may be removed, and the access resistance during transistor operation increases. The evil that it will end up is considered.

  Therefore, in order to avoid the adverse effect of increasing the access resistance, a structure in which the Si implantation region 7 on the source electrode 9 side and the source electrode 9 are brought close to the gate electrode 10 as shown in FIG.

  Note that the various modifications described above do not have to be individually adopted, and may be configured by combining them.

  Although only the minimum necessary elements that operate as transistors are described above, the heterojunction FET of this embodiment is finally used as a device in a structure in which wirings, via holes, and the like are formed.

<Manufacturing process>
14 to 20 are views showing a manufacturing process of the heterojunction FET of the present embodiment. In these drawings, the components given the same reference numerals as those in FIGS. 1 and 3 to 13 indicate the same or corresponding components.

First, by applying an epitaxial growth method such as MOCVD or MBE on the semi-insulating SiC substrate 1, the buffer layer 2, the channel layer 3 made of GaN, the barrier layer 4 made of Al _0.28 Ga _0.72 N, and made of GaN. The cap layers 5 are epitaxially grown sequentially from the bottom (FIG. 14). When the channel layer 3, the barrier layer 4, and the cap layer 5 are grown, trimethylammonium, trimethylgallium, trimethylindium, ammonia, which is a nitride semiconductor source gas, or silane, which is an n-type dopant source gas, is used. By adjusting the pressure, flow rate, temperature, and introduction time, the channel layer 3, the barrier layer 4, and the cap layer 5 can be formed to have a desired composition, film thickness, and doping concentration.

Next, using a resist pattern or the like as a mask 14, Si is implanted into a desired region directly below the drain electrode 8 and the source electrode 9 by an ion implantation method or the like. The dose is 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ^−2. The Si implantation regions 6 and 7 are formed by introducing the implantation energy at 10 to 1000 keV. However, what is implanted here may be an n-type impurity in the nitride semiconductor, and may not be Si (FIG. 15).

  After removing the mask 14, for example, a drain electrode 8 made of a metal such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, W, Pt, or a multilayer film composed of these metals. A source electrode 9 is deposited by vapor deposition or sputtering, and formed by lift-off or the like (FIG. 16).

Next, using the resist pattern or the like as a mask 15, a predetermined region of the cap layer 5 is removed by a dry etching method using Cl ₂ or the like to form a trench (second trench) (FIG. 17). Here, if the etching time and the gas flow rate are adjusted to a desired etching depth, a heterojunction FET having the structure shown in FIGS. 3, 5, and 11 that leaves the cap layer 5 of 28 nm or less at the bottom of the trench can be manufactured.

  That is, the second trench is formed leaving the cap layer 5 of 28 nm or less at the bottom. As a result, current collapse can be suppressed while reducing gate leakage current.

In the case where the Al composition ratios of the cap layer 5 and the barrier layer 4 are different, in addition to a chlorine-based gas such as Cl ₂ during etching, a fluorine-based gas such as oxygen or SF ₆ is used selectively. In addition, only the cap layer can be etched, and the controllability of the etching depth is improved.

  Thereafter, the mask 15 is removed, and a surface protective film 11 is formed by laminating, for example, a nitride film such as Si or Al or a multilayer film made of these using a plasma CVD method or a cat-CVD method ( FIG. 18).

Next, using the resist pattern or the like as a mask 16, the cap layer 5 in the region where the gate electrode 10 is to be formed is removed together with the surface protection film 11 by a dry etching method using Cl ₂ or the like to form a first trench ( FIG. 19). As in the process shown in FIG. 17, when the Al composition ratios of the cap layer 5 and the barrier layer 4 are different, in addition to a chlorine-based gas such as Cl ₂ during etching, fluorine such as oxygen or SF ₆ is used. The controllability of the etching depth is improved by using the system gas.

After the mask 16 is removed, a metal such as Ti, Al, Pt, Au, Ni, Pd, a silicide such as IrSi, PtSi, NiSi ₂ , a nitride metal such as TiN, WN, or the like is used. A gate electrode 10 made of a multilayer film is deposited by vapor deposition or sputtering, and formed by lift-off or the like (FIG. 20). In forming the gate electrode 10, a resist pattern having an opening having the same width as the etched region is used, or the resist pattern is tapered by adjusting exposure and development parameters, and then vapor deposition is performed. A rectangular, trapezoidal, or Y-shaped gate electrode 10 can be formed by depositing electrodes by a method or the like.

  By the above method, a heterojunction FET having the structure shown in FIG. 1 can be manufactured. In the above description, only the minimum necessary elements that operate as a transistor have been described. However, the element is finally used as a device through a formation process of wiring, via holes, and the like.

  That is, in the method of manufacturing a heterojunction FET made of a nitride semiconductor according to the present embodiment, (a) a step of forming a cap layer 5 on the barrier layer 4, and (b) forming a gate electrode 10 of the cap layer 5 Forming the source electrode 9 and the drain electrode 8 apart from both sides of the region to be formed; and (c) forming a first trench in the region of the cap layer 5 where the gate electrode 10 is to be formed; Forming a second trench at least in the cap layer 5 of the first region among the first region between the first electrode and the drain electrode 8 and the second region between the first trench and the source electrode 9, and (d) Forming a gate electrode 10 in the first trench. As a result, the second trench formed in the cap layer 5 physically cuts off the path through which the gate leakage current transmitted through the cap layer 5 flows, so that the film thickness of the GaN cap layer 5 is increased, that is, a deep recessed gate structure. Even in this case, the gate leakage current can be reduced and the current collapse can be suppressed.

  In FIG. 15, without performing ion implantation, the cap layer 5 is removed by a dry etching method using the mask 14, and the drain electrode 8 and the source electrode 9 are formed in the removed region. When the process shown in FIG. 20 is performed, a heterojunction FET having a structure without the ion implantation regions 6 and 7 shown in FIG. 6 can be manufactured.

  In addition, when a desired region is etched by changing the mask pattern at the time of etching shown in FIGS. 17 and 19, a heterojunction FET having the structure shown in FIG. 10 can be manufactured.

  Further, after the surface protective film 11 shown in FIG. 18 is formed, an oxide of at least one kind of atoms of, for example, Al, Ga, Si, Hf, Ti, or the like is used by using a plasma CVD method or a cat-CVD method. Then, by forming an insulating film made of nitride, oxynitride, etc., and then performing the steps shown in FIGS. 19 and 20, a heterojunction FET having the insulating film 13 shown in FIG. 8 can be manufactured. Alternatively, after depositing the above-described insulating film using a mask made of a resist pattern or the like, the insulating film is left only in a predetermined region by a lift-off method or the like, and then the steps shown in FIGS. 19 and 20 are performed. 9 can be produced. However, the order of the steps may be changed, and the step of forming the gate electrode 10 (FIG. 20) may be performed before the surface protective film 11 and the insulating film 13 are formed. For final use as a device, a part of the source / drain electrode covered with the surface protective film 11 or the insulating film 13 is removed by wet etching using, for example, hydrofluoric acid, and then the wiring is removed. Need to form.

  When the heterojunction FET having the self-aligned structure shown in FIGS. 11 and 12 is manufactured, after the steps shown in FIGS. 17 and 18 are omitted and the gate electrode 10 is formed (FIG. 20), the drain electrode 8, Using the source electrode 9 and the gate electrode 10 as a mask, the cap layer 5 is removed by, for example, a dry etching method to form a trench, and then the surface protective film 11 is formed.

  Further, in the process of manufacturing the hetero-junction FET having the self-aligned structure, in the step shown in FIG. 15, the opening of the resist pattern on the source electrode 9 side is widened, and in the step shown in FIG. If it is formed by a lift-off method or the like in the vicinity of the region where 10 is to be formed, a heterojunction FET having a structure as shown in FIG. 13 can be manufactured.

  That is, the method for manufacturing a heterojunction FET made of a nitride semiconductor according to the present embodiment includes (a) a step of forming a cap layer 5 on the barrier layer 4, and (b) a gate electrode 10 of the cap layer 6. A step of forming the source electrode 9 and the drain electrode 8 apart from both sides of the region to be formed; (c) a step of forming a first trench in the region of the cap layer 5 where the gate electrode 10 is to be formed; ) Forming a gate electrode 10 in the first trench; and (e) etching the cap layer 5 using the gate electrode 10, the drain electrode 8 and the source electrode 9 as a mask to form a second trench. According to such a method, since the electrode is used as a mask, it is not necessary to form a pattern with a resist mask, and the process becomes simple.

  In the step of forming the second trench by etching the cap layer 5 using the gate electrode 10, the drain electrode 8 and the source electrode 9 as a mask, the second trench is formed leaving the cap layer 5 of 28 nm or less at the bottom. Thus, a heterojunction FET that suppresses current collapse while reducing gate leakage current can be manufactured by a simple process using an electrode as a mask.

  Note that it is not necessary to employ all the processes described above, and a process combining them may be used.

<Effect>
According to the heterojunction FET of the present embodiment, the following effects can be obtained as described above. That is, the heterojunction FET of the present embodiment is a heterojunction FET made of a nitride semiconductor, and the barrier layer 4, the cap layer 5 provided on the barrier layer 4, and the lower part thereof is buried in the cap layer 5. Thus, the gate electrode 10 provided on the cap layer 5, and the source electrode 9 and the drain electrode 8 provided separately on both sides of the gate electrode 10, respectively, between the gate electrode 10 and the drain electrode 8 are provided. Among the first region and the second region between the gate electrode 10 and the source electrode 9, at least one trench is formed in the cap layer 5 in the first region. By adopting such a structure, the trench structure physically cuts off the path through which the gate leakage current transmitted through the GaN cap layer 5 flows. Therefore, the GaN cap layer 5 has a large film thickness, that is, a deep recess gate structure. Even in this case, gate leakage current can be reduced and current collapse can be suppressed.

  Alternatively, the trench of the GaN cap layer 5 is formed in both the first region and the second region. Even in such a structure, since the trench structure physically blocks the path through which the gate leakage current transmitted through the GaN cap layer 5 flows, even when the GaN cap layer 5 has a large film thickness, that is, a deep recess gate structure. Gate leakage current can be reduced and current collapse can be suppressed.

  Further, the trench in the first region, which is a region between the gate electrode 10 and the drain electrode 8, is a single trench formed with its end portion aligned with the end portions of the gate electrode and the drain electrode 8. With such a structure, trenches can be formed by performing self-aligned dry etching using the gate electrode 10 and the drain electrode 8 as a mask, and the process of forming a resist mask is omitted, thus improving the simplicity of the process. effective.

  Further, the trench in the second region, which is a region between the gate electrode 10 and the source electrode 9, is a single trench formed with its end portions aligned with the end portions of the gate electrode 10 and the source electrode 9. With such a structure, trenches can be formed by performing self-aligned dry etching using the gate electrode 10 and the source electrode 9 as a mask, and the process of forming a resist mask is omitted, which is effective in improving process simplicity. There is.

  The trench is formed so as to leave the cap layer 5 of 28 nm or less at the bottom. As a result, current collapse can be suppressed while reducing gate leakage current.

  Further, according to the method of manufacturing the heterojunction FET of the present embodiment, the following effects can be obtained as described above. That is, in the method of manufacturing a heterojunction FET made of a nitride semiconductor according to the present embodiment, (a) a step of forming a cap layer 5 on the barrier layer 4, and (b) a gate electrode 10 of the cap layer 5 is formed. Forming the source electrode 9 and the drain electrode 8 apart from both sides of the region to be formed; and (c) forming a first trench in the region of the cap layer 5 where the gate electrode 10 is to be formed; Forming a second trench at least in the cap layer 5 of the first region among the first region between the first electrode and the drain electrode 8 and the second region between the first trench and the source electrode 9, and (d) Forming a gate electrode 10 in the first trench. As a result, the second trench formed in the cap layer 5 physically cuts off the path through which the gate leakage current transmitted through the cap layer 5 flows, so that the film thickness of the GaN cap layer 5 is increased, that is, a deep recessed gate structure. Even in this case, the gate leakage current can be reduced and the current collapse can be suppressed.

  Further, in the step (c), the second trench is formed leaving the cap layer 5 of 28 nm or less at the bottom. As a result, current collapse can be suppressed while reducing gate leakage current.

  Further, according to another method for manufacturing a heterojunction FET of the present embodiment, the following effects can be obtained as described above. That is, the method for manufacturing a heterojunction FET made of a nitride semiconductor according to the present embodiment includes (a) a step of forming a cap layer 5 on the barrier layer 4, and (b) a gate electrode 10 of the cap layer 6. A step of forming the source electrode 9 and the drain electrode 8 apart from both sides of the region to be formed; (c) a step of forming a first trench in the region of the cap layer 5 where the gate electrode 10 is to be formed; ) Forming a gate electrode 10 in the first trench; and (e) etching the cap layer 5 using the gate electrode 10, the drain electrode 8 and the source electrode 9 as a mask to form a second trench. According to such a method, since the electrode is used as a mask, it is not necessary to form a pattern with a resist mask, and the process becomes simple.

  In the step (e), the second trench is formed leaving the cap layer 5 of 28 nm or less at the bottom. Thus, a heterojunction FET that suppresses current collapse while reducing gate leakage current can be manufactured by a simple process using an electrode as a mask.

  1 semi-insulating substrate, 2 buffer layer, 3 channel layer, 4 barrier layer, 5 cap layer, 6 Si implanted region, 7 Si implanted region, 8 drain electrode, 9 source electrode, 10 gate electrode, 11 surface protective film, 12 Two-dimensional electron gas, 13 insulating film, 14-16 mask.

Claims (5)

A heterojunction field effect transistor made of a nitride semiconductor,
A barrier layer;
A cap layer provided on the barrier layer;
A source electrode and a drain electrode provided separately from each other;
A gate electrode provided on the cap layer between the source electrode and the drain electrode so as to bury a lower portion in the cap layer, and an upper portion of the gate electrode protruding at least toward the drain electrode ;
With
Wherein the first region and of the second region is between the gate electrode and the source electrode is between the gate electrode and the drain electrode, preparative wrench Te the cap layer odor of at least the first region is formed,
The trench in the first region is a single trench formed with an end portion thereof aligned with an end portion of the overhanging upper portion of the gate electrode and an end portion of the drain electrode. Junction field effect transistor. The upper part of the gate electrode projects to the source electrode side,
The trench is also formed in the second region,
2. The heterojunction electric field according to claim 1, wherein the trench of the second region is a single trench formed such that an end thereof is aligned with an end of the gate electrode and the source electrode. Effect transistor. 3. The heterojunction field effect transistor according to claim 1, wherein the trench is formed so as to leave the cap layer of 28 nm or less at the bottom. A method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor,
(A) forming a cap layer on the barrier layer;
(B) forming a source electrode and a drain electrode apart from both sides of a region where the gate electrode of the cap layer is to be formed;
(C) forming a first trench in a region of the cap layer where the gate electrode is to be formed;
(D) forming the gate electrode in the first trench;
(E) etching the cap layer using the gate electrode, the drain electrode, and the source electrode as a mask to form a second trench, and a method for manufacturing a heterojunction field effect transistor. 5. The method of manufacturing a heterojunction field effect transistor according to claim 4, wherein the step (e) is a step of forming the second trench leaving the cap layer of 28 nm or less at the bottom.

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