CN107219448B - The barrier layer internal trap of constant is distributed characterizing method when based on feature - Google Patents
The barrier layer internal trap of constant is distributed characterizing method when based on feature Download PDFInfo
- Publication number
- CN107219448B CN107219448B CN201710422200.XA CN201710422200A CN107219448B CN 107219448 B CN107219448 B CN 107219448B CN 201710422200 A CN201710422200 A CN 201710422200A CN 107219448 B CN107219448 B CN 107219448B
- Authority
- CN
- China
- Prior art keywords
- barrier layer
- pulse
- trap
- capture
- release
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The barrier layer internal trap of constant is distributed characterizing method when the invention discloses a kind of based on feature.Mainly solve the problem of that the prior art can not measure barrier layer internal trap below device grids and capture/discharge the total quantity of electronics and be unable to characterize electronics with pulse width interval change profile situation.Its implementation is: applying pulse voltage on the semiconductor devices to be tested of preparation, ammeter registration in observation circuit；The quantity that electronics was captured/discharged to device barrier layer internal trap is obtained by mathematical computations again；Then it by the way that the low and high level pulsewidth of pulse is varied multiple times, obtains trap and captures/discharge the distribution situation that the quantity of electronics changes with pulse width interval.The present invention advantage simple, as a result reliable with test process and test equipment, can be used for process optimization and the fail-safe analysis of microelectronic component, and the research to current collapse mechanism.
Description
Technical field
The invention belongs to microelectronic testing field, in particular to it is a kind of based on feature when constant barrier layer internal trap distribution
Characterizing method is used for heterojunction transistor, especially excellent using III-V material as the technique of the wide band gap semiconductor device of representative
Change and fail-safe analysis.
Background technique
It has many good qualities by the semiconductor material with wide forbidden band of representative of III-V material, the heterogeneous crystalline solid prepared with it
Tube device has the advantages that operating current is big, operating rate is fast, has in fields such as high frequency, high power, microwave and communication radars
Big advantage and broad application prospect.Therefore the type device has just become the hot spot that everybody studies since birth.
Semiconductor device art rapid development, but high frequency, big signal driving under, the output electric current of microelectronic component
The amplitude of oscillation reduces sharply, and output power density decline, this phenomenon is known as current collapse effect.In high temperature, the adverse circumstances such as high pressure and
Device under high-power applications also will appear phenomena such as leakage current decline, threshold voltage shift, seriously affect the steady of device work
It is qualitative, to find out its cause, researcher is considered that device draws in preparation process or under different use environments to barrier layer
Trap is entered.Therefore, the quantity of barrier layer internal trap trapped electron can assess barrier layer trap to degeneration in measurement device
Influence degree, and then optimised devices preparation process, improve the reliability of device.
The method of traditional measurement device current avalanche be using Semiconductor Parameter Analyzer to heterojunction semiconductor device into
Row direct current or pulse test obtain current collapse by comparing the maximum output current under different pulse voltages and DC voltage
Amount, however this method be unable to get the total quantity of barrier layer internal trap and trap below device grids capture/discharge electronics
Distribution situation of the quantity in distinct pulse widths interval, therefore also the manufacturing process of heterojunction semiconductor device can not just be carried out
Optimization, influences the job stability of heterojunction semiconductor device.
Summary of the invention
It is an object of the invention in view of the above shortcomings of the prior art, propose it is a kind of based on feature when constant barrier layer
Internal trap is distributed characterizing method, to realize the optimization to heterojunction semiconductor device manufacturing process, improves the operation is stable of device
Property.
To achieve the above object, technical solution of the present invention includes the following steps:
1) it makes tested device: successively preparing substrate, nucleating layer, buffering from bottom to top using heterogenous junction epitaxy technique
Layer, insert layer and barrier layer, then metal electrode is deposited on semiconductor material, source S and drain D are prepared, between source and drain
Grid G is prepared, remembers that the spacing of pole grid and drain electrode is LGD, the spacing of grid and source electrode is LGS, draining with the spacing of source electrode is LDS,
The length of grid, source electrode and three electrodes that drain is respectively LG, LS, LD；
2) connecting test circuit: source S is connect simultaneously with drain D and the second ammeter A2, successively by one end of grid G
It is connect with the first ammeter A1 and pulse power E, the other end of the second ammeter A2 and pulse power E is grounded；
3) capture/release electron amount when calculating the filling dynamic equilibrium of barrier layer internal trap:
3a) apply the pulse voltage in P period in the grid G of tested device, the pulse high level of pulse voltage is
VH, low-voltage puts down as VL, high pulse width WHLow-level pulse width is WLAnd pulse period T=WH+WL.The first electric current is read respectively
The registration I of Table A 1G(t) and the registration I of the second ammeter A2DS(t)；
The low level pulse for 3b) applying 0V to tested device grid G, obtains barrier layer trap trapped electron electric current I (t)
=IG(t)-IDS(t), and the current direction of regulation barrier layer trap trapped electron formation is positive；
It 3c) is applied more than the high level pulse of 0V to tested device grid G, obtains barrier layer trap release electronic current
I (t)=- | IG(t)-IDS(t) |, and the current direction that the release of regulation barrier layer trap electronically forms is negative；
3e) according to the relationship of the quantity of electric charge and electric current, calculate P and the P-1 pulse period internals barrier layer trap capture/
The electron amount of release is respectively as follows:
Wherein P is positive integer, and T is the pulse period；E is electron charge, and size is 1 × 10-19C；
3f) calculate step 3e) in the relative error of N (P) and N (P-1) that measures, judgement barrier layer trap capture/release
Whether electron amount reaches dynamic equilibrium:
IfThen determine that barrier layer trap is captured/discharged electron amount and reaches dynamic equilibrium, stops
Apply pulse voltage, remembers that the total electron amount of barrier layer internal trap capture/release at this time is N=N (P)；
Conversely, not up to dynamic equilibrium, then continue to execute step 3a) to 3e), until meeting capture/release electron amount
Dynamic equilibrium condition；
4) distribution of the barrier layer internal trap trapped electron quantity in different low-level pulse width intervals is calculated:
The low level width of pulse voltage 4a) is varied multiple times, keeps the other parameters of pulse voltage constant, repeats step 3)
All testing procedures, successively record barrier layer internal trap capture total electron amount NWL(k), wherein k=1,2,3 ..., m；
4b) according to step 4a), barrier layer internal trap is obtained in WL(k-1)-WL(k)Low-level pulse width between capture electricity
Subnumber amount are as follows:
ΔNWL(k)=NWL(k-1)-NWL(k),
Wherein, NWL(k-1)The barrier layer internal trap capture that the low level width for changing pulse voltage for kth -1 time obtains
Total electron amount, NWL(k)For the total electronics for the barrier layer internal trap capture that the low level width that kth time changes pulse voltage obtains
Quantity；
5) distribution of the barrier layer internal trap release electron amount in different high pulse width intervals is calculated:
The high level width of pulse 5a) is varied multiple times, keeps the other parameters of pulse voltage constant, repeats the institute of step 3)
There is testing procedure, successively records total electron amount N of barrier layer internal trap releaseWH(k)；
5b) according to step 5a), barrier layer internal trap is obtained in WH(k)-WH(k-1)High pulse width between the electronics that discharges
Quantity are as follows: Δ NWH(k)=NWH(k)-NWH(k-1), wherein NWH(k-1)What the high level width for changing pulse voltage for kth -1 time obtained
Total electron amount of barrier layer internal trap capture, NWH(k)The barrier layer obtained for the high level width that kth time changes pulse voltage
Total electron amount of internal trap release.
The invention has the following advantages over the prior art:
1) distribution situation that electronics was captured/discharged to trap can directly be characterized.
The present invention can not only directly obtain the electronics sum of barrier layer capture below grid by survey calculation, can be with
The distribution situation in different low-level pulse width interval inner potential barrier layer internal trap trapped electron quantity is obtained, and in different high level
Pulse width interval inner potential barrier layer internal trap discharges the distribution situation of electron amount, has thus reacted between different low, high pulse widths
Every the distribution situation of inner potential barrier layer internal trap quantity；
2) test equipment and test process are simple.
Test equipment and test process needed for the present invention are very simple, it is only necessary to which monitoring applies two during pulse voltage
Ammeter registration, then test data is quickly handled through simple mathematical formulae, so that it may obtain square barrier under test device grids
The electron amount of layer trap capture；
It is 3) of the invention since the interval of the pulse width applied to device is exactly the when constant of trap capture and release electronics,
Thus by testing under different pulsewidths, the distribution situation of trap capture and release electron amount constant at any time can be obtained.
Detailed description of the invention
Fig. 1 is implementation flow chart of the invention；
Fig. 2 is test circuit diagram of the invention；
Fig. 3 is to apply ammeter registration real-time change schematic diagram in P pulse process to Fig. 1；
Fig. 4 be in the present invention barrier layer internal trap trapped electron quantity with low-level pulse width change schematic diagram；
Constant distribution changes schematic diagram with low-level pulse width when Fig. 5 is barrier layer internal trap trapped electron in the present invention；
Fig. 6 is that barrier layer internal trap discharges electron amount with high pulse width variation schematic diagram in the present invention；
Fig. 7 is that constant is distributed with high pulse width variation schematic diagram when barrier layer internal trap discharges electronics in the present invention.
Specific embodiment
With reference to the accompanying drawings and examples, specific embodiments of the present invention will be described in further detail.Embodiment
For illustrating the present invention, but it is not intended to limit the scope of the invention.
Referring to Fig.1, this step is implemented as follows:
Step 1, tested device is made.
1a) substrate, nucleating layer, buffer layer, insert layer and potential barrier are successively prepared from bottom to top using heterogenous junction epitaxy technique
Layer；
Metal electrode 1b) is deposited on barrier layer again, prepares source S and drain D, grid G is prepared between source and drain, is remembered
Pole grid and the spacing of drain electrode are LGD, the spacing of grid and source electrode is LGS, draining with the spacing of source electrode is LDS, note grid, source electrode and
The length of three electrodes of draining is respectively LG, LS, LD；
This example sets but is not limited to the spacing L of pole grid and drain electrodeGD=2.5 μm, the spacing L of grid and source electrodeGS=2.5 μm,
The spacing L of drain electrode and source electrodeDS=5.4 μm；
It is respectively L that this example, which sets but be not limited to grid, source electrode and the length of drain electrode,G=0.4 μm, LS=0.5 μm, LD=0.5
μm；
The tested device that the present invention applies meets LGD> 5LG, LGS> 5LG, the trap pair in device barrier layer can be ignored
The capture effect of electronics at gate interface.
Step 2, connecting test circuit.
Referring to Fig. 2, source S is connect simultaneously with drain D and the second ammeter A2, by one end of grid G successively with first
Ammeter A1 is connected with pulse power E, and the other end of the second ammeter A2 and pulse power E is grounded.
Step 3, capture/release electron amount when barrier layer internal trap is filled up to dynamic equilibrium is calculated.
Referring to Fig. 3, whether this step reaches dynamic to the reading of ammeter registration and judgement capture capture/release electronics
The specific testing procedure of balance is as follows:
3a) first apply the pulse voltage in P period in the grid G of tested device, the high level of the pulse voltage is
VH, low-voltage puts down as VL, high pulse width WH, low-level pulse width WL, pulse period T=WH+WL；Read the first electricity respectively again
The registration I of flow table A1G(t) and the registration I of the second ammeter A2DS(t)；
The low level pulse for 3b) applying 0V to tested device grid G, obtains barrier layer trap trapped electron electric current I (t)
=IG(t)-IDS(t), and the current direction of regulation barrier layer trap trapped electron formation is positive；
It 3c) is applied more than the high level pulse of 0V to tested device grid G, obtains barrier layer trap release electronic current
I (t)=- | IG(t)-IDS(t) |, and the current direction that the release of regulation barrier layer trap electronically forms is negative；
3e) according to the relationship of the quantity of electric charge and electric current, the P pulse period internals barrier layer trap capture/release is calculated
Electron amount N (P):
Calculate the P-1 pulse period internals barrier layer trap capture/release electron amount N (P-1):
Wherein P is positive integer, and T is the pulse period；E is electron charge, and size is 1 × 10-19C；
3f) calculate step 3e) in the P pulse period internals barrier layer trap capture/release electron amount N (P)
With the relative error of the P-1 pulse period internals barrier layer trap capture/release electron amount N (P-1), barrier layer is determined
Whether trap capture capture/release electron amount reaches dynamic equilibrium:
IfThen determine that barrier layer trap capture capture/release electron amount reaches dynamic equilibrium,
Stop applying pulse voltage, remembers that total electron amount of barrier layer internal trap capture at this time is N=N (P)；
Conversely, not up to dynamic equilibrium, then continue to execute step 3a) to 3e), until meeting capture/release electron amount
Dynamic equilibrium condition.
Step 4, distribution of the barrier layer internal trap trapped electron quantity in different low-level pulse width intervals is calculated.
This step obtains the specific test step of barrier layer internal trap trapped electron quantity variation by changing low level width
It is rapid as follows:
The low level width for 4a) successively changing pulse voltage is WL(1), WL(2), WL(3)..., WL(m), and keep pulse electric
The pulse high level V of pressureH, pulses low VLAnd high pulse width WHIt is constant, all testing procedures of step 3 are repeated, are successively remembered
Record total electron amount N of barrier layer internal trap captureWL(k), obtain barrier layer internal trap trapped electron quantity and become with low-level pulse width
Change schematic diagram, such as Fig. 4, wherein WL(1)<WL(2)<WL(3)<...<WL(m), k=1,2,3 ..., m, m is positive integer；
4b) according to step 4a), barrier layer internal trap is obtained in WL(k-1)-WL(k)Low-level pulse width between capture electricity
Subnumber amount are as follows: Δ NWL(k)=NWL(k)-NWL(k-1), wherein NWL(k-1)The low level width for changing pulse voltage for kth -1 time obtains
Barrier layer internal trap capture total electron amount, NWL(k)The potential barrier obtained for the low level width that kth time changes pulse voltage
Total electron amount of layer internal trap capture；
It 4c) is obtained according to the formula of step 4b) as shown in Figure 5 in different low-level pulse width interval inner potential barrier layer internal traps
Trapped electron amount Δ NWL(k)Distribution situation, according to the theory of Semiconductor Physics, the trapped electron that applies to device under test
The time of pulse is exactly the when constant of trap trapped electron, therefore constant internal trap capture electricity when Fig. 5 substantially characterizes different
Sub- amount Δ NWL(k)Distribution situation.
Step 5, distribution of the barrier layer internal trap release electron amount in different high pulse width intervals is calculated.
This step obtains the variation realization of barrier layer internal trap trapped electron quantity by changing low level width, and step is such as
Under:
The high level width for 5a) successively changing pulse voltage is WH(1), WH(2), WH(3)..., WH(m), and keep pulse electric
The pulse high level V of pressureH, pulses low VLAnd low-level pulse width WLIt is constant, all testing procedures of step 3 are repeated, are successively remembered
Record total electron amount N of barrier layer internal trap captureWH(k), obtain barrier layer internal trap release electron amount and become with high pulse width
Change schematic diagram, such as Fig. 6, wherein WH(1)<WH(2)<WH(3)<...<WH(m), k=1,2,3 ..., m, m is positive integer；
5b) according to step 5a), barrier layer internal trap is obtained in WH(k-1)-WH(k)High pulse width between the electronics that discharges
Quantity are as follows: Δ NWH(k)=NWH(k-1)-NWH(k), wherein NWH(k)The potential barrier obtained for the high level width that kth time changes pulse voltage
Total electron amount of layer internal trap release, NWH(k-1)The barrier layer that the high level width for changing pulse voltage for kth -1 time obtains
Total electron amount of internal trap release；
5c) according to the formula of step 5b), the invagination of the barrier layer between different high pulse widths as shown in Figure 7 is obtained
The electron amount Δ N of trap releaseWH(k)Distribution situation；According to the theory of Semiconductor Physics, the release electricity applied to device under test
The time of the pulse width of son is exactly the when constant of trap release electronics, therefore constant invaginates when Fig. 7 substantially characterizes different
Trap discharges electronics Δ NWH(k)Distribution situation.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, it is clear that for this field
Professional for, after understanding the contents of the present invention and principle, can modify within the spirit and principles in the present invention,
Equivalent replacement and improvement etc., for example, resolution chart of the present invention is based on III-IV compound semiconductor hetero-junctions
The transistor device of material preparation, can equally be well applied to the semiconductor devices with ohmic contact regions of other race's elements preparation,
Such as the MOS device of Si, Ge material preparation.These made modifications, equivalent substitutions and improvements should be included in guarantor of the invention
Within the scope of shield.
Claims (4)
1. a kind of barrier layer internal trap based on characteristic time constant is distributed characterizing method, include the following steps:
1) it makes tested device: successively preparing substrate from bottom to top using heterogenous junction epitaxy technique, nucleating layer, buffer layer, inserts
Enter layer and barrier layer, then deposit metal electrode on semiconductor material, prepare source S and drain D, grid are prepared between source and drain
Pole G remembers that the spacing of pole grid and drain electrode is LGD, the spacing of grid and source electrode is LGS, draining with the spacing of source electrode is LDS, grid, source
The length of pole and three electrodes that drain is respectively LG, LS, LD；
2) connecting test circuit: source S is connect simultaneously with drain D and the second ammeter A2, by one end of grid G successively with
One ammeter A1 is connected with pulse power E, and the other end of the second ammeter A2 and pulse power E is grounded；
3) capture/release electron amount when barrier layer internal trap is filled up to dynamic equilibrium is calculated:
3a) apply the pulse voltage in P period in the grid G of tested device, the pulse high level of pulse voltage is VH, it is low
Voltage is put down as VL, high pulse width WHLow-level pulse width is WLAnd pulse period T=WH+WL；The first ammeter A1 is read respectively
Registration IG(t) and the registration I of the second ammeter A2DS(t)；
The low level pulse for 3b) applying 0V to tested device grid G, obtains barrier layer trap trapped electron electric current I (t)=IG
(t)-IDS(t), and the current direction of regulation barrier layer trap trapped electron formation is positive；
It 3c) is applied more than the high level pulse of 0V to tested device grid G, obtains barrier layer trap release electronic current I (t)
=-| IG(t)-IDS(t) |, and the current direction that the release of regulation barrier layer trap electronically forms is negative；
3e) according to the relationship of the quantity of electric charge and electric current, P and the P-1 pulse period internals barrier layer trap capture/release are calculated
Electron amount be respectively as follows:
Wherein P is positive integer, and T is the pulse period；E is electron charge, and size is 1 × 10-19C；
3f) calculate step 3e) in the P pulse period internals barrier layer trap capture/release electron amount N (P) and the
The relative error of P-1 pulse period internals barrier layer trap capture/release electron amount N (P-1) determines barrier layer trap
Whether capture/release electron amount reaches dynamic equilibrium:
IfThen determine that barrier layer trap is captured/discharged electron amount and reaches dynamic equilibrium, stops applying
Pulse voltage remembers that the total electron amount of barrier layer internal trap capture/release at this time is N=N (P)；
Conversely, not up to dynamic equilibrium, then continue to execute step 3a) to 3e), until meeting capture/release electron amount dynamic
Equilibrium condition；
4) distribution of the barrier layer internal trap trapped electron quantity in different low-level pulse width intervals is calculated:
The low level width of pulse voltage 4a) is varied multiple times, keeps the other parameters of pulse voltage constant, repeats the institute of step 3)
There is testing procedure, successively records total electron amount N of barrier layer internal trap captureWL(k), wherein k=1,2,3 ..., m；
4b) according to step 4a), barrier layer internal trap is obtained in WL(k-1)-WL(k)Low-level pulse width interval in capture electron number
Amount are as follows: Δ NWL(k)=NWL(k)-NWL(k-1), wherein NWL(k-1)The gesture that the low level width for changing pulse voltage for kth -1 time obtains
Total electron amount of barrier layer internal trap capture, NWL(k)In the barrier layer obtained for the low level width that kth time changes pulse voltage
Total electron amount of trap capture；
5) distribution of the barrier layer internal trap release electron amount in different high pulse width intervals is calculated:
The high level width of pulse 5a) is varied multiple times, keeps the other parameters of pulse voltage constant, repeats all surveys of step 3)
Try is rapid, successively records total electron amount N of barrier layer internal trap releaseWH(k)；
5b) according to step 5a), barrier layer internal trap is obtained in WH(k)-WH(k-1)High pulse width interval in discharge electron number
Amount are as follows: Δ NWH(k)=NWH(k)-NWH(k-1), wherein NWH(k-1)The gesture that the high level width for changing pulse voltage for kth -1 time obtains
Total electron amount of barrier layer internal trap release, NWH(k)In the barrier layer obtained for the high level width that kth time changes pulse voltage
Total electron amount of trap release.
2. according to the method described in claim 1, wherein in step 1 grid and source electrode spacing LGSAnd the spacing of grid and drain electrode
LGDIt is all larger than 5 times of grid length LG, it may be assumed that LGD> 5LG, LGS> 5LG, to ignore the trap in device barrier layer to gate interface
Locate the capture effect of electronics.
3. according to the method described in claim 1, wherein step 4a) in the low level width of pulse voltage is varied multiple times, keep
The other parameters of pulse voltage are constant, are to maintain the pulse high level V of device under test applicationH, pulses low VLAnd high level arteries and veins
Wide WHConstant, successively changing low-level pulse width is WL(1), WL(2), WL(3)..., WL(m), wherein WL(1)<WL(2)<WL(3)<...<
WL(m), and in the condition of these low-level pulse widths successively lower all test operations for repeating step 3), obtain different low level arteries and veins
Wide WL(k)Total electron amount N of lower barrierlayer internal trap captureWL(k)。
4. according to the method described in claim 1, wherein step 5a) in the high level width of pulse voltage is varied multiple times, keep
The other parameters of pulse voltage are constant, are to maintain the pulse high level V of device under test applicationH, pulses low VLAnd low level arteries and veins
Wide WLConstant, successively changing high pulse width is WH(1), WH(2), WH(3)..., WH(m), and the condition of these high pulse widths according to
The secondary lower all test operations for repeating step 3), obtain different high pulse width WH(k)Total electronics of lower barrierlayer internal trap release
Quantity NWH(k), wherein WH(1)<WH(2)<WH(3)<...<WH(m)。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710422200.XA CN107219448B (en) | 2017-06-07 | 2017-06-07 | The barrier layer internal trap of constant is distributed characterizing method when based on feature |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710422200.XA CN107219448B (en) | 2017-06-07 | 2017-06-07 | The barrier layer internal trap of constant is distributed characterizing method when based on feature |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107219448A CN107219448A (en) | 2017-09-29 |
| CN107219448B true CN107219448B (en) | 2019-03-26 |
Family
ID=59947812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710422200.XA Active CN107219448B (en) | 2017-06-07 | 2017-06-07 | The barrier layer internal trap of constant is distributed characterizing method when based on feature |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107219448B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101562182A (en) * | 2008-04-02 | 2009-10-21 | 香港科技大学 | Integrated hemt and a combination, method as well as a system of a horizontal field effect rectifier |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9406574B1 (en) * | 2007-08-09 | 2016-08-02 | Cypress Semiconductor Corporation | Oxide formation in a plasma process |
| KR101570652B1 (en) * | 2009-05-06 | 2015-11-23 | 엠케이에스 인스트루먼츠, 인코포레이티드 | Electrostatic ion trap |
| CN102832203B (en) * | 2012-08-29 | 2014-10-08 | 北京大学 | Structure and method for testing trap density of gate oxide interface |
| CN103367193B (en) * | 2013-07-24 | 2015-10-07 | 北京大学 | The method of testing of gate oxide trap density and position and device |
| JP6225584B2 (en) * | 2013-09-13 | 2017-11-08 | 富士電機株式会社 | Semiconductor device evaluation method, semiconductor device and manufacturing method thereof |
| CN105006500B (en) * | 2015-06-18 | 2017-01-25 | 西安电子科技大学 | Transverse IV-clan element quantum well photoelectric detector and preparation method |
| CN106546638B (en) * | 2015-09-23 | 2019-02-26 | 中国科学院宁波材料技术与工程研究所 | The test method of energy band defect concentration distribution |
| CN105466970B (en) * | 2015-12-11 | 2018-02-13 | 北京大学 | For detecting the detection method and structure of trap states in gallium nitride radical heterojunction structure |
-
2017
- 2017-06-07 CN CN201710422200.XA patent/CN107219448B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101562182A (en) * | 2008-04-02 | 2009-10-21 | 香港科技大学 | Integrated hemt and a combination, method as well as a system of a horizontal field effect rectifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107219448A (en) | 2017-09-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Elliot | The use of charge pumping currents to measure surface state densities in MOS transistors | |
| Berglund | Surface states at steam-grown silicon-silicon dioxide interfaces | |
| Bonilla et al. | On the c-Si/SiO2 interface recombination parameters from photo-conductance decay measurements | |
| CN102621473B (en) | Test method generated by monitoring negative bias temperature instability (NBTI) effect interface states in real time | |
| CN103367193B (en) | The method of testing of gate oxide trap density and position and device | |
| CN108318796B (en) | Three-port silicon carbide-based power device interface state testing method | |
| CN110824321B (en) | Stray capacitance obtaining method for IGBT dynamic parameter test platform | |
| CN109116209A (en) | A kind of test method of silica-interface state density and capture interface | |
| CN107219448B (en) | The barrier layer internal trap of constant is distributed characterizing method when based on feature | |
| CN107703431B (en) | Device surface state trap measurement method based on changeable frequency pulse technique | |
| US9465069B2 (en) | Method for the extraction of recombination characteristics at metallized semiconductor surfaces | |
| CN109541321A (en) | A kind of small signal capacitance test method of MOS transistor grid and system | |
| CN105158666B (en) | A kind of method for measuring and characterizing semiconductor devices trap parameters | |
| Stradiotto et al. | On the fly characterization of charge trapping phenomena at GaN/dielectric and GaN/AlGaN/dielectric interfaces using impedance measurements | |
| CN114564907A (en) | Method for establishing GaN HEMT device threshold voltage and drain current model | |
| CN107703430B (en) | The measurement method that surface state trap influences device output characteristics | |
| Taniguchi | Graphical technique to determine minority carrier lifetime and surface generation velocity using triangular-voltage sweep CV method | |
| CN114216939B (en) | Silicon carbide surface defect state energy distribution measuring method, system and storage medium | |
| CN103913690A (en) | Method and system for measuring transistor output resistance frequency dispersion characteristic | |
| Kemmer et al. | Current-voltage characteristics of silicon solar cells: Determination of base doping concentration and hysteresis correction | |
| Matre | Deep-level transient spectroscopy system with a response time in the microsecond time frame | |
| Stradiotto et al. | Characterization of charge trapping phenomena at III–N/dielectric interfaces | |
| CN116362035A (en) | Substrate bias effect simulation modeling method for silicon-based GaN HEMT device | |
| Wachnik | The use of charge pumping to characterize generation by interface traps | |
| Ostapchuk et al. | Evaluation of the Self-Heating Effect in the Static Characterization of Cryo-Cooled Power Diodes |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |