CN107219448A - The barrier layer internal trap distribution characterizing method of constant during feature based - Google Patents
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Abstract
Characterizing method is distributed the invention discloses a kind of barrier layer internal trap of constant during feature based.Mainly solution prior art can not measure barrier layer internal trap below device grids and capture/discharge the total quantity of electronics, and can not characterize the problem of electronics is with pulse width interval change profile situation.Its implementation is：Apply ammeter registration in pulse voltage, observation circuit on the semiconductor devices to be tested of preparation；Again the quantity that electronics was captured/discharged to device barrier layer internal trap is obtained by mathematical computations；Then by the way that the low and high level pulsewidth of pulse is varied multiple times, obtain trap and capture/discharge the distribution situation that the quantity of electronics changes with pulse width interval.The present invention has test process and test equipment simple, the advantage of reliable results, process optimization and fail-safe analysis available for microelectronic component, and the research to current collapse mechanism.
Description
Technical field
The invention belongs to the barrier layer internal trap distribution of constant during a kind of microelectronic testing field, more particularly to feature based
Characterizing method, it is particularly excellent using III-V material as the technique of the wide band gap semiconductor device of representative for heterojunction transistor
Change and fail-safe analysis.
Background technology
Semiconductor material with wide forbidden band using III-V material as representative has many good qualities, the heterogeneous crystalline solid prepared with it
Tube device has the advantages that operating current is big, operating rate is fast, has in fields such as high frequency, high power, microwave and communication radars
Big advantage and it is widely applied prospect.Therefore the type device has just turned into the focus that everybody studies since the birth.
Semiconductor device art is developed rapidly, but under high frequency, the driving of big signal, the output current of microelectronic component
The amplitude of oscillation is reduced sharply, and output power density declines, and this phenomenon is referred to as current collapse effect.In high temperature, the adverse circumstances such as high pressure and
The phenomenons such as leakage current decline, threshold voltage shift also occur in device under high-power applications, have a strong impact on the steady of device work
It is qualitative, to find out its cause, researcher is considered that device draws in preparation process or under different use environments to barrier layer
Trap is entered.Therefore, the quantity of barrier layer internal trap trapped electron can assess barrier layer trap to degeneration in measurement device
Influence degree, and then optimised devices preparation technology, improve the reliability of device.
The method of traditional measurement device current avalanche is that heterojunction semiconductor device is entered using Semiconductor Parameter Analyzer
Row direct current or pulse test, by the maximum output current under relatively more different pulse voltages and DC voltage, obtain current collapse
Amount, however this method can not obtain barrier layer internal trap below device grids total quantity and trap capture/discharge electronics
Distribution situation of the quantity in distinct pulse widths interval, therefore also the manufacturing process of heterojunction semiconductor device can not just be carried out
Optimization, influences the job stability of heterojunction semiconductor device.
The content of the invention
It is an object of the invention to for above-mentioned the deficiencies in the prior art, propose a kind of barrier layer of constant during feature based
Internal trap is distributed characterizing method, to realize the optimization to heterojunction semiconductor device manufacturing process, improves the working stability of device
Property.
To achieve the above object, technical scheme comprises the following steps：
1) tested device is made：Substrate, nucleating layer, buffering are prepared from bottom to top successively using heterogenous junction epitaxy technique
Layer, insert layer and barrier layer, then metal electrode is deposited on semi-conducting material, source S and drain D are prepared, between source and drain
Grid G is prepared, note pole grid are L with the spacing drainedGD, the spacing of grid and source electrode is LGS, drain and the spacing of source electrode be LDS,
The length of grid, source electrode and three electrodes that drain is respectively LG, LS, LD；
2) connecting test circuit：One end of source S is connected with drain D, the other end is connected with the second ammeter A2, by grid
Pole G one end is connected with pulse power E and the first ammeter A1 successively, by the second ammeter A2 and pulse power E other end
It is grounded；
3) electron amount of capture/release when calculating the filling dynamic equilibrium of barrier layer internal trap：
3a) apply the pulse voltage in P cycle in the grid G of tested device, the pulse high level of pulse voltage is
VH, low-voltage put down as VL, high pulse width be WHLow-level pulse width is WLAnd pulse period T=WH+WL.The first electric current is read respectively
The registration I of Table A 1G(t) with the second ammeter A2 registration IDS(t)；
3b) apply 0V low level pulse to tested device grid G, obtain barrier layer trap trapped electron electric current I (t)
=IG(t)-IDS(t), and provide the sense of current of barrier layer trap trapped electron formation for just；
0V high level pulse 3c) is applied more than to tested device grid G, barrier layer trap release electronic current is obtained
I (t)=- | IG(t)-IDS(t) |, and the sense of current that the release of regulation barrier layer trap is electronically formed is negative；
3e) according to the relation of the quantity of electric charge and electric current, calculate P and the P-1 pulse period internals barrier layer trap capture/
The electron amount of release is respectively：
Wherein P is positive integer, and T is the pulse period；E is electron charge, and its size is 1 × 10-19C；
3f) calculation procedure 3e) in the N (P) that measures and N (P-1) relative error, judge barrier layer trap capture/release
Whether electron amount reaches dynamic equilibrium：
IfThen judge that barrier layer trap is captured/discharged electron amount and reaches dynamic equilibrium, stop
Apply pulse voltage, total electron amount of the barrier layer internal trap capture/release of note now is N=N (P)；
Conversely, not up to dynamic equilibrium, then continue executing with step 3a) to 3e), until meeting capture/release electron amount
Dynamic equilibrium condition；
4) distribution of the barrier layer internal trap trapped electron quantity in different low-level pulse width intervals is calculated：
The low level width of pulse voltage 4a) is varied multiple times, keeps the other specification of pulse voltage constant, repeat step 3)
All testing procedures, total electron amount N of barrier layer internal trap capture is recorded successivelyWL(k), wherein k=1,2,3 ..., m；
4b) according to step 4a), barrier layer internal trap is obtained in WL(k-1)-WL(k)Low-level pulse width between capture electricity
Quantum count is：
ΔNWL(k)=NWL(k-1)-NWL(k),
Wherein, NWL(k-1)The barrier layer internal trap capture obtained for the low level width of -1 change pulse voltage of kth
Total electron amount, NWL(k)The total electronics for the barrier layer internal trap capture that the low level width for changing pulse voltage for kth time is obtained
Quantity；
5) distribution of the barrier layer internal trap release electron amount in different high pulse width intervals is calculated：
5a) be varied multiple times the high level width of pulse, keep the other specification of pulse voltage constant, repeat step 3) institute
There is testing procedure, total electron amount N of barrier layer internal trap release is recorded successivelyWH(k)；
5b) according to step 5a), barrier layer internal trap is obtained in WH(k)-WH(k-1)High pulse width between the electronics that discharges
Quantity is：ΔNWH(k)=NWH(k)-NWH(k-1), wherein, NWH(k-1)Obtained for the high level width of kth -1 time change pulse voltage
Total electron amount of barrier layer internal trap capture, NWH(k)The barrier layer that the high level width for changing pulse voltage for kth time is obtained
Total electron amount of internal trap release.
The present invention has the following advantages that compared with prior art：
1) distribution situation that electronics was captured/discharged to trap can directly be characterized.
The present invention can not only directly obtain the electronics sum of barrier layer capture below grid by survey calculation, can be with
The distribution situation in different low-level pulse width interval inner potential barrier layer internal trap trapped electron quantity is obtained, and in different high level
Pulse width interval inner potential barrier layer internal trap discharges the distribution situation of electron amount, has thus reacted between different low, high pulse widths
Every the distribution situation of inner potential barrier layer internal trap quantity；
2) test equipment and test process are simple.
Test equipment and test process are very simple needed for of the invention, it is only necessary to which monitoring applies two during pulse voltage
Ammeter registration, then through simple mathematical formulae to the quick processing of test data, so that it may obtain square barrier under test device grids
The electron amount of layer trap capture；
It is 3) of the invention because the interval of the pulse width applied to device is exactly the when constant of trap capture and release electronics,
Thus by being tested under different pulsewidths, the distribution situation of trap capture and release electron amount constant at any time can obtain.
Brief description of the drawings
Fig. 1 is the implementation process figure of the present invention；
Fig. 2 is the test circuit schematic diagram of the present invention；
Fig. 3 is to apply ammeter registration real-time change schematic diagram in P pulse process to Fig. 1；
Fig. 4 be in the present invention barrier layer internal trap trapped electron quantity with low-level pulse width change schematic diagram；
Constant distribution is with low-level pulse width change schematic diagram when Fig. 5 is barrier layer internal trap trapped electron in the present invention；
Fig. 6 is that barrier layer internal trap discharges electron amount with high pulse width change schematic diagram in the present invention；
Constant distribution is with high pulse width change schematic diagram when Fig. 7 is barrier layer internal trap release electronics in the present invention.
Embodiment
With reference to the accompanying drawings and examples, the embodiment to the present invention is described in further detail.Embodiment
For illustrating the present invention, but it is not limited to the scope of the present invention.
Reference picture 1, this step is implemented as follows：
Step 1, tested device is made.
1a) substrate, nucleating layer, cushion, insert layer and potential barrier are prepared from bottom to top successively using heterogenous junction epitaxy technique
Layer；
Metal electrode 1b) is deposited on barrier layer again, source S and drain D is prepared, grid G is prepared between source and drain, is remembered
Pole grid are L with the spacing drainedGD, the spacing of grid and source electrode is LGS, drain and the spacing of source electrode be LDS, note grid, source electrode and
The length of three electrodes of drain electrode is respectively LG, LS, LD；
This example sets but is not limited to pole grid and the spacing L of drain electrodeGD=2.5 μm, the spacing L of grid and source electrodeGS=2.5 μm,
Drain electrode and the spacing L of source electrodeDS=5.4 μm；
This example sets but is not limited to grid, the length respectively L of source electrode and drain electrodeG=0.4 μm, LS=0.5 μm, LD=0.5
μm；
The tested device that the present invention is applied meets LGD＞ 5LG, LGS＞ 5LG, the trap pair in device barrier layer can be neglected
The capture effect of electronics at gate interface.
Step 2, connecting test circuit.
Reference picture 2, one end of source S is connected with drain D, and the other end is connected with the second ammeter A2, by the one of grid G
End is connected with pulse power E and the first ammeter A1 successively, and the second ammeter A2 and pulse power E other end is grounded.
Step 3, the electron amount of capture/release when barrier layer internal trap is filled up to dynamic equilibrium is calculated.
Whether reference picture 3, reading and judgement capture capture/release electronics of this step to ammeter registration reaches dynamic
The specific testing procedure of balance is as follows：
3a) first apply the pulse voltage in P cycle in the grid G of tested device, the high level of the pulse voltage is
VH, low-voltage put down as VL, high pulse width is WH, low-level pulse width is WL, pulse period T=WH+WL；Read the first electricity respectively again
Flow table A1 registration IG(t) with the second ammeter A2 registration IDS(t)；
3b) apply 0V low level pulse to tested device grid G, obtain barrier layer trap trapped electron electric current I (t)
=IG(t)-IDS(t), and provide the sense of current of barrier layer trap trapped electron formation for just；
0V high level pulse 3c) is applied more than to tested device grid G, barrier layer trap release electronic current is obtained
I (t)=- | IG(t)-IDS(t) |, and the sense of current that the release of regulation barrier layer trap is electronically formed is negative；
3e) according to the relation of the quantity of electric charge and electric current, the P pulse period internals barrier layer trap capture/release of calculating
Electron amount N (P):
Calculate the electron amount N (P-1) of the P-1 pulse period internals barrier layer trap capture/release：
Wherein P is positive integer, and T is the pulse period；E is electron charge, and its size is 1 × 10-19C；
3f) calculation procedure 3e) in the P pulse period internals barrier layer trap capture/release electron amount N (P)
With the electron amount N (P-1) of the P-1 pulse period internals barrier layer trap capture/release relative error, barrier layer is judged
Whether trap capture capture/release electron amount reaches dynamic equilibrium：
IfThen judge that barrier layer trap capture capture/release electron amount reaches dynamic equilibrium,
Stop applying pulse voltage, total electron amount of the barrier layer internal trap capture of note now is N=N (P)；
Conversely, not up to dynamic equilibrium, then continue executing with step 3a) to 3e), until meeting capture/release electron amount
Dynamic equilibrium condition.
Step 4, distribution of the barrier layer internal trap trapped electron quantity in different low-level pulse width intervals is calculated.
This step obtains the specific test step of barrier layer internal trap trapped electron number change by changing low level width
It is rapid as follows：
The low level width for 4a) changing pulse voltage successively is WL(1), WL(2), WL(3)..., WL(m), and keep pulse electricity
The pulse high level V of pressureH, pulses low VLAnd high pulse width WHConstant, all testing procedures of repeat step 3 are remembered successively
Record total electron amount N of barrier layer internal trap captureWL(k), obtain barrier layer internal trap trapped electron quantity and become with low-level pulse width
Change schematic diagram, wherein such as Fig. 4, WL(1)<WL(2)<WL(3)<...<WL(m), k=1,2,3 ..., m, m is positive integer；
4b) according to step 4a), barrier layer internal trap is obtained in WL(k-1)-WL(k)Low-level pulse width between capture electricity
Quantum count is：ΔNWL(k)=NWL(k)-NWL(k-1), wherein NWL(k-1)Low level width for -1 change pulse voltage of kth is obtained
Barrier layer internal trap capture total electron amount, NWL(k)The potential barrier that the low level width for changing pulse voltage for kth time is obtained
Total electron amount of layer internal trap capture；
4c) according to step 4b) formula obtain as shown in Figure 5 in different low-level pulse width interval inner potential barrier layer internal traps
Trapped electron amount Δ NWL(k)Distribution situation, according to the theory of Semiconductor Physics, the trapped electron applied to device under test
The time of pulse is exactly the when constant of trap trapped electron, therefore Fig. 5 constant internal trap capture electricity when substantially characterizing different
Quantum count Δ NWL(k)Distribution situation.
Step 5, distribution of the barrier layer internal trap release electron amount in different high pulse width intervals is calculated.
This step obtains the realization of barrier layer internal trap trapped electron number change by changing low level width, and its step is such as
Under：
The high level width for 5a) changing pulse voltage successively is WH(1), WH(2), WH(3)..., WH(m), and keep pulse electricity
The pulse high level V of pressureH, pulses low VLAnd low-level pulse width WLConstant, all testing procedures of repeat step 3 are remembered successively
Record total electron amount N of barrier layer internal trap captureWH(k), obtain barrier layer internal trap release electron amount and become with high pulse width
Change schematic diagram, wherein such as Fig. 6, WH(1)<WH(2)<WH(3)<...<WH(m), k=1,2,3 ..., m, m is positive integer；
5b) according to step 5a), barrier layer internal trap is obtained in WH(k-1)-WH(k)High pulse width between the electronics that discharges
Quantity is：ΔNWH(k)=NWH(k-1)-NWH(k), wherein NWH(k)The potential barrier that the high level width for changing pulse voltage for kth time is obtained
Total electron amount of layer internal trap release, NWH(k-1)The barrier layer obtained for the high level width of -1 change pulse voltage of kth
Total electron amount of internal trap release；
5c) according to step 5b) formula, obtain the barrier layer as shown in Figure 7 between different high pulse widths and cave in
The electron amount Δ N of trap releaseWH(k)Distribution situation；According to the theory of Semiconductor Physics, the release electricity applied to device under test
The time of the pulse width of son is exactly the when constant that trap discharges electronics, thus Fig. 7 when substantially characterizing different constant cave in
Trap release electronics Δ NWH(k)Distribution situation.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, it is clear that for this area
Professional for, after present disclosure and principle is understood, can modify within the spirit and principles in the present invention,
Equivalent substitution and improvement etc., for example, resolution chart of the present invention is to be based on III-IV compound semiconductor hetero-junctions
Transistor device prepared by material, can equally be well applied to the semiconductor devices with ohmic contact regions prepared by other race's elements,
The MOS device that for example prepared by Si, Ge material.These modifications, equivalent substitutions and improvements made should be included in the guarantor of the present invention
Within the scope of shield.
Claims (4)
1. a kind of barrier layer internal trap distribution characterizing method of feature based time constant, comprises the following steps：
1) tested device is made：Prepared from bottom to top successively using heterogenous junction epitaxy technique substrate, nucleating layer, cushion, insert
Enter layer and barrier layer, then metal electrode is deposited on semi-conducting material, prepare source S and drain D, grid are prepared between source and drain
The spacing of pole G, note pole grid and drain electrode is LGD, the spacing of grid and source electrode is LGS, drain and the spacing of source electrode be LDS, grid, source
The length of pole and three electrodes that drain is respectively LG, LS, LD；
2) connecting test circuit：One end of source S is connected with drain D, the other end is connected with the second ammeter A2, by grid G
One end be connected successively with pulse power E and the first ammeter A1, the second ammeter A2 and pulse power E other end is connect
Ground；
3) electron amount of capture/release when barrier layer internal trap is filled up to dynamic equilibrium is calculated：
3a) apply the pulse voltage in P cycle in the grid G of tested device, the pulse high level of pulse voltage is VH, it is low
Voltage is put down as VL, high pulse width be WHLow-level pulse width is WLAnd pulse period T=WH+WL.The first ammeter A1 is read respectively
Registration IG(t) with the second ammeter A2 registration IDS(t)；
3b) apply 0V low level pulse to tested device grid G, obtain barrier layer trap trapped electron electric current I (t)=IG
(t)-IDS(t), and provide the sense of current of barrier layer trap trapped electron formation for just；
0V high level pulse 3c) is applied more than to tested device grid G, barrier layer trap release electronic current I (t) is obtained
=-| IG(t)-IDS(t) |, and the sense of current that the release of regulation barrier layer trap is electronically formed is negative；
3e) according to the relation of the quantity of electric charge and electric current, P and the P-1 pulse period internals barrier layer trap capture/release are calculated
Electron amount be respectively：
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Wherein P is positive integer, and T is the pulse period；E is electron charge, and its size is 1 × 10-19C；
3f) calculation procedure 3e) in the P pulse period internals barrier layer trap capture/release electron amount N (P) and
The electron amount N (P-1) of P-1 pulse period internals barrier layer trap capture/release relative error, judges barrier layer trap
Whether capture/release electron amount reaches dynamic equilibrium：
IfThen judge that barrier layer trap is captured/discharged electron amount and reaches dynamic equilibrium, stop applying
Pulse voltage, total electron amount of the barrier layer internal trap capture/release of note now is N=N (P)；
Conversely, not up to dynamic equilibrium, then continue executing with step 3a) to 3e), until meeting capture/release electron amount dynamic
Equilibrium condition；
4) distribution of the barrier layer internal trap trapped electron quantity in different low-level pulse width intervals is calculated：
4a) be varied multiple times the low level width of pulse voltage, keep the other specification of pulse voltage constant, repeat step 3) institute
There is testing procedure, total electron amount N of barrier layer internal trap capture is recorded successivelyWL(k), wherein k=1,2,3 ..., m；
4b) according to step 4a), barrier layer internal trap is obtained in WL(k-1)-WL(k)Low-level pulse width interval in capture electron number
Measure and be：ΔNWL(k)=NWL(k)-NWL(k-1), wherein, NWL(k-1)The gesture obtained for the low level width of -1 change pulse voltage of kth
Total electron amount of barrier layer internal trap capture, NWL(k)In the barrier layer that the low level width for changing pulse voltage for kth time is obtained
Total electron amount of trap capture；
5) distribution of the barrier layer internal trap release electron amount in different high pulse width intervals is calculated：
5a) be varied multiple times the high level width of pulse, keep the other specification of pulse voltage constant, repeat step 3) all surveys
Try is rapid, and total electron amount N of barrier layer internal trap release is recorded successivelyWH(k)；
5b) according to step 5a), barrier layer internal trap is obtained in WH(k)-WH(k-1)High pulse width interval in discharge electron number
Measure and be：ΔNWH(k)=NWH(k)-NWH(k-1), wherein, NWH(k-1)The gesture obtained for the high level width of -1 change pulse voltage of kth
Total electron amount of barrier layer internal trap release, NWH(k)In the barrier layer that the high level width for changing pulse voltage for kth time is obtained
Total electron amount of trap release.
2. according to the method described in claim 1, wherein in step 1 grid and source electrode spacing LGSAnd grid and the spacing of drain electrode
LGDIt is all higher than 5 times of grid length LG, i.e.,：LGD＞ 5LG, LGS＞ 5LG, to ignore the trap in device barrier layer to gate interface
Locate the capture effect of electronics.
3. according to the method described in claim 1, wherein step 4a) in the low level width of pulse voltage is varied multiple times, keep
The other specification of pulse voltage is constant, is to maintain the pulse high level V of device under test applicationH, pulses low VLAnd high level arteries and veins
Wide WHConstant, it is W to change low-level pulse width successivelyL(1), WL(2), WL(3)..., WL(m), wherein WL(1)<WL(2)<WL(3)<...<
WL(m), and descend repeat step 3 successively in the condition of these low-level pulse widths) all test operations, obtain different low level arteries and veins
Wide WL(k)Total electron amount N of lower barrierlayer internal trap captureWL(k)。
4. according to the method described in claim 1, wherein step 5a) in the high level width of pulse voltage is varied multiple times, keep
The other specification of pulse voltage is constant, is to maintain the pulse high level V of device under test applicationH, pulses low VLAnd low level arteries and veins
Wide WLConstant, it is W to change high pulse width successivelyH(1), WH(2), WH(3)..., WH(m), and these high pulse widths condition according to
Secondary lower repeat step 3) all test operations, obtain different high pulse width WH(k)Total electronics of lower barrierlayer internal trap release
Quantity NWH(k), wherein WH(1)<WH(2)<WH(3)<...<WH(m)。
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