CN107219448A - The barrier layer internal trap distribution characterizing method of constant during feature based - Google Patents

Abstract

The invention discloses a trap distribution characterization method in a potential barrier layer based on characteristic time constants. It mainly solves the problem that the prior art cannot measure the total number of trapped/released electrons in the barrier layer below the gate of the device, and cannot characterize the distribution of the electrons as the pulse width interval changes. The implementation plan is: apply a pulse voltage on the prepared semiconductor device to be tested, and monitor the current representation in the circuit; then obtain the number of trapped/released electrons in the barrier layer of the device through mathematical calculation; and then change the pulse level by multiple times The pulse width of the level can be used to obtain the distribution of the number of electrons captured/released by the trap as the pulse width interval changes. The invention has the advantages of simple testing process and testing equipment and reliable results, and can be used for process optimization and reliability analysis of microelectronic devices and research on current collapse mechanism.

Description

Characterization Method of Traps Distribution in Barrier Layer Based on Characteristic Time Constant

technical field

The invention belongs to the field of microelectronic testing, in particular to a characteristic time constant-based trap distribution characterization method in a barrier layer, which is used for heterojunction transistors, especially wide bandgap semiconductor devices represented by III-V materials Process optimization and reliability analysis.

Background technique

Wide-bandgap semiconductor materials represented by III-V materials have many advantages. The heterojunction transistor devices prepared by them have the advantages of large working current and fast working speed. The field has huge advantages and broad application prospects. Therefore, this type of device has become a research hotspot since its birth.

Semiconductor device technology is developing rapidly, but driven by high frequency and large signals, the output current swing of microelectronic devices decreases sharply, and the output power density decreases. This phenomenon is called the current collapse effect. Devices in harsh environments such as high temperature and high voltage and high-power applications will also have phenomena such as leakage current drop and threshold voltage drift, which seriously affect the stability of the device. It is the pitfalls introduced into the barrier layer in different usage environments. Therefore, measuring the number of trapped electrons in the barrier layer in the device can evaluate the influence of the barrier layer traps on the degradation, and then optimize the device manufacturing process and improve the reliability of the device.

The traditional method of measuring device current collapse is to use a semiconductor parameter analyzer to conduct DC or pulse tests on heterojunction semiconductor devices, and obtain the current collapse by comparing the maximum output current under different pulse voltages and DC voltages. However, this method cannot obtain The total number of traps in the barrier layer under the device gate and the distribution of the number of trapped/released electrons in different pulse width intervals, so it is impossible to optimize the manufacturing process of heterojunction semiconductor devices, affecting the heterojunction The stability of semiconductor devices.

Contents of the invention

The object of the present invention is to address the shortcomings of the above-mentioned prior art, and propose a trap distribution characterization method in the barrier layer based on characteristic time constants, so as to optimize the manufacturing process of heterojunction semiconductor devices and improve the working stability of the devices.

To achieve the above object, the technical solution of the present invention comprises the following steps:

1) Make the device to be tested: use the heterojunction epitaxy process to prepare the substrate, nucleation layer, buffer layer, insertion layer and barrier layer sequentially from bottom to top, and then deposit metal electrodes on the semiconductor material to prepare the source S and the drain D, prepare the gate G between the source and the drain, record the distance between the gate and the drain as L _GD , the distance between the gate and the source as L _GS , the distance between the drain and the source as L _DS , and the distance between the gate and the drain as L DS . The lengths of the pole, source and drain electrodes are L _G , L _S , L _D respectively;

2) Connect the test circuit: connect one end of the source S to the drain D, and the other end to the second ammeter A2, connect one end of the gate G to the pulse power supply E and the first ammeter A1 in turn, and connect the second ammeter A2 and the other end of the pulse power supply E are grounded;

3) Calculate the number of electrons captured/released during the dynamic equilibrium of trap filling in the barrier layer:

3a) Apply a pulse voltage of P cycles on the gate G of the device to be tested, the pulse voltage of the pulse high level is V _H , the low voltage level is V _L , and the high level pulse width is W _H and the low level pulse width W _L and the pulse period T=W _H +W _L . Read out the indication I _G (t) of the first ammeter A1 and the indication I _DS (t) of the second ammeter A2 respectively;

3b) Apply a low-level pulse of 0V to the gate G of the device to be tested, and obtain the electron current I(t) = I _G (t)-I _DS (t) trapped in the barrier layer traps, and stipulate that the trapped electrons in the barrier layer form The direction of the current is positive;

3c) Apply a high-level pulse greater than 0V to the gate G of the device to be tested, and obtain the barrier layer trap release electron current I(t)=-|I _G (t)-I _DS (t)|, and specify the barrier layer The direction of the current formed by the release of electrons from the trap is negative;

3e) According to the relationship between the amount of charge and the current, calculate the number of electrons trapped/released by the device barrier layer traps in the Pth and P-1th pulse periods, respectively:

Among them, P is a positive integer, T is the pulse period; e is the electron charge, and its size is 1×10 ^-19 C;

3f) Calculate the relative error of N(P) and N(P-1) measured in step 3e), and determine whether the number of trapped/released electrons in the barrier layer trap reaches a dynamic balance:

like Then it is determined that the number of trapped/released electrons in the barrier layer traps reaches a dynamic balance, and the application of the pulse voltage is stopped, and the total number of electrons captured/released by the traps in the barrier layer at this time is N=N(P);

On the contrary, if the dynamic balance is not reached, then continue to perform steps 3a) to 3e), until the dynamic balance condition of the number of captured/released electrons is met;

4) Calculate the distribution of the number of trapped electrons in the barrier layer in different low-level pulse width intervals:

4a) Change the low-level width of the pulse voltage multiple times, keep other parameters of the pulse voltage constant, repeat all the test steps in step 3), and record the total number of electrons N _WL(k) captured by traps in the barrier layer in turn, where k=1, 2, 3, ..., m;

4b) According to step 4a), the number of electrons captured by traps in the barrier layer between the low-level pulse width of W _L(k-1) -W _L(k) is:

ΔN _WL(k) =N _WL(k-1) -N _WL(k) ,

Among them, N _WL(k-1) is the total number of electrons captured by traps in the barrier layer obtained by changing the low-level width of the pulse voltage for the k-1th time, and N WL( _k ) is the low-level width of the pulse voltage for the k-th time. The total number of electrons captured by the traps in the barrier layer obtained by the level width;

5) Calculate the distribution of the number of traps releasing electrons in the barrier layer at different high-level pulse width intervals:

5a) changing the high-level width of the pulse multiple times, keeping other parameters of the pulse voltage constant, repeating all the test steps of step 3), and recording the total number of electrons N _{WH (k)} released by traps in the barrier layer in turn;

5b) According to step 5a), the number of electrons released by traps in the potential barrier layer between the high-level pulse width of W _H(k) -W _H(k-1) is: ΔN _WH(k) =N _{WH( k)} -N _WH(k-1) , wherein, N _WH(k-1) is the total number of electrons trapped in the barrier layer obtained by changing the high level width of the pulse voltage for the k-1th time, N _{WH( k)} is the total number of electrons released by traps in the barrier layer obtained by changing the high-level width of the pulse voltage for the kth time.

Compared with the prior art, the present invention has the following advantages:

1) The distribution of trapped/released electrons can be directly characterized.

The present invention can not only directly obtain the total number of electrons captured by the barrier layer under the grid through measurement and calculation, but also obtain the distribution of the number of electrons trapped in the barrier layer in different low-level pulse width intervals, and the The distribution of the number of electrons released by traps in the barrier layer within the pulse width interval reflects the distribution of the number of traps in the barrier layer in different low and high pulse width intervals;

2) The test equipment and test process are simple.

The test equipment and test process required by the present invention are very simple. It only needs to monitor the two current representations in the process of applying the pulse voltage, and then quickly process the test data through simple mathematical formulas to obtain the barrier layer under the gate of the test device. The number of electrons captured by the trap;

3) In the present invention, since the interval of the pulse width applied to the device is the time constant of the trap trapping and releasing electrons, the distribution of the trap trapping and releasing electron quantity time constants can be obtained by testing under different pulse widths.

Description of drawings

Fig. 1 is the realization flowchart of the present invention;

Fig. 2 is a test circuit schematic diagram of the present invention;

Fig. 3 is a schematic diagram of the real-time change of the current representation number during the application of P pulses in Fig. 1;

Fig. 4 is a schematic diagram of the variation of the number of trapped electrons in the barrier layer with the low-level pulse width in the present invention;

Fig. 5 is a schematic diagram of the time constant distribution of trapped electrons in the barrier layer in the present invention as it changes with the low-level pulse width;

Fig. 6 is a schematic diagram of the number of electrons released from traps in the barrier layer of the present invention changing with the high-level pulse width;

Fig. 7 is a schematic diagram of the time constant distribution of traps releasing electrons in the barrier layer according to the variation of the high-level pulse width in the present invention.

detailed description

The specific implementation of the present invention will be further described in detail below in conjunction with the accompanying drawings and examples. The examples are used to illustrate the present invention, but not to limit the scope of the present invention.

Referring to Figure 1, the specific implementation of this step is as follows:

Step 1, making the device to be tested.

1a) The substrate, nucleation layer, buffer layer, insertion layer and barrier layer are sequentially prepared from bottom to top by using a heterojunction epitaxy process;

1b) Then deposit a metal electrode on the barrier layer to prepare the source S and the drain D, and prepare the gate G between the source and the drain. Note that the distance between the gate and the drain is L _GD , and the distance between the gate and the source is The distance between the drain and the source is L _GS , the distance between the drain and the source is L _DS , and the lengths of the gate, source and drain electrodes are L _G , L _S , and L _D ;

In this example, it is assumed, but not limited to, that the distance between the gate and the drain L _GD =2.5 μm, the distance between the gate and the source L _GS =2.5 μm, and the distance between the drain and the source L _DS =5.4 μm;

In this example, it is assumed but not limited to that the lengths of the gate, source and drain are L _G =0.4 μm, L _S =0.5 μm, L _D =0.5 μm;

The device to be tested applied in the present invention satisfies _LGD >5L _G , LG _GS >5L _G , and traps in the barrier layer of the device can ignore the trapping effect of electrons at the gate interface.

Step 2, connect the test circuit.

Referring to Figure 2, connect one end of the source S to the drain D, and the other end to the second ammeter A2, connect one end of the gate G to the pulse power supply E and the first ammeter A1 in sequence, and connect the second ammeter A2 to the pulse The other ends of the power supply E are all grounded.

Step 3, calculate the number of electrons captured/released when the trap filling in the barrier layer reaches a dynamic equilibrium.

Referring to Figure 3, in this step, the specific test steps for reading the number of current indications and determining whether the captured/released electrons have reached a dynamic balance are as follows:

3a) First apply a pulse voltage of P cycles on the gate G of the device to be tested. The high level of the pulse voltage is V _H , the low voltage level is V _L , the high level pulse width is W _H , and the low level is V H . The pulse width is W _L , the pulse period T=W _H +W _L ; then read out the indication I _G (t) of the first ammeter A1 and the indication I _DS (t) of the second ammeter A2 respectively;

3b) Apply a low-level pulse of 0V to the gate G of the device to be tested, and obtain the electron current I(t) = I _G (t)-I _DS (t) trapped in the barrier layer traps, and stipulate that the trapped electrons in the barrier layer form The direction of the current is positive;

3c) Apply a high-level pulse greater than 0V to the gate G of the device to be tested, and obtain the barrier layer trap release electron current I(t)=-|I _G (t)-I _DS (t)|, and specify the barrier layer The direction of the current formed by the release of electrons from the trap is negative;

3e) According to the relationship between the amount of charge and the current, calculate the number N(P) of electrons captured/released by the barrier layer traps in the Pth pulse period:

Calculate the number N(P-1) of electrons captured/released by traps in the barrier layer of the internal device in the P-1th pulse period:

Among them, P is a positive integer, T is the pulse period; e is the electron charge, and its size is 1×10 ^-19 C;

3f) Calculating the number N(P) of electrons captured/released by the traps in the barrier layer in the Pth pulse period and the number N of electrons captured/released in the traps in the barrier layer in the P-1th pulse period in step 3e) The relative error of (P-1) determines whether the number of captured/released electrons in the barrier layer traps has reached a dynamic balance:

like Then it is determined that the number of trapped/released electrons captured by the traps in the barrier layer reaches a dynamic balance, and the application of the pulse voltage is stopped, and the total number of electrons captured by the traps in the barrier layer at this time is N=N(P);

On the contrary, if the dynamic balance is not reached, continue to perform steps 3a) to 3e) until the dynamic balance condition of the number of captured/released electrons is met.

Step 4, calculating the distribution of the number of trapped electrons in the potential barrier layer in different low-level pulse width intervals.

In this step, the specific test steps to obtain the change in the number of trapped electrons in the barrier layer by changing the width of the low level are as follows:

4a) Change the low-level width of the pulse voltage to W _L(1) , W _L(2) , W _L(3) ,..., W _L(m) in sequence, and keep the pulse high level of the pulse voltage V _H , pulse low-level V _L and high-level pulse width W _H remain unchanged, repeat all the test steps in step 3, record the total number of electrons N _WL(k) captured by traps in the barrier layer in sequence, and obtain Schematic diagram of the number of trapped electrons changing with the low-level pulse width, as shown in Figure 4, where W _L(1) <W _L(2) <W _L(3) <...<W _L(m) , k=1, 2, 3, ..., m, m is a positive integer;

4b) According to step 4a), the number of electrons captured by traps in the barrier layer between the low-level pulse width of W _L(k-1) -W _L(k) is: ΔN _WL(k) =N _{WL (k)} -N _WL(k-1) , where N _WL(k-1) is the total number of electrons trapped in the barrier layer obtained by changing the low-level width of the pulse voltage for the k-1th time, N _{WL( k)} is the total number of electrons captured by traps in the barrier layer obtained by changing the low-level width of the pulse voltage for the kth time;

4c) According to the formula in step 4b), the distribution of the number of trapped electrons ΔN _WL(k) in the barrier layer in different low-level pulse width intervals as shown in Figure 5 is obtained. According to the theory of semiconductor physics, for the The time of the electron-trapping pulse applied by the device is the time constant of trapping electrons, so Fig. 5 essentially characterizes the distribution of the number of trapping electrons ΔN _WL(k) in different time constants.

Step 5, calculating the distribution of the number of electrons released from traps in the barrier layer in different high-level pulse width intervals.

This step is achieved by changing the width of the low level to obtain the change in the number of trapped electrons in the barrier layer, and the steps are as follows:

5a) Change the high-level width of the pulse voltage to W _H(1) , W _H(2) , W _H(3) ,..., W _H(m) in sequence, and keep the pulse high level of the pulse voltage V _H , pulse low-level V _L and low-level pulse width W _L remain unchanged, repeat all the test steps in step 3, record the total number of electrons N _WH(k) captured by traps in the barrier layer in turn, and obtain Schematic diagram of the number of traps releasing electrons changing with the high-level pulse width, as shown in Figure 6, where W _H(1) <W _H(2) <W _H(3) <...<W _H(m) , k=1, 2, 3, ..., m, m is a positive integer;

5b) According to step 5a), the number of electrons released by traps in the barrier layer between the high-level pulse width of W _H(k-1) -W _H(k) is: ΔN _WH(k) =N _{WH( k-1)} -N _WH(k) , where N _WH(k) is the total number of electrons released by traps in the barrier layer obtained by changing the high level width of the pulse voltage for the kth time, N _WH(k-1) is The total number of electrons released by traps in the barrier layer obtained by changing the high-level width of the pulse voltage for the k-1th time;

5c) According to the formula of step 5b), the distribution of the number of electrons ΔN _{WH (k)} released by traps in the barrier layer between different high-level pulse widths as shown in Figure 7 is obtained; according to the theory of semiconductor physics, The time constant of the pulse width of releasing electrons applied to the device under test is the time constant of trap releasing electrons, so Figure 7 essentially characterizes the distribution of trap releasing electrons ΔN _WH(k) in different time constants.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. Obviously, for those skilled in the art, after understanding the content and principle of the present invention, within the spirit and principles of the present invention Modifications, equivalent replacements and improvements can be made. For example, the test pattern used in the present invention is based on the transistor device prepared by III-IV compound semiconductor heterojunction materials, and is also applicable to transistor devices with ohmic contact regions prepared by other group elements. Semiconductor devices, such as MOS devices made of Si and Ge materials. These modifications, equivalent replacements and improvements shall all be included within the protection scope of the present invention.

Claims (4)

1. a kind of barrier layer internal trap distribution characterizing method of feature based time constant, comprises the following steps：

1) tested device is made：Prepared from bottom to top successively using heterogenous junction epitaxy technique substrate, nucleating layer, cushion, insert Enter layer and barrier layer, then metal electrode is deposited on semi-conducting material, prepare source S and drain D, grid are prepared between source and drain The spacing of pole G, note pole grid and drain electrode is L_GD, the spacing of grid and source electrode is L_GS, drain and the spacing of source electrode be L_DS, grid, source The length of pole and three electrodes that drain is respectively L_G, L_S, L_D；

2) connecting test circuit：One end of source S is connected with drain D, the other end is connected with the second ammeter A2, by grid G One end be connected successively with pulse power E and the first ammeter A1, the second ammeter A2 and pulse power E other end is connect Ground；

3) electron amount of capture/release when barrier layer internal trap is filled up to dynamic equilibrium is calculated：

3a) apply the pulse voltage in P cycle in the grid G of tested device, the pulse high level of pulse voltage is V_H, it is low Voltage is put down as V_L, high pulse width be W_HLow-level pulse width is W_LAnd pulse period T=W_H+W_L.The first ammeter A1 is read respectively Registration I_G(t) with the second ammeter A2 registration I_DS(t)；

3b) apply 0V low level pulse to tested device grid G, obtain barrier layer trap trapped electron electric current I (t)=I_G (t)-I_DS(t), and provide the sense of current of barrier layer trap trapped electron formation for just；

0V high level pulse 3c) is applied more than to tested device grid G, barrier layer trap release electronic current I (t) is obtained =-| I_G(t)-I_DS(t) |, and the sense of current that the release of regulation barrier layer trap is electronically formed is negative；

3e) according to the relation of the quantity of electric charge and electric current, P and the P-1 pulse period internals barrier layer trap capture/release are calculated Electron amount be respectively：

<mrow> <mi>N</mi> <mrow> <mo>(</mo> <mi>P</mi> <mo>)</mo> </mrow> <mo>=</mo> <mfrac> <mrow> <msubsup> <mo>&amp;Integral;</mo> <mn>0</mn> <mrow> <mi>P</mi> <mi>T</mi> </mrow> </msubsup> <mi>I</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mi>d</mi> <mi>t</mi> </mrow> <mi>e</mi> </mfrac> <mo>,</mo> <mi>N</mi> <mrow> <mo>(</mo> <mi>P</mi> <mo>-</mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>=</mo> <mfrac> <mrow> <msubsup> <mo>&amp;Integral;</mo> <mn>0</mn> <mrow> <mo>(</mo> <mi>P</mi> <mo>-</mo> <mn>1</mn> <mo>)</mo> <mi>T</mi> </mrow> </msubsup> <mi>I</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mi>d</mi> <mi>t</mi> </mrow> <mi>e</mi> </mfrac> <mo>,</mo> </mrow>

Wherein P is positive integer, and T is the pulse period；E is electron charge, and its size is 1 × 10^-19C；

3f) calculation procedure 3e) in the P pulse period internals barrier layer trap capture/release electron amount N (P) and The electron amount N (P-1) of P-1 pulse period internals barrier layer trap capture/release relative error, judges barrier layer trap Whether capture/release electron amount reaches dynamic equilibrium：

IfThen judge that barrier layer trap is captured/discharged electron amount and reaches dynamic equilibrium, stop applying Pulse voltage, total electron amount of the barrier layer internal trap capture/release of note now is N=N (P)；

Conversely, not up to dynamic equilibrium, then continue executing with step 3a) to 3e), until meeting capture/release electron amount dynamic Equilibrium condition；

4) distribution of the barrier layer internal trap trapped electron quantity in different low-level pulse width intervals is calculated：

4a) be varied multiple times the low level width of pulse voltage, keep the other specification of pulse voltage constant, repeat step 3) institute There is testing procedure, total electron amount N of barrier layer internal trap capture is recorded successively_WL(k), wherein k=1,2,3 ..., m；

4b) according to step 4a), barrier layer internal trap is obtained in W_L(k-1)-W_L(k)Low-level pulse width interval in capture electron number Measure and be：ΔN_WL(k)=N_WL(k)-N_WL(k-1), wherein, N_WL(k-1)The gesture obtained for the low level width of -1 change pulse voltage of kth Total electron amount of barrier layer internal trap capture, N_WL(k)In the barrier layer that the low level width for changing pulse voltage for kth time is obtained Total electron amount of trap capture；

5) distribution of the barrier layer internal trap release electron amount in different high pulse width intervals is calculated：

5a) be varied multiple times the high level width of pulse, keep the other specification of pulse voltage constant, repeat step 3) all surveys Try is rapid, and total electron amount N of barrier layer internal trap release is recorded successively_WH(k)；

5b) according to step 5a), barrier layer internal trap is obtained in W_H(k)-W_H(k-1)High pulse width interval in discharge electron number Measure and be：ΔN_WH(k)=N_WH(k)-N_WH(k-1), wherein, N_WH(k-1)The gesture obtained for the high level width of -1 change pulse voltage of kth Total electron amount of barrier layer internal trap release, N_WH(k)In the barrier layer that the high level width for changing pulse voltage for kth time is obtained Total electron amount of trap release.

2. according to the method described in claim 1, wherein in step 1 grid and source electrode spacing L_GSAnd grid and the spacing of drain electrode L_GDIt is all higher than 5 times of grid length L_G, i.e.,：L_GD＞ 5L_G, L_GS＞ 5L_G, to ignore the trap in device barrier layer to gate interface Locate the capture effect of electronics.

3. according to the method described in claim 1, wherein step 4a) in the low level width of pulse voltage is varied multiple times, keep The other specification of pulse voltage is constant, is to maintain the pulse high level V of device under test application_H, pulses low V_LAnd high level arteries and veins Wide W_HConstant, it is W to change low-level pulse width successively_L(1), W_L(2), W_L(3)..., W_L(m), wherein W_L(1)<W_L(2)<W_L(3)<...< W_L(m), and descend repeat step 3 successively in the condition of these low-level pulse widths) all test operations, obtain different low level arteries and veins Wide W_L(k)Total electron amount N of lower barrierlayer internal trap capture_WL(k)。

4. according to the method described in claim 1, wherein step 5a) in the high level width of pulse voltage is varied multiple times, keep The other specification of pulse voltage is constant, is to maintain the pulse high level V of device under test application_H, pulses low V_LAnd low level arteries and veins Wide W_LConstant, it is W to change high pulse width successively_H(1), W_H(2), W_H(3)..., W_H(m), and these high pulse widths condition according to Secondary lower repeat step 3) all test operations, obtain different high pulse width W_H(k)Total electronics of lower barrierlayer internal trap release Quantity N_WH(k), wherein W_H(1)<W_H(2)<W_H(3)<...<W_H(m)。