CN103367193B - The method of testing of gate oxide trap density and position and device - Google Patents
The method of testing of gate oxide trap density and position and device Download PDFInfo
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- CN103367193B CN103367193B CN201310314338.XA CN201310314338A CN103367193B CN 103367193 B CN103367193 B CN 103367193B CN 201310314338 A CN201310314338 A CN 201310314338A CN 103367193 B CN103367193 B CN 103367193B
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Abstract
The invention provides and the method for testing of a kind of gate oxide trap density and position and device, relate to MOS device quality, reliability testing technical field.This method comprises step: S1, source and drain terminal access negative voltage, substrate terminal ground connection, make pn tie forward bias; After S2, pn tie forward bias, at grid access direct grid current scanning voltage, scan by the method being pressed onto positive voltage from negative electricity, make device surface become weak anti-type state from accumulated state; In scanning process, substrate terminal is measured, obtain substrate current; S3, set up an I-V curve of substrate current and direct grid current scanning voltage; S4, a fixed voltage is applied to grid, repeat step S1 ~ S3 many times, obtain many articles of the 2nd I-V curves; By the measurement to many articles of the 2nd I-V curve bottom level, obtain the trap density of pn knot.The present invention can measure the trap density of pn knot and position the position of trap, and then improves device layout, reduces the generation of trap.
Description
Technical field
The present invention relates to MOS device quality, reliability testing technical field, be specifically related to method of testing and the device of a kind of gate oxide trap density and position.
Background technology
Along with the develop rapidly of semiconductor technology and the significantly raising of microelectronic chip integrated level, the design of integrated circuit and level of processing have entered the nanoscale MOS epoch, gate oxide is as the core of MOS device, in MOS device quality, reliability assessment, have very important effect, wherein the interface trap density of gate oxide is one of very important index.The generation of gate oxide interface trap makes device mobility decline, and causes device performance to reduce, and therefore, is very necessary in technological process to the monitoring of gate oxide interface trap.
Conventional gate oxide interface trap density testing apparatus is oxide layer capacitance structure or MOSFET(metal-oxide half field effect transistor) device, a two ends capacitor structure comprising grid and substrate, or the four end MOSFET element structures comprising source electrode, grid, drain electrode and substrate.The method of testing of the routine of the interface trap density of gate oxide is that the gate oxide testing apparatus of for n-type and p-type MOS device is respectively measured.Number of patent application is 201110397002.5 applications for a patent for invention, refer to a kind of gate oxide interface trap density testing apparatus and method of testing, adopts same testing apparatus to complete test to n and p-type MOS device gate oxide interface trap density.
But above-mentioned method of testing, the index paid close attention to is only limitted to the density of the gate oxide interface trap of N-shaped and p-type MOS device, lack the density measurement near interface trap, particularly do not consider the trap density that pn ties, and pn ties the position distribution situation of trap.
Summary of the invention
(1) technical problem solved
For the deficiencies in the prior art, the invention provides method of testing and the device of a kind of gate oxide trap density and position, the trap density of pn knot can be measured.
(2) technical scheme
For realizing above object, the present invention is achieved by the following technical programs:
A method of testing for gate oxide trap density and position, is characterized in that, comprises the following steps:
S1, source and drain terminal access negative voltage, substrate terminal ground connection, make pn tie forward bias;
After S2, described pn tie forward bias, at grid access direct grid current scanning voltage, scan according to the method being pressed onto positive voltage from negative electricity, make device surface be transformed to weak anti-type state from accumulated state; In described direct grid current scanning voltage scanning process, described substrate terminal is measured, obtain substrate current;
S3, set up an I-V curve of described substrate current and described direct grid current scanning voltage;
S4, a fixed voltage is applied to described grid, then repeat step S1 ~ S3 many times, obtain many articles of described substrate currents and described direct grid current scanning voltage the 2nd I-V curve; By the measurement to many articles of the 2nd I-V curve bottom level, obtain the trap density of pn knot.
Preferably, also step S5 is comprised after step S4, with the same subscription interval of described direct grid current scanning voltage, many articles of the 2nd I-V curves in an I-V curve in step S3 and step S4 are sampled, obtain the multiple sampled values on curve, many articles of the 2nd I-V curve sampled values are deducted respectively the sampled value of an I-V curve, obtain the 3rd I-V curve of many articles of described substrate currents and described direct grid current scanning voltage; Obtain described substrate current crest location according to the 3rd I-V curve, this crest location is through-peak peak, by the measurement to through-peak peak value, obtains the trap density of pn knot.
Preferably, after step S5, also comprise step S6, judge that pn ties the positional information of trap by the corresponding relation of described substrate current curve bottom level and described through-peak peak value.
Wherein, judge that the positional information mode of pn knot trap is: if the described substrate current bottom level change observed obviously, pn knot trap mostly concentrates on and is greater than in the region of 0.1um with the distance of device surface; If the change of the described through-peak peak value observed is obvious, pn knot trap mostly concentrates on and is less than in the region of 0.1um with the distance of device surface.
Preferably, the described negative voltage accessed in step S1 is between-0.2V ~-0.5V.
Preferably, the described direct grid current scanning voltage in step S2 is between-1.5V ~ 0.5V.
Preferably, the described fixed voltage in step S4 is 5V.
Present invention also offers a kind of gate oxide trap density and position measurement device, it is characterized in that, comprise the p-type gate oxide capacitance of N-shaped MOSFET and correspondence, or the N-shaped gate oxide capacitance of p-type MOSFET and correspondence; The p-type gate oxide capacitance that described N-shaped MOSFET is corresponding with it, and the N-shaped gate oxide capacitance intersection formation pn knot that p-type MOSFET is corresponding with it;
Wherein, the side of testing apparatus is N-shaped MOSFET, and its n+ adulterates and forms the source electrode of described testing apparatus, and its p+ doping and p well region form the substrate of described testing apparatus, and its grid forms a part for described testing apparatus grid; The opposite side of described testing apparatus is p-type gate oxide capacitance, and its n+ in n-well region adulterates and forms the drain electrode of described testing apparatus, and its grid forms another part of described testing apparatus grid;
Or the side of described testing apparatus is p-type MOSFET, its p+ adulterates and forms the source electrode of described testing apparatus, and its n+ doping and n-well region form the substrate of described testing apparatus, and its grid forms a part for described testing apparatus grid; The opposite side of described testing apparatus is N-shaped gate oxide capacitance, and its p+ at p well region adulterates and forms the drain electrode of described testing apparatus, and its grid forms another part of described testing apparatus grid.
(3) beneficial effect
The present invention, by providing method of testing and the device of a kind of gate oxide trap density and position, by measuring the relation of substrate current and direct grid current scanning voltage, obtains the trap density of pn knot; And then as the index improved device layout, reduce the generation that pn ties trap, reduce the problem because pn knot trap causes device performance to reduce.
The present invention, by measuring the through-peak peak value obtained, also obtains the trap density of pn knot; And then as the index improved device layout.
The present invention is by measuring the relation of substrate current bottom level and through-peak peak value, can in vertical direction the pn near device surface be tied trap and tie trap away from the pn of device surface and make a distinction, obtain the position distribution situation of relevant trap, and then as the index improved device layout.
The trap that the pn of N-shaped gate oxide interface trap, p-type gate oxide interface trap and near interface ties these three kinds, trap dissimilar can make a distinction by the present invention on same device, and the analysis of three kinds of traps is all concentrated in same I-V curve chart study, the information of relevant trap is obtained by the different qualities of curve, very intuitively easy.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is method of testing flow chart in the embodiment of the present invention;
Fig. 2 is another flow chart of method of testing in the embodiment of the present invention;
Two kinds of structural representations that Fig. 3 (a) and (b) are testing apparatus in one embodiment of the invention;
Fig. 4 is that in the embodiment of the present invention, test circuit arranges schematic diagram;
Fig. 5 is along with stress time increases first and second IV curve synoptic diagram tested the substrate current that obtains and change with scanning voltage in the embodiment of the present invention;
Fig. 6 is first and second IV curve synoptic diagram that in the embodiment of the present invention, pn ties the analog result of relation between trap density and substrate current bottom level;
Fig. 7 is for obtain through-peak peak schematic diagram by the 3rd I-V curve;
Fig. 8 is that in the embodiment of the present invention, pn knot trap area arranges schematic diagram;
Fig. 9 is that in the embodiment of the present invention, trap area Length parameter affects schematic diagram for through-peak and substrate current bottom level;
Figure 10 be in the embodiment of the present invention trap area Distance parameter for the schematic diagram of the impact of through-peak and substrate current bottom level.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment 1:
As shown in Figure 1, the method for testing of a kind of gate oxide trap density and position, comprises the following steps:
S1, source and drain terminal access negative voltage, substrate terminal ground connection, make pn tie forward bias;
After S2, described pn tie forward bias, at grid access direct grid current scanning voltage, scan according to the method being pressed onto positive voltage from negative electricity, make device surface be transformed to weak anti-type state from accumulated state; In described direct grid current scanning voltage scanning process, described substrate terminal is measured, obtain substrate current;
S3, set up an I-V curve of described substrate current and described direct grid current scanning voltage;
S4, a fixed voltage is applied to described grid, then repeat step S1 ~ S3 many times, obtain many articles of described substrate currents and described direct grid current scanning voltage the 2nd I-V curve; By the measurement to many articles of the 2nd I-V curve bottom level, obtain the trap density of pn knot.
The embodiment of the present invention, by providing the method for testing of a kind of gate oxide trap density and position, by measuring the relation of substrate current and direct grid current scanning voltage, obtains the trap density of pn knot; And then as the index improved device layout, to reduce the generation that pn ties trap, reduce the problem because pn knot trap causes device performance to reduce.
Details below with regard to the embodiment of the present invention is described:
As shown in Figure 2, the method for testing of a kind of gate oxide trap density and position, comprises the following steps:
S1, source and drain terminal access negative voltage, substrate terminal ground connection, make pn tie forward bias;
Preferably, the described negative voltage accessed in step S1 is between-0.2V ~-0.5V.
It should be noted that, when adopting the device in Fig. 3 (a), at source and drain terminal access negative voltage, substrate terminal ground connection, makes pn tie forward bias; When adopting the device in Fig. 3 (b), at source and drain terminal access positive voltage, substrate terminal ground connection, makes pn tie forward bias;
After S2, described pn tie forward bias, at grid access direct grid current scanning voltage, scan according to the method being pressed onto positive voltage from negative electricity, make device surface be transformed to weak anti-type state from accumulated state; In described direct grid current scanning voltage scanning process, described substrate terminal is measured, obtain substrate current;
Preferably, the described direct grid current scanning voltage in step S2 is between-1.5V ~ 0.5V.
S3, set up an I-V curve of described substrate current and described direct grid current scanning voltage;
As shown in Figure 5, test the substrate current that obtains first and second I-V curve synoptic diagram of change with direct grid current scanning voltage for increasing along with stress time, nethermost one article is an I-V curve.
S4, a fixed voltage is applied to described grid, then repeat step S1 ~ S3 many times, obtain many articles of described substrate currents and described direct grid current scanning voltage the 2nd I-V curve; By the measurement to many articles of the 2nd I-V curve bottom level, obtain the trap density of pn knot.
Preferably, the described fixed voltage in step S4 is 5V.
As shown in Figure 6, tie first and second I-V curve synoptic diagram of the analog result of relation between trap density and substrate current bottom level for pn, nethermost one article is an I-V curve, and remaining is many articles of the 2nd I-V curves.
S5, with the same subscription interval of described direct grid current scanning voltage, many articles of the 2nd I-V curves in an I-V curve in step S3 and step S4 are sampled, obtain the multiple sampled values on curve, many articles of the 2nd I-V curve sampled values are deducted respectively the sampled value of an I-V curve, obtain the 3rd I-V curve of many articles of described substrate currents and described direct grid current scanning voltage; Obtain described substrate current crest location according to the 3rd I-V curve, this crest location is through-peak peak, by the measurement to through-peak peak value, obtains the trap density of pn knot.
As shown in Figure 7, through-peak peak schematic diagram is obtained by the 3rd I-V curve.
S6, judge that pn ties the positional information of trap by the corresponding relation of described substrate current curve bottom level and described through-peak peak value.
As shown in Figure 8, arrange a trap district in pn junction interface, trap is filled with trap in district, and the distance of trap offset device surface is Distance, and the length in trap district is Length.When the numerical value of Distance and Length changes, the relation of simulation substrate current and direct grid current scanning voltage, obtains as analytic target the positional information that pn ties trap using the change of substrate current bottom level and through-peak peak value.
Analysis situation is as follows:
1) work as Distance=0, when changing Length, the analog result obtained as shown in Figure 9.This illustrates as Length less (when being less than 0.1um), and when namely pn knot trap is positioned near surface, the increase of Length only can increase the peak value of through-peak, does not change the height bottom substrate current;
2) as Length comparatively large (when being greater than 0.1um), along with the increase of Length, the height meeting lifting bottom substrate current, and through-peak can reach a saturation value;
3) if fixed L ength, change Distance, the analog result obtained as shown in Figure 10.Therefrom can obtain the relation that pn ties the degree of depth and through-peak and substrate current bottom level residing for trap.The pn knot trap of near surface is comparatively large for the contribution of through-peak, and less to the contribution of substrate current bottom level; It is less that pn away from surface ties the contribution of trap to through-peak, and larger to the contribution of substrate current bottom level.
Based on above analysis, judge positional information mode that pn ties trap for: if the change ratio of through-peak peak value exceeds reservation threshold value described in the described substrate current bottom level change ratio observed, pn ties trap and mostly concentrates on and be greater than in the region of 0.1um with the distance of device surface; If substrate current bottom level change ratio exceeds reservation threshold value described in the change ratio of the described through-peak peak value observed, pn knot trap mostly concentrates on and is less than in the region of 0.1um with the distance of device surface.
Described reservation threshold value is preferably 10%.
The present invention, by measuring the through-peak peak value obtained, also obtains the trap density of pn knot; And then as the index improved device layout.
The present invention is by measuring the relation of substrate current bottom level and through-peak peak value, can in vertical direction the pn near device surface be tied trap and tie trap away from the pn of device surface and make a distinction, obtain the position distribution situation of relevant trap, and then as the index improved device layout.
Embodiment 2:
A kind of gate oxide trap density and position measurement device, is characterized in that, comprise the p-type gate oxide capacitance of N-shaped MOSFET and correspondence, or the N-shaped gate oxide capacitance of p-type MOSFET and correspondence; The p-type gate oxide capacitance that described N-shaped MOSFET is corresponding with it, and the N-shaped gate oxide capacitance intersection formation pn knot that p-type MOSFET is corresponding with it.
As shown in Fig. 3 (a), for N-shaped gate oxide interface trap density testing apparatus, the left side of N-shaped testing apparatus is N-shaped MOSFET element part, by n
+, p-well and grid form the source electrode of testing apparatus of the present invention, substrate and grid, the right side of testing apparatus is p-type gate oxide capacitance part, by n
+, n-well and grid form the drain electrode of apparatus of the present invention, substrate and grid, wherein grid is shared, material is thus formed the gate oxide interface trap density testing apparatus that contains n and p-type device simultaneously.Wherein, Ln and Lp represents the length of N-shaped and p-type part in testing apparatus respectively, is directly proportional to gate oxide interface trap quantity.In the test of gate oxide interface trap density, the most short channel length that Ln and Lp should be more than or equal to that gate fabrication process allows, and in testing apparatus, the channel width of N-shaped or p-type part is fixed value.Same, p-type gate oxide interface trap density testing apparatus has similar design, as shown in Figure 3 (b).
When carrying out the test of gate oxide interface trap density, need to apply forward bias between source and drain and substrate, the absolute value of voltage is between 0.2 ~ 0.5V, grid voltage scans the weak transoid of device from device accumulation, can not supply voltage be exceeded, in order to avoid cause, the high pressure of gate oxide be damaged, in gate voltage scanning process, measure substrate current, device to test circuit as shown in Figure 4 simultaneously.
Utilize the testing apparatus of the embodiment of the present invention, theoretical according to complex centre, when grid voltage makes the electronics of gate oxide interface equal with hole concentration, the recombination current that gate oxide interface trap produces as complex centre is maximum, namely on substrate current, peak feature is presented, as shown in Figure 5.Wherein the peak value of substrate current can be expressed as:
Wherein, A by the area of survey interface trap, σ is the capture cross of interface trap, v
thfor heat movement speed, V
ffor source and drain end is to the forward bias voltage of substrate, K
bfor Boltzmann constant, T is kelvin degree, N
itfor interface trap density, q is electron charge, n
iintrinsic semiconductor concentration.Therefore, the peak value of substrate current and forward bias voltage and 1/T exponent function relation.Because the type of n-well and p-well is contrary, so substrate current occurs that the position of peak value is different, in gate voltage sweep limits, two peak values that substrate current occurs distinguish N-shaped and p-type part in correspondence testing apparatus, therefore also achieve the object simultaneously measuring n and p-type MOS device gate oxide interface trap density.
Generally speaking, the embodiment of the present invention, by providing method of testing and the device at a kind of gate oxide interface and neighbouring trap density and position, by measuring the relation of substrate current and direct grid current scanning voltage, obtains the trap density of pn knot; And then as the index improved device layout, reduce the generation that pn ties trap, reduce the problem because pn knot trap causes device performance to reduce.
The embodiment of the present invention, by measuring the through-peak peak value obtained, also obtains the trap density of pn knot; And then as the index improved device layout.
The embodiment of the present invention is by measuring the relation of substrate current bottom level and through-peak peak value, can in vertical direction the pn near device surface be tied trap and tie trap away from the pn of device surface and make a distinction, obtain the position distribution situation of relevant trap, and then as the index improved device layout.
The trap that the pn of N-shaped gate oxide interface trap, p-type gate oxide interface trap and near interface ties these three kinds, trap dissimilar can make a distinction by the embodiment of the present invention on same device, and the analysis of three kinds of traps is all concentrated in same I-V curve chart study, the information of relevant trap is obtained by the different qualities of curve, very intuitively easy.
It should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
Above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (8)
1. a method of testing for gate oxide trap density and position, is characterized in that, comprises the following steps:
S1, source and drain terminal access negative voltage, substrate terminal ground connection, make pn tie forward bias;
After S2, described pn tie forward bias, at grid access direct grid current scanning voltage, scan according to the method being pressed onto positive voltage from negative electricity, make device surface be transformed to weak anti-type state from accumulated state; In described direct grid current scanning voltage scanning process, described substrate terminal is measured, obtain substrate current;
S3, set up an I-V curve of described substrate current and described direct grid current scanning voltage;
S4, a fixed voltage is applied to described grid, then repeat step S1 ~ S3 many times, obtain many articles of described substrate currents and described direct grid current scanning voltage the 2nd I-V curve; By the measurement to many articles of the 2nd I-V curve bottom level, obtain the trap density of pn knot.
2. method of testing as claimed in claim 1, it is characterized in that, also step S5 is comprised after step S4, with the same subscription interval of described direct grid current scanning voltage, many articles of the 2nd I-V curves in an I-V curve in step S3 and step S4 are sampled, obtain the multiple sampled values on curve, many articles of the 2nd I-V curve sampled values are deducted respectively the sampled value of an I-V curve, obtain the 3rd I-V curve of many articles of described substrate currents and described direct grid current scanning voltage; Obtain described substrate current crest location according to the 3rd I-V curve, this crest location is through-peak peak, by the measurement to through-peak peak value, obtains the trap density of pn knot.
3. method of testing as claimed in claim 2, is characterized in that, also comprise step S6 after step S5, judges that pn ties the positional information of trap by the corresponding relation of described substrate current curve bottom level and described through-peak peak value.
4. method of testing as claimed in claim 3, it is characterized in that, judge positional information mode that pn ties trap for: if the change ratio of through-peak peak value exceeds reservation threshold value described in the described substrate current bottom level change ratio observed, pn ties trap and mostly concentrates on and be greater than in the region of 0.1um with the distance of device surface; If substrate current bottom level change ratio exceeds reservation threshold value described in the change ratio of the described through-peak peak value observed, pn knot trap mostly concentrates on and is less than in the region of 0.1um with the distance of device surface.
5. method of testing as claimed in claim 4, is characterized in that, subscribing threshold value is 10%.
6. method of testing as claimed in claim 1, it is characterized in that, the described negative voltage accessed in step S1 is between-0.2V ~-0.5V.
7. method of testing as claimed in claim 1, it is characterized in that, the described direct grid current scanning voltage in step S2 is between-1.5V ~ 0.5V.
8. method of testing as claimed in claim 1, it is characterized in that, the described fixed voltage in step S4 is 5V.
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| CN107219448B (en) * | 2017-06-07 | 2019-03-26 | 西安电子科技大学 | The barrier layer internal trap of constant is distributed characterizing method when based on feature |
| CN107478977B (en) * | 2017-07-13 | 2019-12-06 | 中山大学 | Method for extracting trap state density of oxide semiconductor thin film transistor |
| CN107589361B (en) * | 2017-09-06 | 2020-10-02 | 中国工程物理研究院电子工程研究所 | Method for measuring trap energy level distribution in oxide layer of semiconductor device |
| CN107703430B (en) * | 2017-09-11 | 2019-02-22 | 西安电子科技大学 | The measurement method that surface state trap influences device output characteristics |
| CN107703431B (en) * | 2017-09-11 | 2019-02-22 | 西安电子科技大学 | Device surface state trap measurement method based on changeable frequency pulse technique |
| CN112098790B (en) * | 2020-08-05 | 2023-04-14 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | MIS-HEMT (metal insulator semiconductor-high electron mobility transistor) -based energy distribution testing method and system for boundary trap |
| CN113419156A (en) * | 2021-06-15 | 2021-09-21 | 合肥工业大学 | Power semiconductor device gate oxide state monitoring system and using method thereof |
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| CN102053114A (en) * | 2010-11-02 | 2011-05-11 | 北京大学 | Method for testing density of grid dielectric layer trap of non-substrate semiconductor device |
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