CN103367193A - Method and device for testing trap density and position of gate oxide layer - Google Patents
Method and device for testing trap density and position of gate oxide layer Download PDFInfo
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- CN103367193A CN103367193A CN201310314338XA CN201310314338A CN103367193A CN 103367193 A CN103367193 A CN 103367193A CN 201310314338X A CN201310314338X A CN 201310314338XA CN 201310314338 A CN201310314338 A CN 201310314338A CN 103367193 A CN103367193 A CN 103367193A
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Abstract
The invention provides a method and a device for testing trap density and position of a gate oxide layer, and relates to the technical field of quality and reliability testing of an MOS (Metal Oxide Semiconductor) device. The method comprises the following steps: S1, accessing negative voltage at a source end and a drain end, grounding at a substrate end, so that p and n nodes are forward bias; S2, after the p and n nodes are forward bias, accessing a grid direct-current scanning voltage at a grid, and scanning from negative voltage to positive voltage, so that the surface of the device becomes weak inversion state from accumulation state; measuring the substrate end during the scanning process so as to obtain substrate current; S3, establishing a first I-V curve of the substrate current and the grid direct-current scanning voltage; S4, applying a fixed voltage to the grid, repeating the steps S1 to S 3 for multiple times so as to obtain a plurality of second I-V curves; measuring the heights of bottoms of the second I-V curves so as to obtain the trap density of p and n nodes. According to the method and the device, the strap density of the p and no nodes can be measured and the positions of traps can be positioned, so that the design of the device is improved so as to reduce the traps.
Description
Technical field
The present invention relates to MOS device quality, reliability testing technical field, be specifically related to method of testing and the device of a kind of gate oxide trap density and position.
Background technology
Along with the develop rapidly of semiconductor technology and the significantly raising of microelectronic chip integrated level, the design of integrated circuit and level of processing have entered the nanoscale MOS epoch, gate oxide is as the core of MOS device, have very important effect aspect MOS device quality, the reliability assessment, wherein the interface trap density of gate oxide is one of very important index.The generation of gate oxide interface trap causes device performance to reduce so that device mobility descends, and therefore, the monitoring to the gate oxide interface trap in technological process is very necessary.
Gate oxide interface trap density testing apparatus commonly used is oxide layer capacitance structure or MOSFET(metal-oxide half field effect transistor) device, a two ends capacitor structure that comprises grid and substrate, or four end MOSFET device architectures that comprise source electrode, grid, drain electrode and substrate.The method of testing of the routine of the interface trap density of gate oxide is to measure for the gate oxide testing apparatus of N-shaped and p-type MOS device respectively.Number of patent application is 201110397002.5 applications for a patent for invention, has mentioned a kind of gate oxide interface trap density testing apparatus and method of testing, adopts same testing apparatus to finish test to n and p-type MOS component grid oxidizing layer interface trap density.
But above-mentioned method of testing, the index of paying close attention to only limits to the density of the gate oxide interface trap of N-shaped and p-type MOS device, lack the density measurement for the near interface trap, particularly do not consider the trap density of pn knot, and the position distribution situation of pn knot trap.
Summary of the invention
(1) technical problem that solves
For the deficiencies in the prior art, the invention provides method of testing and the device of a kind of gate oxide trap density and position, can measure the trap density of pn knot.
(2) technical scheme
For realizing above purpose, the present invention is achieved by the following technical programs:
The method of testing of a kind of gate oxide trap density and position is characterized in that, may further comprise the steps:
S1, at source and drain terminal access negative voltage, substrate terminal ground connection makes pn knot forward bias;
Behind S2, the described pn knot forward bias, at grid access direct grid current scanning voltage, scan according to the method that is pressed onto positive voltage from negative electricity, make device surface be transformed to weak anti-type state from accumulated state; In described direct grid current scanning voltage scanning process, described substrate terminal is measured, obtained substrate current;
S3, set up an I-V curve of described substrate current and described direct grid current scanning voltage;
S4, described grid is applied a fixed voltage, then repeating step S1～S3 is many times, obtains many described substrate currents and described direct grid current scanning voltage the 2nd I-V curve; By the measurement to many articles of the 2nd I-V curve bottom level, obtain the trap density of pn knot.
Preferably, also comprise step S5 behind the step S4, same subscription interval with described direct grid current scanning voltage, many articles of the 2nd I-V curves among an I-V curve among the step S3 and the step S4 are sampled, obtain a plurality of sampled values on the curve, many articles of the 2nd I-V curve sampled values are deducted respectively the sampled value of an I-V curve, obtain the 3rd I-V curve of many described substrate currents and described direct grid current scanning voltage; Obtain described substrate current crest location according to the 3rd I-V curve, this crest location is the through-peak peak, by the measurement to the through-peak peak value, obtains the trap density of pn knot.
Preferably, also comprise step S6 behind the step S5, judge the positional information of pn knot trap by the corresponding relation of described substrate current curve bottom level and described through-peak peak value.
Wherein, judge that the positional information mode of pn knot trap is: if the described substrate current bottom level that observes changes obviously, pn knot trap concentrates in the zone of distance greater than 0.1um with device surface mostly; If the variation of the described through-peak peak value that observes is obvious, pn knot trap concentrates in the zone of distance less than 0.1um with device surface mostly.
Preferably, the described negative voltage that accesses among the step S1-0.2V～-0.5V between.
Preferably, the described direct grid current scanning voltage among the step S2 be-1.5V～0.5V between.
Preferably, the described fixed voltage among the step S4 is 5V.
The present invention also provides a kind of gate oxide trap density and position measurement device, it is characterized in that, comprises N-shaped MOSFET and corresponding p-type gate oxide electric capacity, perhaps p-type MOSFET and corresponding N-shaped gate oxide electric capacity; The p-type gate oxide electric capacity that described N-shaped MOSFET is corresponding with it, and the p-type MOSFET N-shaped gate oxide electric capacity intersection corresponding with it consists of the pn knot;
Wherein, a side of testing apparatus is N-shaped MOSFET, and its n+ mixes and consists of the source electrode of described testing apparatus, and its p+ doping and p well region consist of the substrate of described testing apparatus, and its grid consists of the part of described testing apparatus grid; The opposite side of described testing apparatus is p-type gate oxide electric capacity, and its n+ at the n well region mixes and consists of the drain electrode of described testing apparatus, and its grid consists of another part of described testing apparatus grid;
Perhaps, a side of described testing apparatus is p-type MOSFET, and its p+ mixes and consists of the source electrode of described testing apparatus, and its n+ doping and n well region consist of the substrate of described testing apparatus, and its grid consists of the part of described testing apparatus grid; The opposite side of described testing apparatus is N-shaped gate oxide electric capacity, and its p+ at the p well region mixes and consists of the drain electrode of described testing apparatus, and its grid consists of another part of described testing apparatus grid.
(3) beneficial effect
The present invention by measuring the relation of substrate current and direct grid current scanning voltage, obtains the trap density of pn knot by method of testing and the device of a kind of gate oxide trap density and position are provided; And then as designs is carried out improved index, reduce the generation of pn knot trap, reduce the problem that causes device performance to reduce because of pn knot trap.
The through-peak peak value of the present invention by measuring also obtains the trap density that pn ties; And then as designs is carried out improved index.
The present invention is by measuring the relation of substrate current bottom level and through-peak peak value, can be in vertical direction will make a distinction near the pn knot trap of device surface with away from the pn knot trap of device surface, obtain the position distribution situation of relevant trap, and then as designs is carried out improved index.
The present invention can be on same device makes a distinction these three kinds of dissimilar traps of pn knot trap of N-shaped gate oxide interface trap, p-type gate oxide interface trap and near interface, and the analysis of three kinds of traps all concentrated in the same I-V curve chart study, obtained the information of relevant trap by the different qualities of curve, very easy to be directly perceived.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is method of testing flow chart in the embodiment of the invention;
Fig. 2 is another flow chart of method of testing in the embodiment of the invention;
Fig. 3 (a) with (b) be two kinds of structural representations of testing apparatus in one embodiment of the invention;
Fig. 4 is that test circuit arranges schematic diagram in the embodiment of the invention;
Fig. 5 test the substrate current that obtains with first and second IV curve synoptic diagram of scanning voltage variation along with stress time increases in the embodiment of the invention;
Fig. 6 is first and second IV curve synoptic diagram that pn ties the analog result of trap density and substrate current bottom level Relations Among in the embodiment of the invention;
Fig. 7 is for to obtain through-peak peak schematic diagram by the 3rd I-V curve;
Fig. 8 is that pn knot trap area arranges schematic diagram in the embodiment of the invention;
Fig. 9 be in the embodiment of the invention trap area Length parameter for the schematic diagram that affects of through-peak and substrate current bottom level;
Figure 10 be in the embodiment of the invention trap area Distance parameter for the schematic diagram of the impact of through-peak and substrate current bottom level.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer, below in conjunction with the accompanying drawing in the embodiment of the invention, technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Embodiment 1:
As shown in Figure 1, the method for testing of a kind of gate oxide trap density and position may further comprise the steps:
S1, at source and drain terminal access negative voltage, substrate terminal ground connection makes pn knot forward bias;
Behind S2, the described pn knot forward bias, at grid access direct grid current scanning voltage, scan according to the method that is pressed onto positive voltage from negative electricity, make device surface be transformed to weak anti-type state from accumulated state; In described direct grid current scanning voltage scanning process, described substrate terminal is measured, obtained substrate current;
S3, set up an I-V curve of described substrate current and described direct grid current scanning voltage;
S4, described grid is applied a fixed voltage, then repeating step S1～S3 is many times, obtains many described substrate currents and described direct grid current scanning voltage the 2nd I-V curve; By the measurement to many articles of the 2nd I-V curve bottom level, obtain the trap density of pn knot.
The embodiment of the invention by measuring the relation of substrate current and direct grid current scanning voltage, obtains the trap density of pn knot by the method for testing of a kind of gate oxide trap density and position is provided; And then as designs is carried out improved index, to reduce the generation of pn knot trap, reduce the problem that causes device performance to reduce because of pn knot trap.
The below describes with regard to the details of the embodiment of the invention:
As shown in Figure 2, the method for testing of a kind of gate oxide trap density and position may further comprise the steps:
S1, at source and drain terminal access negative voltage, substrate terminal ground connection makes pn knot forward bias;
Preferably, the described negative voltage that accesses among the step S1-0.2V～-0.5V between.
Need to prove, when the device among employing Fig. 3 (a), at source and drain terminal access negative voltage, substrate terminal ground connection makes pn knot forward bias; When the device among employing Fig. 3 (b), at source and drain terminal access positive voltage, substrate terminal ground connection makes pn knot forward bias;
Behind S2, the described pn knot forward bias, at grid access direct grid current scanning voltage, scan according to the method that is pressed onto positive voltage from negative electricity, make device surface be transformed to weak anti-type state from accumulated state; In described direct grid current scanning voltage scanning process, described substrate terminal is measured, obtained substrate current;
Preferably, the described direct grid current scanning voltage among the step S2 be-1.5V～0.5V between.
S3, set up an I-V curve of described substrate current and described direct grid current scanning voltage;
As shown in Figure 5, test the substrate current that obtains with first and second I-V curve synoptic diagram of variation of direct grid current scanning voltage for increasing along with stress time, nethermost one is an I-V curve.
S4, described grid is applied a fixed voltage, then repeating step S1～S3 is many times, obtains many described substrate currents and described direct grid current scanning voltage the 2nd I-V curve; By the measurement to many articles of the 2nd I-V curve bottom level, obtain the trap density of pn knot.
Preferably, the described fixed voltage among the step S4 is 5V.
As shown in Figure 6, tie first and second I-V curve synoptic diagram of the analog result of trap density and substrate current bottom level Relations Among for pn, nethermost one is an I-V curve, and remaining is many articles of the 2nd I-V curves.
S5, with the same subscription interval of described direct grid current scanning voltage, many articles of the 2nd I-V curves among an I-V curve among the step S3 and the step S4 are sampled, obtain a plurality of sampled values on the curve, many articles of the 2nd I-V curve sampled values are deducted respectively the sampled value of an I-V curve, obtain the 3rd I-V curve of many described substrate currents and described direct grid current scanning voltage; Obtain described substrate current crest location according to the 3rd I-V curve, this crest location is the through-peak peak, by the measurement to the through-peak peak value, obtains the trap density of pn knot.
As shown in Figure 7, obtain through-peak peak schematic diagram by the 3rd I-V curve.
S6, the corresponding relation by described substrate current curve bottom level and described through-peak peak value are judged the positional information of pn knot trap.
As shown in Figure 8, in the pn junction interface trap district is set, trap has been filled trap in the district, and the distance of trap offset device surface is Distance, and the length in trap district is Length.When the numerical value of Distance and Length changed, the relation of simulation substrate current and direct grid current scanning voltage was obtained the positional information that pn ties trap with the variation of substrate current bottom level and through-peak peak value as analytic target.
The analysis situation is as follows:
1) work as Distance=0, when changing Length, the analog result that obtains as shown in Figure 9.This explanation is as Length less (less than 0.1um time), and when namely pn knot trap was positioned near surface, the increase of Length only can increase the peak value of through-peak, does not change the height bottom the substrate current;
2) as Length large (greater than 0.1um time), along with the increase of Length, the height of substrate current bottom can lifting, and through-peak can reach a saturation value;
3) if fixed L ength changes Distance, the analog result that obtains as shown in figure 10.Can therefrom obtain the relation of the pn knot trap degree of depth of living in and through-peak and substrate current bottom level.The pn knot trap of near surface is larger for the contribution of through-peak, and less to the contribution of substrate current bottom level; Pn knot trap away from the surface is less to the contribution of through-peak, and larger to the contribution of substrate current bottom level.
Based on above analysis, the positional information mode of judging pn knot trap is: exceed the reservation threshold value if the described substrate current bottom level that observes changes the variation ratio of the described through-peak peak value of ratio, pn knot trap concentrates in the zone of distance greater than 0.1um with device surface mostly; If the variation ratio described substrate current bottom level variation ratio of the described through-peak peak value that observes exceeds the reservation threshold value, pn knot trap concentrates in the zone of distance less than 0.1um with device surface mostly.
Described reservation threshold value is preferably 10%.
The through-peak peak value of the present invention by measuring also obtains the trap density that pn ties; And then as designs is carried out improved index.
The present invention is by measuring the relation of substrate current bottom level and through-peak peak value, can be in vertical direction will make a distinction near the pn knot trap of device surface with away from the pn knot trap of device surface, obtain the position distribution situation of relevant trap, and then as designs is carried out improved index.
Embodiment 2:
A kind of gate oxide trap density and position measurement device is characterized in that, comprise N-shaped MOSFET and corresponding p-type gate oxide electric capacity, perhaps p-type MOSFET and corresponding N-shaped gate oxide electric capacity; The p-type gate oxide electric capacity that described N-shaped MOSFET is corresponding with it, and the p-type MOSFET N-shaped gate oxide electric capacity intersection corresponding with it consists of the pn knot.
Shown in Fig. 3 (a), take N-shaped gate oxide interface trap density testing apparatus as example, the left side of N-shaped testing apparatus is N-shaped MOSFET device portions, by n
+, p-well and grid consist of source electrode, substrate and the grid of testing apparatus of the present invention, the right side of testing apparatus is p-type gate oxide capacitive part, by n
+, n-well and grid consist of drain electrode, substrate and the grid of apparatus of the present invention, wherein grid shares, and has so just formed a gate oxide interface trap density testing apparatus that has comprised simultaneously n and p-type device.Wherein, Ln and Lp represent respectively N-shaped and p-type length partly in the testing apparatus, are directly proportional with gate oxide interface trap quantity.In gate oxide interface trap density test, the short channel length that Ln and Lp should allow more than or equal to gate fabrication process, and the channel width of N-shaped or p-type part is fixed value in the testing apparatus.Same, p-type gate oxide interface trap density testing apparatus has similar design, shown in Fig. 3 (b).
When carrying out the test of gate oxide interface trap density, need between source and drain and substrate, apply forward bias, the absolute value of voltage is between 0.2～0.5V, grid voltage scans transoid a little less than the device from device accumulation, can not beyond supply voltage, in order to avoid cause high pressure damage to gate oxide, in the gate voltage scanning process, measure simultaneously substrate current, the device to test circuit as shown in Figure 4.
Utilize the testing apparatus of the embodiment of the invention, theoretical according to the complex centre, when grid voltage so that gate oxide electronics and hole concentration at the interface when equating, the recombination current that the gate oxide interface trap produces as the complex centre is maximum, namely present peak feature at substrate current, as shown in Figure 5.Wherein the peak value of substrate current can be expressed as:
Wherein, A by the area of survey interface trap, σ is the capture cross of interface trap, v
ThBe heat movement speed, V
fBe the forward bias voltage of source drain terminal to substrate, K
BBe Boltzmann constant, T is kelvin degree, N
ItBe interface trap density, q is electron charge, n
iIntrinsic semiconductor concentration.Therefore, the peak value of substrate current and forward bias voltage and 1/T exponent function relation.Because the type opposite of n-well and p-well, so it is different that the position of peak value appears in substrate current, in the gate voltage sweep limits, therefore two peak values that substrate current occurs are corresponding respectively N-shaped and p-type part in the testing apparatus have also realized measuring simultaneously the purpose of n and p-type MOS component grid oxidizing layer interface trap density.
Generally speaking, the embodiment of the invention by measuring the relation of substrate current and direct grid current scanning voltage, obtains the trap density of pn knot by method of testing and the device of a kind of gate oxide interface and near trap density and position are provided; And then as designs is carried out improved index, reduce the generation of pn knot trap, reduce the problem that causes device performance to reduce because of pn knot trap.
The through-peak peak value of the embodiment of the invention by measuring also obtains the trap density that pn ties; And then as designs is carried out improved index.
The embodiment of the invention is by measuring the relation of substrate current bottom level and through-peak peak value, can be in vertical direction will make a distinction near the pn knot trap of device surface with away from the pn knot trap of device surface, obtain the position distribution situation of relevant trap, and then as designs is carried out improved index.
The embodiment of the invention can be on same device makes a distinction these three kinds of dissimilar traps of pn knot trap of N-shaped gate oxide interface trap, p-type gate oxide interface trap and near interface, and the analysis of three kinds of traps all concentrated in the same I-V curve chart study, obtained the information of relevant trap by the different qualities of curve, very easy to be directly perceived.
Need to prove, in this article, relational terms such as the first and second grades only is used for an entity or operation are separated with another entity or operating space, and not necessarily requires or hint and have the relation of any this reality or sequentially between these entities or the operation.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby not only comprise those key elements so that comprise process, method, article or the equipment of a series of key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.In the situation that not more restrictions, the key element that is limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
Above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (9)
1. the method for testing of a gate oxide trap density and position is characterized in that, may further comprise the steps:
S1, at source and drain terminal access negative voltage, substrate terminal ground connection makes pn knot forward bias;
Behind S2, the described pn knot forward bias, at grid access direct grid current scanning voltage, scan according to the method that is pressed onto positive voltage from negative electricity, make device surface be transformed to weak anti-type state from accumulated state; In described direct grid current scanning voltage scanning process, described substrate terminal is measured, obtained substrate current;
S3, set up an I-V curve of described substrate current and described direct grid current scanning voltage;
S4, described grid is applied a fixed voltage, then repeating step S1～S3 is many times, obtains many described substrate currents and described direct grid current scanning voltage the 2nd I-V curve; By the measurement to many articles of the 2nd I-V curve bottom level, obtain the trap density of pn knot.
2. method of testing as claimed in claim 1, it is characterized in that, also comprise step S5 behind the step S4, same subscription interval with described direct grid current scanning voltage, many articles of the 2nd I-V curves among an I-V curve among the step S3 and the step S4 are sampled, obtain a plurality of sampled values on the curve, many articles of the 2nd I-V curve sampled values are deducted respectively the sampled value of an I-V curve, obtain the 3rd I-V curve of many described substrate currents and described direct grid current scanning voltage; Obtain described substrate current crest location according to the 3rd I-V curve, this crest location is the through-peak peak, by the measurement to the through-peak peak value, obtains the trap density of pn knot.
3. method of testing as claimed in claim 2 is characterized in that, also comprises step S6 behind the step S5, judges the positional information of pn knot trap by the corresponding relation of described substrate current curve bottom level and described through-peak peak value.
4. method of testing as claimed in claim 3, it is characterized in that, the positional information mode of judging pn knot trap is: exceed the reservation threshold value if the described substrate current bottom level that observes changes the variation ratio of the described through-peak peak value of ratio, pn knot trap concentrates in the zone of distance greater than 0.1um with device surface mostly; If the variation ratio described substrate current bottom level variation ratio of the described through-peak peak value that observes exceeds the reservation threshold value, pn knot trap concentrates in the zone of distance less than 0.1um with device surface mostly.
5. method of testing as claimed in claim 4 is characterized in that, subscribing threshold value is 10%.
6. method of testing as claimed in claim 1 is characterized in that, the described negative voltage that accesses among the step S1-0.2V～-0.5V between.
7. method of testing as claimed in claim 1 is characterized in that, the described direct grid current scanning voltage among the step S2 is-1.5V～0.5V between.
8. method of testing as claimed in claim 1 is characterized in that, the described fixed voltage among the step S4 is 5V.
9. a gate oxide trap density and position measurement device is characterized in that, comprise N-shaped MOSFET and corresponding p-type gate oxide electric capacity, perhaps p-type MOSFET and corresponding N-shaped gate oxide electric capacity; The p-type gate oxide electric capacity that described N-shaped MOSFET is corresponding with it, the N-shaped gate oxide electric capacity intersection that perhaps p-type MOSFET is corresponding with it consist of the pn knot;
Wherein, a side of testing apparatus is N-shaped MOSFET, and its n+ mixes and consists of the source electrode of described testing apparatus, and its p+ doping and p well region consist of the substrate of described testing apparatus, and its grid consists of the part of described testing apparatus grid; The opposite side of described testing apparatus is p-type gate oxide electric capacity, and its n+ at the n well region mixes and consists of the drain electrode of described testing apparatus, and its grid consists of another part of described testing apparatus grid;
Perhaps, a side of described testing apparatus is p-type MOSFET, and its p+ mixes and consists of the source electrode of described testing apparatus, and its n+ doping and n well region consist of the substrate of described testing apparatus, and its grid consists of the part of described testing apparatus grid; The opposite side of described testing apparatus is N-shaped gate oxide electric capacity, and its p+ at the p well region mixes and consists of the drain electrode of described testing apparatus, and its grid consists of another part of described testing apparatus grid.
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