CN106384734A - Integrated circuit plasma protection structure with high-pressure-resistant characteristics and forming method thereof - Google Patents
Integrated circuit plasma protection structure with high-pressure-resistant characteristics and forming method thereof Download PDFInfo
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- CN106384734A CN106384734A CN201611113099.1A CN201611113099A CN106384734A CN 106384734 A CN106384734 A CN 106384734A CN 201611113099 A CN201611113099 A CN 201611113099A CN 106384734 A CN106384734 A CN 106384734A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000005669 field effect Effects 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 18
- 150000004706 metal oxides Chemical class 0.000 abstract description 18
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 238000012360 testing method Methods 0.000 description 25
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
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- 230000004048 modification Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- General Physics & Mathematics (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an integrated circuit plasma protection structure with high-pressure-resistant characteristics and a forming method thereof. The integrated circuit plasma protection structure comprises a substrate and, a first diode, a second diode and a metal oxide semiconductor field effect transistor, wherein the first diode, the second diode and the metal oxide semiconductor field effect transistor are formed in the substrate; the first diode and the second diode are connected in series in the same direction to form a serially connected diode group; one end of the serially connected diode group is connected with a grid electrode of the metal oxide semiconductor field effect transistor. The integrated circuit plasma protection structure with high-pressure-resistant characteristics and the forming method thereof provided by the invention have the advantages that one end of the formed serially connected diode group is connected with the grid electrode of the metal oxide semiconductor field effect transistor, so that charges of the metal oxide semiconductor field effect transistor are discharged away through the serially connected diode group when being conducted; the damage due to the charges is avoided; in addition, the metal oxide semiconductor field effect transistor has higher reverse-biased breakdown voltage characteristics.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly to a kind of integrated circuit plasma with high withstand voltage characteristic
Protection structure and forming method.
Background technology
Through semicentennial high speed development, microelectric technique is right with the semiconductor technology relying on microelectric technique
The development of human society creates revolutionary impact.Technological evaluation in semiconductor manufacturing needs various test structures with monitoring
As carrier, the input/output terminal of test structure requires connect on metal pad (PAD), thus carrying out signal to test structure
Input and output.In technical process, metal PAD is very big charge-trapping antenna with respect to test structure, and electric charge can be by gold
Belong to PAD to conduct to test structure, stress is produced to test structure, lead to test structure to be degenerated and even lost efficacy, thus losing work(
Energy.So protecting to test structure, it is to avoid the charging damage test structure in technical process, guarantee test structure is just
Often assess and monitoring manufacturing process.
The protection of test structure avoids outside the requirement of charging damage in meeting technical process, also will avoid interference survey as far as possible
The function of examination structure is it is ensured that test structure can be normally carried out testing.Generally adopt single diode and capacitive oxide at present
Two ways carries out protecting the mos field effect transistor of test structure, by single diode or oxide electricity
Hold the gate connected in parallel with tested object such as mos field effect transistor (MOSFET), but single two poles
The easy reverse breakdown of tube capacity, electric capacity is limited to the design that volume or capacity etc. are then unfavorable for semiconductor device structure.
Therefore, how to prevent semiconductor device structure from occurring charging damage is those skilled in the art's urgent need to resolve one
Technical problem.
Content of the invention
It is an object of the invention to provide a kind of integrated circuit plasma protection structure with high withstand voltage characteristic and its
Forming method, to solve the problems, such as that in prior art, charging damage in semiconductor structure.
For solving above-mentioned technical problem, the present invention provides a kind of integrated circuit plasma protection with high withstand voltage characteristic
Structure, including：Substrate and be formed at the first diode in substrate, the second diode and metal oxide semiconductor field-effect
Transistor, described first diode forms series diode group, described series diode with described second diode series aiding connection
One end of group connects the grid of described mos field effect transistor.
Preferably, in the described integrated circuit plasma protection structure with high withstand voltage characteristic, described series connection two poles
Doped region in the other end of pipe group and described mos field effect transistor common substrate.
Preferably, in the described integrated circuit plasma protection structure with high withstand voltage characteristic, described metal oxidation
Thing semiconductor field effect transistor is N-type mos field effect transistor.
Preferably, in the described integrated circuit plasma protection structure with high withstand voltage characteristic, shape in described substrate
Become to have the first doped region, the second doped region and the 3rd doped region, described first doped region, the second doped region, the 3rd doped region are simultaneously
Put arrangement, and the second doped region is located between the first doped region and the 3rd doped region；It is formed with the 4th in described first doped region
Doped region, described first doped region and the 4th doped region collectively form described first diode；Described second doped region and the 3rd
Doped region collectively forms described second diode；It is formed with source area and drain region, the described 3rd in described 3rd doped region
It is formed with gate regions, described source area, drain region and gate regions collectively form described MOS field on doped region
Effect transistor, described 4th doped region is connected with described gate regions；Described first doped region and the conductive-type of the 3rd doped region
Type is N-type, and described second doped region, the conduction type of the 4th doped region, source area and drain region are p-type.
Preferably, in the described integrated circuit plasma protection structure with high withstand voltage characteristic, described 3rd doping
It is formed with the 5th doped region, the conduction type of described 3rd doped region and the 5th doped region is identical in area.
Preferably, in the described integrated circuit plasma protection structure with high withstand voltage characteristic, described metal oxidation
Thing semiconductor field effect transistor is P-type mos field-effect transistor.
Preferably, in the described integrated circuit plasma protection structure with high withstand voltage characteristic, shape in described substrate
Become to have the first doped region, the second doped region and the 3rd doped region, described second doped region and the 3rd doped region Alignment, described
First doped region is formed in the second doped region；It is formed with the 4th doped region, described first doped region in described first doped region
Collectively form described first diode with the 4th doped region；Described second doped region and the 3rd doped region collectively form described second
Diode；It is formed with source area and drain region in described 3rd doped region, described 3rd doped region is formed with gate regions, institute
State source area, drain region and gate regions and collectively form described mos field effect transistor；Described first doping
The conduction type of area and the 3rd doped region is p-type, described second doped region, the conduction of the 4th doped region, source area and drain region
Type is N-type.
Preferably, in the described integrated circuit plasma protection structure with high withstand voltage characteristic, described 3rd doping
It is formed with the 5th doped region, the conduction type of described 3rd doped region and the 5th doped region is identical in area.
Preferably, in the described integrated circuit plasma protection structure with high withstand voltage characteristic, described one or two pole
Between pipe and described second diode, at least series aiding connection has one the 3rd diode.
The present invention also provides a kind of forming method of the integrated circuit plasma protection structure with high withstand voltage characteristic, bag
Include：One substrate is provided；Form the first diode, the second diode and metal oxide semiconductor field-effect in described substrate
Transistor, described first diode forms series diode group, described series diode with described second diode series aiding connection
Group one end connects the grid of described mos field effect transistor.
Preferably, in the forming method of the described integrated circuit plasma protection structure with high withstand voltage characteristic, institute
The forming method stating the first diode, the second diode and mos field effect transistor includes：In substrate
Middle formation the first doped region, the second doped region, the 3rd doped region, described first doped region, the second doped region, the 3rd doped region are simultaneously
Put arrangement, and the second doped region is located between the first doped region and the 3rd doped region；Form the 4th in described first doped region
Doped region, is formed with source area and drain region in described 3rd doped region, and described first doped region and the 4th doped region are common
Constitute described first diode, described second doped region and the 3rd doped region collectively form described second diode；Described
It is formed with gate regions, described source area, drain region and gate regions collectively form described metal-oxide and partly lead above three doped regions
Body field-effect transistor；Wherein, the conduction type of described first doped region, the 3rd doped region and the 5th doped region is N-type, described
Second doped region, the conduction type of the 4th doped region, source area and drain region are p-type.
Preferably, in the forming method of the described integrated circuit plasma protection structure with high withstand voltage characteristic, also
Form the 5th doped region in described 3rd doped region, the conduction type of described 3rd doped region and the 5th doped region is identical.
Preferably, in the forming method of the described integrated circuit plasma protection structure with high withstand voltage characteristic, institute
The forming method stating the first diode, the second diode and mos field effect transistor includes：In substrate
Middle formation the first doped region, the second doped region, the 3rd doped region, described second doped region and the 3rd doped region Alignment, institute
State the first doped region to be formed in the second doped region；Form the 4th doped region in described first doped region, mix the described 3rd
It is formed with source area and drain region, described first doped region and the 4th doped region collectively form described first diode in miscellaneous area,
Described second doped region and the 3rd doped region collectively form described second diode；It is formed with grid above described 3rd doped region
Polar region, described source area, drain region and gate regions collectively form described mos field effect transistor；Wherein,
The conduction type of described first doped region, the 3rd doped region and the 5th doped region is N-type, described second doped region, the 4th doping
The conduction type of area, source area and drain region is p-type.
Preferably, in the forming method of the described integrated circuit plasma protection structure with high withstand voltage characteristic, also
Form the 5th doped region in described 3rd doped region, the conduction type of described 3rd doped region and the 5th doped region is identical
Have in integrated circuit plasma protection structure of high withstand voltage characteristic and forming method thereof what the present invention provided,
Form the first diode, the second diode and mos field effect transistor in the substrate, by by described
The one end of the series diode group that one diode is formed with described second diode series aiding connection is connected described metal-oxide half
The grid of conductor field-effect transistor, makes mos field effect transistor when electric charge is to conducting by described
Series diode group is drained, it is to avoid the damage being caused due to electric charge, and so that mos field effect transistor is had
The characteristic of higher reverse-biased breakdown voltage.
Brief description
Fig. 1 is the circuit of the integrated circuit plasma protection structure with high withstand voltage characteristic of the embodiment of the present invention one
Figure；
Fig. 2 is that the cuing open of integrated circuit plasma protection structure with high withstand voltage characteristic of the embodiment of the present invention one is shown
Figure；
Fig. 3 is the circuit of the integrated circuit plasma protection structure with high withstand voltage characteristic of the embodiment of the present invention two
Figure；
Fig. 4 is that the cuing open of integrated circuit plasma protection structure with high withstand voltage characteristic of the embodiment of the present invention two is shown
Figure；
Fig. 5 is the forming method of the integrated circuit plasma protection structure with high withstand voltage characteristic of the embodiment of the present invention
Step schematic diagram.
Specific embodiment
In order that objects, features and advantages of the present invention can become apparent from understandable, refer to accompanying drawing.It should be clear that this explanation
Structure depicted in book institute accompanying drawings, ratio, size etc., all only in order to coordinate the content disclosed in description, for being familiar with this
The personage of technology understands and reads, and is not limited to the enforceable qualificationss of the present invention, therefore does not have technical essence and anticipate
Justice, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting effect and the institute that the present invention can be generated by
Under the purpose that can reach, all should still fall in the range of disclosed technology contents obtain and can cover.
Embodiment one
As shown in figures 1 and 3, the present invention provides a kind of integrated circuit plasma protection knot with high withstand voltage characteristic
Structure, including：Substrate and be formed at the first diode 20 in substrate, the second diode 30 and metal oxide semiconductcor field effect
Answer transistor (MOSFET) 40, described first diode 20 forms series diode with described second diode 30 series aiding connection
Group, described series diode group one end connects the grid of described mos field effect transistor 40, described series connection
Doped region in the other end of diode group and described mos field effect transistor 40 common substrate.Described gold
Belong to oxide semiconductor field effect transistor 40 as tested object, described first diode 20 and described second diode 30
For protecting described mos field effect transistor 40, mos field effect transistor is manufacturing
Deng during can be subject to plasma damage, plasma charge can be guided by series diode group, thus avoid by
The damage causing in electric charge, because too high voltages lead to that diode is reverse-biased to be punctured, so the introducing of single diode leads to metal
The grid of oxide semiconductor field effect transistor is unable to high voltage, and the present invention adopts series diode group, and metal is aoxidized
When thing semiconductor field effect transistor 40 carries out the situation such as testing, electric charge can be drained by series diode group, improve simultaneously
Reverse-biased breakdown voltage.
Specifically as shown in Fig. 2 being formed with the first doped region 21, the second doped region 31, the 3rd doped region 40, institute in substrate 10
State the second doped region 31 and the 3rd doped region 40 Alignment, described first doped region 21 is formed in the second doped region 31, institute
State that the first doped region 21 is identical with the conduction type of the 3rd doped region 40, the conduction type of described second doped region 31 and described the
One doped region 21 and the 3rd doped region 40 are contrary.It is formed with the 4th doped region 22 in described first doped region 21, described first
Doped region 21 is different with the conduction type of the 4th doped region 22, and described first doped region 21 and the 4th doped region 22 collectively form institute
State the first diode 20.Described second doped region 31 and the 3rd doped region 40 collectively form described second diode 30.Described
It is formed with source area 41 and drain region 42 in 3rd doped region 40, described 3rd doped region 40 is formed with gate regions 43, institute
State source area 41 and the conduction type of drain region 42 is contrary with the conduction type of described 3rd doped region 40, described source area 41,
Drain region 42 and gate regions 43 collectively form described mos field effect transistor 40.Described second diode 30
With the doped region (i.e. the 3rd doped region 40) in described mos field effect transistor 40 common substrate.Here,
Described 4th doped region 22 is one end of series diode group, and described 3rd doped region 40 is the another of series diode group
End.
As shown in Fig. 2 the conduction type of described first doped region 21, the 3rd doped region 40, the 5th doped region 44 is p-type,
Described second doped region 31, the 4th doped region 22, source area 41, the conduction type of drain region 42 are N-type.Thus, metal aoxidizes
Thing semiconductor field effect transistor 40 is N-type mos field effect transistor (NMOSFET).
Further, it is also formed with the 5th doped region 44 in described 3rd doped region 40, described 3rd doped region 40 He
The conduction type of the 5th doped region 44 is identical, and described 5th doped region 44 is used for drawing as the first terminal, described gate regions 43
Draw as Second terminal.
Described 4th doped region 22 can be formed by source drain dopant mode in the lump with source area 41 and drain region 42, institute
State the first doped region 21 to be formed by trap doping way in the lump with the 3rd doped region 40.It is understood that can be by not
With doping way form the diode of different structure and formed required for series diode group structure it is not limited to Fig. 2
Shown structure.
In a preferred approach, one the 3rd 2 can also be included between described first diode 20 and described second diode 30
Pole pipe, the first diode 20 and described second diode 30 described in described 3rd diode series aiding connection, by series aiding connection more
Many diodes can further improve the reverse-biased breakdown voltage of series diode group, thus improving metal oxide semiconductcor field effect
Answer the reverse voltage endurance of transistor.
As shown in figure 5, the present invention also provides a kind of integrated circuit plasma protection structure with high withstand voltage characteristic
Forming method, including：
Step S10：One substrate is provided；
Step S20：Form the first diode, the second diode and metal oxide semiconductcor field effect in described substrate
Answer transistor, described first diode forms series diode group, described series connection two pole with described second diode series aiding connection
Pipe group one end connect described mos field effect transistor grid, the other end of described series diode group with
Doped region in described mos field effect transistor common substrate.
Detailed introduction has the formation of the integrated circuit plasma protection structure of high withstand voltage characteristic below in conjunction with the accompanying drawings
Method.
First, provide a substrate 10, described substrate 10 is made up of other semi-conducting material such as silicon or germanium, shape in substrate 10
Become the known semiconductor structure needing.
Then, described substrate 10 forms the first diode 20, the second diode 30 and metal-oxide semiconductor (MOS)
Field-effect transistor 40, described first diode 20 forms series diode group, institute with described second diode 30 series aiding connection
State the grid that series diode group one end connects described mos field effect transistor 40, described series diode
Doped region in the other end of group and described mos field effect transistor 40 common substrate.
Specifically, described first diode 20, the second diode 30 and metal-oxide can be formed as follows
Semiconductor field effect transistor 40：
First, the first doped region 21, the second doped region 31, the 3rd doped region 40 are formed in substrate 10, described first mixes
Miscellaneous area 21, the second doped region 31, the 3rd doped region 40 Alignment, and the second doped region 31 is located at the first doped region 21 and the 3rd
Between doped region 40, described first doped region 21 is identical with the conduction type of the 3rd doped region 40, described second doped region 31
Conduction type is contrary with described first doped region 21 and the 3rd doped region 40；
Then, form the 4th doped region 22 in described first doped region 21, be formed with described 3rd doped region 40
Source area 41 and drain region 42；Described first doped region 21 is different with the conduction type of the 4th doped region 22, described first doping
Area 21 and the 4th doped region 22 collectively form described first diode 20；Described second doped region 31 is common with the 3rd doped region 40
Constitute described second diode 30；The conduction type of described source area 41 and drain region 42 and the conduction of described 3rd doped region 40
Type is contrary；
Then, it is formed with gate regions 43 above described 3rd doped region 40, described source area 41, drain region 42 and grid
Area 43 collectively forms described mos field effect transistor 40.Described second diode 30 and described metal oxidation
Doped region (i.e. the 3rd doped region 40) in thing semiconductor field effect transistor 40 common substrate.
Further, the 5th doped region 44, described 3rd doped region 40 and the are formed also in described 3rd doped region 40
The conduction type of five doped regions 44 is identical, and described 5th doped region 44 is used for drawing as the first terminal, the 4th doped region 22 with
Described gate regions 43 connect, and described gate regions 43 are drawn as Second terminal.
Traditional protected mode using single diode, relatively low, the excessive electricity of the reverse-biased breakdown voltage of single diode
Stress can lead to that diode is reverse-biased to be punctured, and makes test structure just lose normal function, so single diode protection mode can limit
Make some high voltage tests (as accelerated tests such as FN tunnellings), be unfavorable for more comprehensively thoroughly test analysis, using oxide electricity
The protected mode held, needs large-area capacitive oxide to share technique electric charge, chip occupying area, is unfavorable for test structure
Design.Compared to the protected mode of traditional single diode or capacitive oxide, using the test structure of the present invention, surveying
During examination, the first diode 20 and the second diode 30 are in conducting state, and the electric charge producing in test is preferential to pass through the one or two
Pole pipe 20 and the second diode 30 guide, and realize tested object (mos field effect transistor) is protected,
And, this test structure and traditional process compatible, not chip occupying area.
Embodiment two
It is in place of the present embodiment and embodiment one difference, mos field effect transistor 40 is p-type gold
Belong to oxide semiconductor field effect transistor (PMOSFET).
Specifically as shown in figure 4, being formed with the first doped region 21, the second doped region 31, the 3rd doped region 40, institute in substrate 10
State the first doped region 21, the second doped region 31, the 3rd doped region 40 Alignment, and the second doped region 31 is located at the first doped region
21 and the 3rd between doped region 40, and described first doped region 21 is identical with the conduction type of the 3rd doped region 40, and described second mixes
The conduction type in miscellaneous area 31 is contrary with described first doped region 21 and the 3rd doped region 40.Described first doped region 21 is formed
There is the 4th doped region 22, described first doped region 21 is different with the conduction type of the 4th doped region 22, described first doped region 21
Collectively form described first diode 20 with the 4th doped region 22.Described second doped region 31 is collectively formed with the 3rd doped region 40
Described second diode 30.It is formed with source area 41 and drain region 42 in described 3rd doped region 40, in the described 3rd doping
Gate regions 43, the conduction of the conduction type of described source area 41 and drain region 42 and described 3rd doped region 40 are formed with area 40
Type is contrary, and it is brilliant that described source area 41, drain region 42 and gate regions 43 collectively form described metal oxide semiconductor field-effect
Body pipe 40.Doped region in described second diode 30 and described mos field effect transistor 40 common substrate
(i.e. the 3rd doped region 40).Here, described 4th doped region 22 is one end of series diode group, described 3rd doped region 40
It is the other end of series diode group.
As shown in figure 4, the conduction type of described first doped region 21, the 3rd doped region 40, the 5th doped region 44 is N-type,
Described second doped region 31, the 4th doped region 22, source area 41, the conduction type of drain region 42 are p-type.
Further, it is also formed with the 5th doped region 44 in described 3rd doped region 40, described 3rd doped region 40 He
The conduction type of the 5th doped region 44 is identical, and described 5th doped region 44 is used for drawing as the first terminal, described gate regions 43
Draw as Second terminal.
Described first diode 20, the second diode 30 and MOS field can be formed as follows
Effect transistor 40：
First, the first doped region 21, the second doped region 31, the 3rd doped region 40 are formed in substrate 10, described second mixes
Miscellaneous area 31 and the 3rd doped region 40 Alignment, described first doped region 21 is formed in the second doped region 31, and described first mixes
Miscellaneous area 21 is identical with the conduction type of the 3rd doped region 40, the conduction type of described second doped region 31 and described first doped region
21 and the 3rd doped region 40 contrary；
Then, form the 4th doped region 22 in described first doped region 21, be formed with described 3rd doped region 40
Source area 41 and drain region 42；Described first doped region 21 is different with the conduction type of the 4th doped region 22, described first doping
Area 21 and the 4th doped region 22 collectively form described first diode 20；Described second doped region 31 is common with the 3rd doped region 40
Constitute described second diode 30；The conduction type of described source area 41 and drain region 42 and the conduction of described 3rd doped region 40
Type is contrary；
Then, it is formed with gate regions 43 above described 3rd doped region 40, described source area 41, drain region 42 and grid
Area 43 collectively forms described mos field effect transistor 40.Described second diode 30 and described metal oxidation
Doped region (i.e. the 3rd doped region 40) in thing semiconductor field effect transistor 40 common substrate.
Further, the 5th doped region 44, described 3rd doped region 40 and the are formed also in described 3rd doped region 40
The conduction type of five doped regions 44 is identical, and described 5th doped region 44 is used for drawing as the first terminal, the 4th doped region 22 with
Described gate regions 43 connect, and described gate regions 43 are drawn as Second terminal.
In sum, integrated circuit plasma protection structure and its shape with high withstand voltage characteristic providing in the present invention
In one-tenth method, form the first diode, the second diode and mos field effect transistor in the substrate, pass through
The one end of the series diode group that described first diode is formed with described second diode series aiding connection is connected described metal
The grid of oxide semiconductor field effect transistor, makes mos field effect transistor when electric charge is to conducting
Drained by described series diode group, it is to avoid the damage being caused due to electric charge, and make metal oxide semiconductor field-effect brilliant
Body pipe has the characteristic of higher reverse-biased breakdown voltage, thus can be formed for testing metal oxide semiconductor field effect transistor
The test structure of pipe.
Foregoing description is only the description to present pre-ferred embodiments, not any restriction to the scope of the invention, this
Any change that the those of ordinary skill in bright field does according to the disclosure above content, modification, belong to the protection of claims
Scope.
Claims (14)
1. a kind of integrated circuit plasma protection structure with high withstand voltage characteristic is it is characterised in that include：Substrate and shape
Become the first diode in substrate, the second diode and mos field effect transistor, described one or two pole
Pipe and described second diode series aiding connection form series diode group, and one end of described series diode group connects described metal
The grid of oxide semiconductor field effect transistor.
2. there is the integrated circuit plasma protection structure of high withstand voltage characteristic as claimed in claim 1 it is characterised in that described
Doped region in the other end of series diode group and described mos field effect transistor common substrate.
3. there is the integrated circuit plasma protection structure of high withstand voltage characteristic as claimed in claim 2 it is characterised in that described
Mos field effect transistor is N-type mos field effect transistor.
4. there is the integrated circuit plasma protection structure of high withstand voltage characteristic as claimed in claim 3 it is characterised in that described
It is formed with the first doped region, the second doped region and the 3rd doped region, described second doped region and the 3rd doped region juxtaposition in substrate
Arrangement, described first doped region is formed in the second doped region；
It is formed with the 4th doped region, described first doped region and the 4th doped region collectively form described in described first doped region
One diode；
Described second doped region and the 3rd doped region collectively form described second diode；
It is formed with source area and drain region in described 3rd doped region, described 3rd doped region is formed with gate regions, described
Source area, drain region and gate regions collectively form described mos field effect transistor, described 4th doped region
It is connected with described gate regions；
The conduction type of described first doped region and the 3rd doped region is p-type, described second doped region, the 4th doped region, source electrode
The conduction type of area and drain region is N-type.
5. there is the integrated circuit plasma protection structure of high withstand voltage characteristic as claimed in claim 4 it is characterised in that described
It is formed with the 5th doped region, the conduction type of described 3rd doped region and the 5th doped region is identical in 3rd doped region.
6. there is the integrated circuit plasma protection structure of high withstand voltage characteristic as claimed in claim 2 it is characterised in that described
Mos field effect transistor is P-type mos field-effect transistor.
7. there is the integrated circuit plasma protection structure of high withstand voltage characteristic as claimed in claim 6 it is characterised in that described
Be formed with the first doped region, the second doped region and the 3rd doped region in substrate, described first doped region, the second doped region, the 3rd
Doped region Alignment, and the second doped region is positioned between the first doped region and the 3rd doped region；
It is formed with the 4th doped region, described first doped region and the 4th doped region collectively form described in described first doped region
One diode；
Described second doped region and the 3rd doped region collectively form described second diode；
It is formed with source area and drain region in described 3rd doped region, described 3rd doped region is formed with gate regions, described
Source area, drain region and gate regions collectively form described mos field effect transistor；
The conduction type of described first doped region and the 3rd doped region is N-type, described second doped region, the 4th doped region, source electrode
The conduction type of area and drain region is p-type.
8. there is the integrated circuit plasma protection structure of high withstand voltage characteristic as claimed in claim 7 it is characterised in that described
It is formed with the 5th doped region, the conduction type of described 3rd doped region and the 5th doped region is identical in 3rd doped region.
9. there is as described in any one in claim 1 to 7 the integrated circuit plasma protection structure of high withstand voltage characteristic, its
It is characterised by, between described first diode and described second diode, at least series aiding connection has one the 3rd diode.
10. a kind of integrated circuit plasma protection structure as any one of claim 1 to 9 with high withstand voltage characteristic
Forming method it is characterised in that include：
One substrate is provided；
Form the first diode, the second diode and mos field effect transistor, institute in described substrate
State the first diode and form series diode group with described second diode series aiding connection, described series diode group one end connects
The grid of described mos field effect transistor.
The forming method of the 11. integrated circuit plasma protection structures as claimed in claim 10 with high withstand voltage characteristic, its
It is characterised by, the forming method of described first diode, the second diode and mos field effect transistor
Including：
Form the first doped region, the second doped region, the 3rd doped region in the substrate, described second doped region and the 3rd doped region are simultaneously
Put arrangement, described first doped region is formed in the second doped region；
Form the 4th doped region in described first doped region, in described 3rd doped region, be formed with source area and drain region,
Described first doped region and the 4th doped region collectively form described first diode, and described second doped region and the 3rd doped region are altogether
With described second diode of composition；
It is formed with gate regions above described 3rd doped region, described source area, drain region and gate regions collectively form described gold
Belong to oxide semiconductor field effect transistor；
Wherein, the conduction type of described first doped region, the 3rd doped region and the 5th doped region is p-type, described second doped region,
The conduction type of the 4th doped region, source area and drain region is N-type.
The forming method of the 12. integrated circuit plasma protection structures as claimed in claim 11 with high withstand voltage characteristic, its
It is characterised by, form the 5th doped region, the conduction of described 3rd doped region and the 5th doped region also in described 3rd doped region
Type is identical.
The forming method of the 13. integrated circuit plasma protection structures as claimed in claim 10 with high withstand voltage characteristic, its
It is characterised by, the forming method of described first diode, the second diode and mos field effect transistor
Including：
Form the first doped region, the second doped region, the 3rd doped region in the substrate, described first doped region, the second doped region,
Three doped region Alignments, and the second doped region is positioned between the first doped region and the 3rd doped region；
Form the 4th doped region in described first doped region, in described 3rd doped region, be formed with source area and drain region,
Described first doped region and the 4th doped region collectively form described first diode, and described second doped region and the 3rd doped region are altogether
With described second diode of composition；
It is formed with gate regions above described 3rd doped region, described source area, drain region and gate regions collectively form described gold
Belong to oxide semiconductor field effect transistor；
Wherein, the conduction type of described first doped region, the 3rd doped region and the 5th doped region is N-type, described second doped region,
The conduction type of the 4th doped region, source area and drain region is p-type.
The forming method of the 14. integrated circuit plasma protection structures as claimed in claim 13 with high withstand voltage characteristic, its
It is characterised by, form the 5th doped region, the conduction of described 3rd doped region and the 5th doped region also in described 3rd doped region
Type is identical.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109037195A (en) * | 2017-06-12 | 2018-12-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111354723A (en) * | 2018-12-24 | 2020-06-30 | 爱思开海力士有限公司 | Semiconductor device with a plurality of transistors |
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| CN106206571A (en) * | 2016-08-31 | 2016-12-07 | 武汉新芯集成电路制造有限公司 | Two-way high resistant plasma protection circuit and manufacture method thereof |
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| CN109037195A (en) * | 2017-06-12 | 2018-12-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109037195B (en) * | 2017-06-12 | 2020-05-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111354723A (en) * | 2018-12-24 | 2020-06-30 | 爱思开海力士有限公司 | Semiconductor device with a plurality of transistors |
| CN111354723B (en) * | 2018-12-24 | 2024-02-27 | 爱思开海力士有限公司 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
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