CN106384734B - Integrated circuit plasma protection structure and forming method with high voltage characteristic - Google Patents
Integrated circuit plasma protection structure and forming method with high voltage characteristic Download PDFInfo
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- CN106384734B CN106384734B CN201611113099.1A CN201611113099A CN106384734B CN 106384734 B CN106384734 B CN 106384734B CN 201611113099 A CN201611113099 A CN 201611113099A CN 106384734 B CN106384734 B CN 106384734B
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 74
- 230000005669 field effect Effects 0.000 claims abstract description 71
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 53
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 238000012360 testing method Methods 0.000 description 25
- 230000005611 electricity Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of integrated circuit plasma protection structure and forming method thereof with high voltage characteristic; it include: substrate and the first diode being formed in substrate, the second diode and Metal Oxide Semiconductor Field Effect Transistor; the first diode and the second diode series aiding connection form series diode group, and series diode group one end connects the grid of the Metal Oxide Semiconductor Field Effect Transistor.In integrated circuit plasma protection structure provided by the invention with high voltage characteristic and forming method thereof; by the grid that one end of the series diode group of formation is connected to the Metal Oxide Semiconductor Field Effect Transistor; oxidize metal object semiconductor field effect transistor draining by the series diode group to when conducting in charge; the damage as caused by charge is avoided, and oxidizes metal the characteristic of object semiconductor field effect transistor reverse-biased breakdown voltage with higher.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of integrated circuit plasma with high voltage characteristic
Protect structure and forming method.
Background technique
By semicentennial high speed development, microelectric technique and the semiconductor technology for relying on microelectric technique are right
The development of human society produces revolutionary impact.Technological evaluation and monitoring in semiconductors manufacture need various test structures
As carrier, the input/output terminal for testing structure is required connect on metal pad (PAD), to carry out signal to test structure
Input and output.In technical process, metal PAD is very big charge-trapping antenna relative to test structure, and charge can pass through gold
Belong to PAD to conduct to test structure, stress is generated to test structure, causes test structure degradation even to fail, to lose function
Energy.So protecting to test structure, the charging damage in technical process is avoided to test structure, just can guarantee test structure just
Often assessment and monitoring manufacturing process.
The protection of test structure is avoided in meeting technical process outside the requirement of charging damage, and interference also to be avoided to survey as far as possible
The function of structure is tried, guarantees that test structure can be normally carried out test.Single diode and capacitive oxide are generallyd use at present
Two ways carries out the Metal Oxide Semiconductor Field Effect Transistor of protection test structure, by single diode or oxide electricity
The gate connected in parallel of appearance and tested object such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET), but single two pole
The easy reverse breakdown of tube capacity, capacitor are limited to the design that volume or capacity etc. are then unfavorable for semiconductor device structure.
Therefore, how to prevent semiconductor device structure from occurring one that charging damage is those skilled in the art's urgent need to resolve
Technical problem.
Summary of the invention
The integrated circuit plasma protection structure that the purpose of the present invention is to provide a kind of with high voltage characteristic and its
Forming method, to solve the problems, such as that charging damage occurs in semiconductor structure in the prior art.
In order to solve the above technical problems, the present invention provides a kind of integrated circuit plasma protection with high voltage characteristic
Structure, comprising: substrate and the first diode being formed in substrate, the second diode and metal oxide semiconductor field-effect
Transistor, the first diode and the second diode series aiding connection form series diode group, the series diode
One end of group connects the grid of the Metal Oxide Semiconductor Field Effect Transistor.
Preferably, in the integrated circuit plasma protection structure described with high voltage characteristic, two poles of the series connection
Doped region in the other end of pipe group and the Metal Oxide Semiconductor Field Effect Transistor common substrate.
Preferably, in the integrated circuit plasma protection structure described with high voltage characteristic, the metal oxidation
Object semiconductor field effect transistor is N-type Metal Oxide Semiconductor Field Effect Transistor.
Preferably, in the integrated circuit plasma protection structure described with high voltage characteristic, shape in the substrate
At having the first doped region, the second doped region and third doped region, first doped region, the second doped region, third doped region are simultaneously
Arrangement is set, and the second doped region is between the first doped region and third doped region；The 4th is formed in first doped region
Doped region, first doped region and the 4th doped region collectively form the first diode；Second doped region and third
Doped region collectively forms second diode；It is formed with source area and drain region in the third doped region, in the third
Gate regions are formed on doped region, the source area, drain region and gate regions collectively form the MOS field
Effect transistor, the 4th doped region are connect with the gate regions；The conductive-type of first doped region and third doped region
Type is N-type, and second doped region, the 4th doped region, source area and the conduction type of drain region are p-type.
Preferably, in the integrated circuit plasma protection structure described with high voltage characteristic, the third doping
It is formed with the 5th doped region in area, the conduction type of the third doped region and the 5th doped region is identical.
Preferably, in the integrated circuit plasma protection structure described with high voltage characteristic, the metal oxidation
Object semiconductor field effect transistor is P type metal oxide semiconductor field effect transistor.
Preferably, in the integrated circuit plasma protection structure described with high voltage characteristic, shape in the substrate
It is described at having the first doped region, the second doped region and third doped region, second doped region and third doped region Alignment
First doped region is formed in the second doped region；The 4th doped region, first doped region are formed in first doped region
The first diode is collectively formed with the 4th doped region；Second doped region and third doped region collectively form described second
Diode；It is formed with source area and drain region in the third doped region, is formed with gate regions on the third doped region, institute
It states source area, drain region and gate regions and collectively forms the Metal Oxide Semiconductor Field Effect Transistor；First doping
The conduction type of area and third doped region is p-type, the conduction of second doped region, the 4th doped region, source area and drain region
Type is N-type.
Preferably, in the integrated circuit plasma protection structure described with high voltage characteristic, the third doping
It is formed with the 5th doped region in area, the conduction type of the third doped region and the 5th doped region is identical.
Preferably, in the integrated circuit plasma protection structure described with high voltage characteristic, the one or two pole
At least series aiding connection has a third diode between pipe and second diode.
The forming method for the integrated circuit plasma protection structure with high voltage characteristic that the present invention also provides a kind of, packet
It includes: a substrate is provided；The first diode, the second diode and metal oxide semiconductor field-effect are formed in the substrate
Transistor, the first diode and the second diode series aiding connection form series diode group, the series diode
Group one end connects the grid of the Metal Oxide Semiconductor Field Effect Transistor.
Preferably, in the forming method of the integrated circuit plasma protection structure described with high voltage characteristic, institute
The forming method for stating the first diode, the second diode and Metal Oxide Semiconductor Field Effect Transistor includes: in substrate
The first doped region of middle formation, the second doped region, third doped region, first doped region, the second doped region, third doped region are simultaneously
Arrangement is set, and the second doped region is between the first doped region and third doped region；The 4th is formed in first doped region
Doped region, is formed with source area and drain region in the third doped region, and first doped region and the 4th doped region are common
The first diode is constituted, second doped region and third doped region collectively form second diode；Described
Gate regions are formed with above three doped regions, the source area, drain region and gate regions collectively form the metal oxide and partly lead
Body field effect transistor；Wherein, the conduction type of first doped region, third doped region and the 5th doped region is N-type, described
Second doped region, the 4th doped region, source area and the conduction type of drain region are p-type.
Preferably, in the forming method of the integrated circuit plasma protection structure described with high voltage characteristic, also
The conduction type of the 5th doped region of formation in the third doped region, the third doped region and the 5th doped region is identical.
Preferably, in the forming method of the integrated circuit plasma protection structure described with high voltage characteristic, institute
The forming method for stating the first diode, the second diode and Metal Oxide Semiconductor Field Effect Transistor includes: in substrate
The first doped region of middle formation, the second doped region, third doped region, second doped region and third doped region Alignment, institute
The first doped region is stated to be formed in the second doped region；The 4th doped region is formed in first doped region, is mixed in the third
Source area and drain region are formed in miscellaneous area, first doped region and the 4th doped region collectively form the first diode,
Second doped region and third doped region collectively form second diode；Grid are formed with above the third doped region
Polar region, the source area, drain region and gate regions collectively form the Metal Oxide Semiconductor Field Effect Transistor；Wherein,
The conduction type of first doped region, third doped region and the 5th doped region is N-type, second doped region, the 4th doping
The conduction type in area, source area and drain region is p-type.
Preferably, in the forming method of the integrated circuit plasma protection structure described with high voltage characteristic, also
The conduction type of the 5th doped region of formation in the third doped region, the third doped region and the 5th doped region is identical
In integrated circuit plasma protection structure provided by the invention with high voltage characteristic and forming method thereof,
First diode, the second diode and Metal Oxide Semiconductor Field Effect Transistor are formed in the substrate, by by described the
The one end for the series diode group that one diode is formed with the second diode series aiding connection connect the metal oxide half
The grid of conductor field effect transistor oxidizes metal object semiconductor field effect transistor in the described to passing through when conducting of charge
Series diode group is drained, and the damage as caused by charge is avoided, and oxidizes metal object semiconductor field effect transistor and have
The characteristic of higher reverse-biased breakdown voltage.
Detailed description of the invention
Fig. 1 is the circuit of the integrated circuit plasma protection structure with high voltage characteristic of the embodiment of the present invention one
Figure；
Fig. 2 is that integrated circuit plasma the cuing open for structure of protection with high voltage characteristic of the embodiment of the present invention one is shown
Figure；
Fig. 3 is the circuit of the integrated circuit plasma protection structure with high voltage characteristic of the embodiment of the present invention two
Figure；
Fig. 4 is that integrated circuit plasma the cuing open for structure of protection with high voltage characteristic of the embodiment of the present invention two is shown
Figure；
Fig. 5 is the forming method of the integrated circuit plasma protection structure with high voltage characteristic of the embodiment of the present invention
Step schematic diagram.
Specific embodiment
In order to keep objects, features and advantages of the present invention more obvious and easy to understand, attached drawing is please referred to.It should be clear that this explanation
Book structure depicted in this specification institute accompanying drawings, ratio, size etc., only to cooperate the revealed content of specification, for being familiar with this
The personage of technology understands and reads, and is not intended to limit the invention enforceable qualifications, therefore does not have technical essence meaning
Justice, the modification of any structure, the change of proportionate relationship or the adjustment of size are not influencing the effect of present invention can be generated and institute
Under the purpose that can reach, should all still it fall in the range of disclosed technology contents obtain and can cover.
Embodiment one
As shown in figures 1 and 3, the present invention provides a kind of integrated circuit plasma protection knot with high voltage characteristic
Structure, comprising: substrate and the first diode 20 being formed in substrate, the second diode 30 and metal oxide semiconductcor field effect
Transistor (MOSFET) 40 is answered, the first diode 20 forms series diode with 30 series aiding connection of the second diode
Group, series diode group one end connect the grid of the Metal Oxide Semiconductor Field Effect Transistor 40, the series connection
Doped region in the other end of diode group and 40 common substrate of Metal Oxide Semiconductor Field Effect Transistor.The gold
Belong to oxide semiconductor field effect transistor 40 as tested object, the first diode 20 and second diode 30
For protecting the Metal Oxide Semiconductor Field Effect Transistor 40, Metal Oxide Semiconductor Field Effect Transistor is being manufactured
Deng during will receive plasma damage, plasma charge can be guided by series diode group, thus avoid by
It is damaged caused by charge, since too high voltages lead to the reverse-biased breakdown of diode, so the introducing of single diode leads to metal
The grid of oxide semiconductor field effect transistor is unable to high voltage, and the present invention uses series diode group, aoxidizes to metal
When object semiconductor field effect transistor 40 carries out the situation such as testing, charge can be drained by series diode group, be improved simultaneously
Reverse-biased breakdown voltage.
Specifically as shown in Fig. 2, being formed with the first doped region 21, the second doped region 31, third doped region 40, institute in substrate 10
40 Alignment of the second doped region 31 and third doped region is stated, first doped region 21 is formed in the second doped region 31, institute
State that the first doped region 21 is identical with the conduction type of third doped region 40, the conduction type of second doped region 31 and described the
One doped region 21 and third doped region 40 are opposite.It is formed with the 4th doped region 22 in first doped region 21, described first
Doped region 21 is different with the conduction type of the 4th doped region 22, and first doped region 21 and the 4th doped region 22 collectively form institute
State first diode 20.Second doped region 31 collectively forms second diode 30 with third doped region 40.Described
It is formed with source area 41 and drain region 42 in third doped region 40, gate regions 43, institute are formed on the third doped region 40
State the conduction type of source area 41 and drain region 42 and the conduction type of the third doped region 40 on the contrary, the source area 41,
Drain region 42 and gate regions 43 collectively form the Metal Oxide Semiconductor Field Effect Transistor 40.Second diode 30
With the doped region (i.e. third doped region 40) in 40 common substrate of Metal Oxide Semiconductor Field Effect Transistor.Here,
4th doped region 22 is one end of series diode group, and the third doped region 40 is the another of series diode group
End.
As shown in Fig. 2, the conduction type of first doped region 21, third doped region 40, the 5th doped region 44 is p-type,
Second doped region 31, the 4th doped region 22, source area 41, drain region 42 conduction type be N-type.Thus, metal oxidation
Object semiconductor field effect transistor 40 is N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET).
Further, the 5th doped region 44,40 He of third doped region are also formed in the third doped region 40
The conduction type of 5th doped region 44 is identical, and the 5th doped region 44 is used as first terminal, the gate regions 43 for drawing
It draws and is used as Second terminal.
4th doped region 22 can be formed by source drain dopant mode together with source area 41 and drain region 42, institute
Stating the first doped region 21 can be formed by trap doping way together with third doped region 40.It is understood that can be by not
Series diode group structure required for same doping way forms the diode of different structure and formed, it is not limited to Fig. 2
Shown in structure.
It in a preferred approach, can also include one the 3rd 2 between the first diode 20 and second diode 30
Pole pipe, first diode 20 and second diode 30 described in the third diode series aiding connection, more by series aiding connection
More diodes can further improve the reverse-biased breakdown voltage of series diode group, to improve metal oxide semiconductcor field effect
Answer the reverse withstand voltage characteristic of transistor.
As shown in figure 5, the present invention also provides a kind of, the integrated circuit plasma with high voltage characteristic protects structure
Forming method, comprising:
Step S10: a substrate is provided；
Step S20: the first diode, the second diode and metal oxide semiconductcor field effect are formed in the substrate
Transistor is answered, the first diode and the second diode series aiding connection form series diode group, two poles of the series connection
Pipe group one end connects the grid of the Metal Oxide Semiconductor Field Effect Transistor, the other end of the series diode group with
Doped region in the Metal Oxide Semiconductor Field Effect Transistor common substrate.
It is detailed with reference to the accompanying drawing to introduce the formation with the integrated circuit plasma protection structure of high voltage characteristic
Method.
Firstly, providing a substrate 10, the substrate 10 is made of other semiconductor materials such as silicon or germanium, the shape in substrate 10
At the well known semiconductor structure of needs.
Then, the first diode 20, the second diode 30 and metal-oxide semiconductor (MOS) are formed in the substrate 10
Field effect transistor 40, the first diode 20 form series diode group, institute with 30 series aiding connection of the second diode
State the grid that series diode group one end connects the Metal Oxide Semiconductor Field Effect Transistor 40, the series diode
The other end and the doped region in 40 common substrate of Metal Oxide Semiconductor Field Effect Transistor of group.
Specifically, first diode 20, the second diode 30 and metal oxide can be formed as follows
Semiconductor field effect transistor 40:
Firstly, forming the first doped region 21, the second doped region 31, third doped region 40 in substrate 10, described first mixes
Miscellaneous area 21, the second doped region 31,40 Alignment of third doped region, and the second doped region 31 are located at the first doped region 21 and third
Between doped region 40, first doped region 21 is identical with the conduction type of third doped region 40, second doped region 31
Conduction type is opposite with first doped region 21 and third doped region 40；
Then, the 4th doped region 22 is formed in first doped region 21, is formed in the third doped region 40
Source area 41 and drain region 42；First doped region 21 is different with the conduction type of the 4th doped region 22, first doping
Area 21 and the 4th doped region 22 collectively form the first diode 20；Second doped region 31 and third doped region 40 are common
Constitute second diode 30；The conduction of the source area 41 and the conduction type of drain region 42 and the third doped region 40
Type is opposite；
Then, gate regions 43, the source area 41, drain region 42 and grid are formed with above the third doped region 40
Area 43 collectively forms the Metal Oxide Semiconductor Field Effect Transistor 40.Second diode 30 is aoxidized with the metal
Doped region (i.e. third doped region 40) in 40 common substrate of object semiconductor field effect transistor.
Further, the 5th doped region 44, the third doped region 40 and the are formed also in the third doped region 40
The conduction type of five doped regions 44 is identical, and the 5th doped region 44 is used as first terminal for drawing, the 4th doped region 22 with
The gate regions 43 connect, and the gate regions 43, which are drawn, is used as Second terminal.
Traditional protected mode using single diode, lower, the excessive electricity of the reverse-biased breakdown voltage of single diode
Stress will lead to the reverse-biased breakdown of diode, and test structure is made just to lose normal function, so single diode protection mode can limit
Some high voltage tests (such as FN tunnelling accelerated test) is made, more comprehensively thorough test analysis is unfavorable for, using oxide electricity
The protected mode of appearance needs the capacitive oxide of large area to share technique charge, and chip occupying area is unfavorable for testing structure
Design.Protected mode compared to traditional single diode or capacitive oxide is being surveyed using test structure of the invention
During examination, first diode 20 and the second diode 30 are on state, and the charge generated in test preferentially passes through the one or two
Pole pipe 20 and the second diode 30 guide, and realize and protect to tested object (Metal Oxide Semiconductor Field Effect Transistor),
Also, the test structure and traditional process compatible, not chip occupying area.
Embodiment two
The present embodiment is that Metal Oxide Semiconductor Field Effect Transistor 40 is p-type gold with the difference place of embodiment one
Belong to oxide semiconductor field effect transistor (PMOSFET).
Specifically as shown in figure 4, being formed with the first doped region 21, the second doped region 31, third doped region 40, institute in substrate 10
The first doped region 21, the second doped region 31,40 Alignment of third doped region are stated, and the second doped region 31 is located at the first doped region
Between 21 and third doped region 40, first doped region 21 is identical with the conduction type of third doped region 40, and described second mixes
The conduction type in miscellaneous area 31 is opposite with first doped region 21 and third doped region 40.It is formed in first doped region 21
There is the 4th doped region 22, first doped region 21 is different with the conduction type of the 4th doped region 22, first doped region 21
The first diode 20 is collectively formed with the 4th doped region 22.Second doped region 31 is collectively formed with third doped region 40
Second diode 30.It is formed with source area 41 and drain region 42 in the third doped region 40, is adulterated in the third
Gate regions 43, the conduction of the conduction type and the third doped region 40 of the source area 41 and drain region 42 are formed in area 40
Type is on the contrary, the source area 41, drain region 42 and gate regions 43 collectively form the metal oxide semiconductor field-effect crystalline substance
Body pipe 40.Second diode 30 and the doped region in 40 common substrate of Metal Oxide Semiconductor Field Effect Transistor
(i.e. third doped region 40).Here, the 4th doped region 22 is one end of series diode group, the third doped region 40
The as other end of series diode group.
As shown in figure 4, the conduction type of first doped region 21, third doped region 40, the 5th doped region 44 is N-type,
Second doped region 31, the 4th doped region 22, source area 41, drain region 42 conduction type be p-type.
Further, the 5th doped region 44,40 He of third doped region are also formed in the third doped region 40
The conduction type of 5th doped region 44 is identical, and the 5th doped region 44 is used as first terminal, the gate regions 43 for drawing
It draws and is used as Second terminal.
First diode 20, the second diode 30 and MOS field can be formed as follows
Effect transistor 40:
Firstly, forming the first doped region 21, the second doped region 31, third doped region 40 in substrate 10, described second mixes
40 Alignment of miscellaneous area 31 and third doped region, first doped region 21 are formed in the second doped region 31, and described first mixes
Miscellaneous area 21 is identical with the conduction type of third doped region 40, the conduction type of second doped region 31 and first doped region
21 and third doped region 40 it is opposite；
Then, the 4th doped region 22 is formed in first doped region 21, is formed in the third doped region 40
Source area 41 and drain region 42；First doped region 21 is different with the conduction type of the 4th doped region 22, first doping
Area 21 and the 4th doped region 22 collectively form the first diode 20；Second doped region 31 and third doped region 40 are common
Constitute second diode 30；The conduction of the source area 41 and the conduction type of drain region 42 and the third doped region 40
Type is opposite；
Then, gate regions 43, the source area 41, drain region 42 and grid are formed with above the third doped region 40
Area 43 collectively forms the Metal Oxide Semiconductor Field Effect Transistor 40.Second diode 30 is aoxidized with the metal
Doped region (i.e. third doped region 40) in 40 common substrate of object semiconductor field effect transistor.
Further, the 5th doped region 44, the third doped region 40 and the are formed also in the third doped region 40
The conduction type of five doped regions 44 is identical, and the 5th doped region 44 is used as first terminal for drawing, the 4th doped region 22 with
The gate regions 43 connect, and the gate regions 43, which are drawn, is used as Second terminal.
In conclusion in the integrated circuit plasma protection structure and its shape provided by the invention with high voltage characteristic
At in method, first diode, the second diode and Metal Oxide Semiconductor Field Effect Transistor are formed in the substrate, is passed through
The one end for the series diode group that the first diode and the second diode series aiding connection are formed is connect the metal
The grid of oxide semiconductor field effect transistor oxidizes metal object semiconductor field effect transistor in charge to when conducting
Drained by the series diode group, avoid the damage as caused by charge, and it is brilliant to oxidize metal object semiconductor field
The characteristic of body pipe reverse-biased breakdown voltage with higher, so as to be formed for testing metal oxide semiconductor field effect transistor
The test structure of pipe.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (9)
1. a kind of integrated circuit plasma with high voltage characteristic protects structure characterized by comprising substrate and shape
At first diode, the second diode and the Metal Oxide Semiconductor Field Effect Transistor in substrate, the one or two pole
Pipe forms series diode group with the second diode series aiding connection, and one end of the series diode group connects the metal
The grid of oxide semiconductor field effect transistor；The other end and the metal-oxide semiconductor (MOS) of the series diode group
Doped region in field effect transistor common substrate；
And the first doped region, the second doped region and third doped region are formed in the substrate, second doped region and
Three doped region Alignments, first doped region are formed in the second doped region；
The 4th doped region is formed in first doped region, first doped region and the 4th doped region collectively form described
One diode；Second doped region and third doped region collectively form second diode；
It is formed with source area and drain region in the third doped region, is formed with gate regions on the third doped region, it is described
Source area, drain region and gate regions collectively form the Metal Oxide Semiconductor Field Effect Transistor, the 4th doped region
It is connect with the gate regions；
The 5th doped region, the conduction type phase of the third doped region and the 5th doped region are formed in the third doped region
Together.
2. the integrated circuit plasma with high voltage characteristic protects structure as described in claim 1, which is characterized in that described
Metal Oxide Semiconductor Field Effect Transistor is N-type Metal Oxide Semiconductor Field Effect Transistor.
3. the integrated circuit plasma with high voltage characteristic protects structure as claimed in claim 2, which is characterized in that
The conduction type of first doped region and third doped region is p-type, second doped region, the 4th doped region, source electrode
The conduction type of area and drain region is N-type.
4. the integrated circuit plasma with high voltage characteristic protects structure as described in claim 1, which is characterized in that described
Metal Oxide Semiconductor Field Effect Transistor is P type metal oxide semiconductor field effect transistor.
5. the integrated circuit plasma with high voltage characteristic protects structure as claimed in claim 4, which is characterized in that
The conduction type of first doped region and third doped region is N-type, second doped region, the 4th doped region, source electrode
The conduction type of area and drain region is p-type.
6. the integrated circuit plasma as described in any one of claim 1 to 5 with high voltage characteristic protects structure,
It is characterized in that, at least series aiding connection has a third diode between the first diode and second diode.
7. a kind of integrated circuit plasma as described in any one of claims 1 to 6 with high voltage characteristic protects structure
Forming method characterized by comprising
One substrate is provided；
The first diode, the second diode and Metal Oxide Semiconductor Field Effect Transistor, institute are formed in the substrate
It states first diode and the second diode series aiding connection forms series diode group, the connection of series diode group one end
The grid of the Metal Oxide Semiconductor Field Effect Transistor；
Wherein, the forming method of first diode, the second diode and Metal Oxide Semiconductor Field Effect Transistor
Include:
The first doped region, the second doped region, third doped region are formed in the substrate, and second doped region and third doped region are simultaneously
Arrangement is set, first doped region is formed in the second doped region；
The 4th doped region is formed in first doped region, is formed with source area and drain region in the third doped region,
First doped region and the 4th doped region collectively form the first diode, and second doped region and third doped region are total
With composition second diode；
Gate regions are formed with above the third doped region, the source area, drain region and gate regions collectively form the gold
Belong to oxide semiconductor field effect transistor, forms the 5th doped region, the third doped region also in the third doped region
It is identical with the conduction type of the 5th doped region.
8. the forming method of the integrated circuit plasma protection structure with high voltage characteristic as claimed in claim 7, special
Sign is, the conduction type of first doped region, third doped region and the 5th doped region is p-type, second doped region, the
Four doped regions, source area and the conduction type of drain region are N-type.
9. the forming method of the integrated circuit plasma protection structure with high voltage characteristic as claimed in claim 7, special
Sign is, the conduction type of first doped region, third doped region and the 5th doped region is N-type, second doped region, the
Four doped regions, source area and the conduction type of drain region are p-type.
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| KR20200078968A (en) * | 2018-12-24 | 2020-07-02 | 에스케이하이닉스 주식회사 | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545914A (en) * | 1993-10-27 | 1996-08-13 | Rohm Co., Ltd | Semiconductor device having zener diodes with temperature stability between base and collector regions |
| CN101083264A (en) * | 2006-06-02 | 2007-12-05 | 中芯国际集成电路制造(上海)有限公司 | Proctive circuit of metal-oxide-semiconductor transistor and its producing method |
| CN106206571A (en) * | 2016-08-31 | 2016-12-07 | 武汉新芯集成电路制造有限公司 | Two-way high resistant plasma protection circuit and manufacture method thereof |
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2016
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545914A (en) * | 1993-10-27 | 1996-08-13 | Rohm Co., Ltd | Semiconductor device having zener diodes with temperature stability between base and collector regions |
| CN101083264A (en) * | 2006-06-02 | 2007-12-05 | 中芯国际集成电路制造(上海)有限公司 | Proctive circuit of metal-oxide-semiconductor transistor and its producing method |
| CN106206571A (en) * | 2016-08-31 | 2016-12-07 | 武汉新芯集成电路制造有限公司 | Two-way high resistant plasma protection circuit and manufacture method thereof |
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