CN102708268B - Method for modeling metal oxide semiconductor (MOS) device - Google Patents

Abstract

The invention provides a method for modeling a metal oxide semiconductor (MOS) device. The MOS device comprises a first type of STI structure at a source end and a second type of STI structure at a drain end. The method for modeling the MOS device comprises the following steps of: a) establishing a group of parameters for defining the distance from a channel region of the device to the first type of STI structure and the distance from the channel region of the device to the second type of STI structure; b) establishing an analytical model of the group of parameters on the influence of the mobility ratio, wherein the analytical model comprises a coefficient to be determined; c) testing a first type of MOS device comprising the first type of STI structure at the source end and the drain end and a second type of MOS device comprising the second type of STI structure at the source end and the drain end, and acquiring the testing data; and d) determining the coefficient of the analytical model according to the testing data. The modeling method is simple and practicable, high in operability and wide in application range.

Description

The modeling method of MOS device

Technical field

The present invention relates to device modeling field, be particularly related to a kind of to contain shallow trench isolation from (STI simultaneously, shallow trench isolation) structure and super shallow trench isolation are from the method for the MOS device modeling of (VSTI, very shallow trenchisolation) structure.

Background technology

Along with the complexity of integrated circuit (IC) design is more and more higher, size is more and more less, and the effect of isolation technology in integrated circuit is manufactured is more and more important.Isolation technology under CMOS technique mainly comprises dielectric material isolation and reverse PN junction isolation etc., and wherein dielectric material is isolated in elimination parasitic transistor, reduces mutual capacitance, and all there is outstanding performance the aspects such as latch-up of inhibition metal-oxide-semiconductor.In the technique of 3-0.35 μ m, selective oxidation (LOCOS) technique is widely used, but this technique has self defect: (1) beak (bird ' s beak) structure makes a silicon dioxide invade an active area; (2) oxygen is infused in pyroprocess and occurs to distribute again, causes the narrow width effect (narrow width effect) of active device; (3) silicon dioxide is in narrow isolated area attenuation; (4) uneven surface configuration.These defects seem particularly outstanding when entering into 0.18 μ m and following process node, and LOCOS technique is unavailable.Therefore,, along with device is developed to nanometer by deep-submicron, shallow trench isolation has substituted from (STI) technology the isolation technology that LOCOS technology becomes main flow.STI technology is compared with LOCOS technology, have complete in beak, completely planarization, good advantages such as anti-breech lock, and STI technology can avoid high-temperature technology, reduces to finish spacing and junction capacity, guaranteed the area of active area, improved integrated level.

Along with reducing of device active region area, STI stress will be can not ignore the impact of device performance, make the performance of device and the area of device active region and device strongly relevant in the position of active area, it not only exerts an influence to device threshold voltage, to the carrier mobility of device, also will exert an influence.In addition, at SOI(silicon-on-insulator) in MOS device, in order to overcome wide channel device, in Width upper body, draw the bad problem of effect, can in device length direction, carry out body and draw.In source, adopting VSTI to carry out body draws, at drain terminal, uses conventional sti structure.Because the degree of depth of STI and VSTI is different, so its stress intensity is different, and the impact that device is caused is also different.Therefore current stress model has only been considered the impact of STI, does not consider STI and VSTI for the impact of circuit performance, is necessary that the impact of comprehensive STI and VSTI carries out modeling to this SOI MOS device.

Summary of the invention

For the method for setting up before model, only consider that STI is for the shortcoming of device performance impact, the invention provides a kind of modeling method of MOS device, described MOS device comprises the sti structure of the first kind in source, the sti structure that comprises Second Type at drain terminal, the method comprises: the channel region of a) setting up definition device is to the distance of the sti structure of the first kind and to one group of parameter of the distance of the sti structure of Second Type; B) set up the analytic model of described one group of parameter on the impact of mobility, described analytic model comprises coefficient to be determined; C) at source and drain terminal, all comprise the first kind sti structure first kind MOS device and at the Second Type MOS device that source and drain terminal all comprise the sti structure of Second Type, test, obtain test data; D) according to described test data, determine the coefficient of described analytic model.

According to the modeling method of taking part in building of carrying provided by the invention, by testing only containing the device of STI and VSTI respectively, and counter stress model extraction parameter, comprehensively determine again the impact of the two, determine output characteristics and the transfer characteristics model of the MOS device that simultaneously contains STI (shallow trench isolation from) and VSTI (super shallow trench isolation from).Simple in method, workable, filled up the blank of carrying out modeling to contain the device of STI and VSTI simultaneously.

Accompanying drawing explanation

Fig. 1 is the process flow diagram that simultaneously contains the MOS device modeling method of STI (shallow trench isolation from) and VSTI (super shallow trench isolation from) according to the present invention;

The element layout schematic diagram that only contains STI or only isolate containing VSTI that Fig. 2 provides for one embodiment of the present of invention;

The element layout schematic diagram of STI isolation and VSTI isolation is provided when providing for one embodiment of the present of invention Fig. 3.

Embodiment

For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.

Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.

Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.

Below with reference to Fig. 1 ~ Fig. 3, the present invention is described.Fig. 1 is the process flow diagram that simultaneously contains the MOS device modeling method of STI (shallow trench isolation from) and VSTI (super shallow trench isolation from) according to the present invention.The domain schematic diagram of the MOS device of STI isolation structure and VSTI isolation structure is provided when providing for one embodiment of the present of invention Fig. 3.This MOS device is SOI MOS device, for the ease of carrying out body in source, draws, and source isolated area 301 is used VSTI structure.302 uses of drain terminal isolated area for example, for the conventional sti structure (, the degree of depth equals the thickness of SOI top layer silicon, cuts off active area completely) of SOI device.

In step S101, the channel region of setting up definition device is for example, to the distance of the sti structure (VSTI structure) of the first kind and for example, to one group of parameter of the distance of the sti structure (conventional sti structure) of Second Type.

As shown in Figure 3, can for example be defined into the channel region (part of grid below) of device, to the distance of the sti structure (VSTI structure) of the first kind by operation parameter SA, operation parameter SB for example defines the channel region of device, to the distance of the sti structure (conventional sti structure) of Second Type.

In step S 102, set up the analytic model of described one group of parameter on the impact of mobility, described analytic model comprises coefficient to be determined.For example can use following formula to effective mobility μ _effmodeling:

$u_{\mathrm{eff}}=\frac{1+r_{\mathrm{ueff}}(\mathrm{SA},\mathrm{SB})}{1+r_{\mathrm{ueff}}({\mathrm{SA}}_{\mathrm{ref}},{\mathrm{SB}}_{\mathrm{ref}})}{u}_{\mathrm{eff}0},$ Wherein

$r_{\mathrm{ueff}}(\mathrm{SA},\mathrm{SB})=\frac{\mathrm{KU}01}{\mathrm{Kstress}\_u01}*\frac{1}{\mathrm{SA}}+\frac{\mathrm{KU}02}{\mathrm{Kstress}\_u02}*\frac{1}{\mathrm{SB}},$

SA wherein _refand SB _reffor thinking that the impact of STI stress is zero larger size substantially, μ _eff0for SA=SA _refand SB=SB _reftime mobility.For example, in test, can first choose SA=SA _refand SB=SB _refthe STI device extracting parameter of (for example SA, SB is 5um), as the basic model of ignoring STI and VSTI stress influence.Now at SA _ref=5um, SB _refin the situation of=5um, obtain initial rate of transform u _eff0.

KU1 and Kstress u1 and KU2 and Kstress u2 are coefficient to be determined.The sti structure (for example VSTI structure) wherein characterizing due to the first kind of source brings the part of impact to be:

$\frac{\mathrm{KU}01}{\mathrm{Kstress}\_u01}*\frac{1}{\mathrm{SA}}$

Sign for example, because the sti structure (conventional sti structure) of the Second Type of drain terminal brings the part of impact to be:

$\frac{\mathrm{KU}02}{\mathrm{Kstress}\_u02}*\frac{1}{\mathrm{SB}}.$

The following describes how to confirm KU1 and Kstress u1 and KU2 and Kstress u2.

In step S 103, at source and drain terminal, all comprise the first kind sti structure first kind MOS device and at the Second Type MOS device that source and drain terminal all comprise the sti structure of Second Type, test, obtain test data.For example, to using the device of device architecture as shown in Figure 2 to test.For example the transfer characteristics of device and output characteristics are tested.

Fig. 2 for one embodiment of the present of invention provide only containing STI or only containing the domain schematic diagram of the device of VSTI isolation.In this step, to source and drain terminal, use the device of identical isolated area 201 to test, for example, first to source and drain terminal, all use the device of sti structure to test.During test, by having different SA, the MOS device of SB parameter is measured, and obtains the u of each device _eff, every couple of SA, SB and u _effform one group of measurement data, so a plurality of MOS devices are measured to the measurement data of group more than first.Similarly, to source and drain terminal, all use the device of VSTI structure to test.During test, by having different SA, the MOS device of SB parameter is measured, and obtains the u of each device _eff, every couple of SA, SB and u _effform one group of measurement data, so a plurality of MOS devices are measured to the measurement data of group more than second.

In step S104, according to test data, determine the coefficient of described analytic model.

To source and drain terminal, all use sti structure and source and drain terminal all to use the similar stress model of the device use of VSTI structure:

$u_{\mathrm{eff}}=\frac{1+r_{\mathrm{ueff}}(\mathrm{SA},\mathrm{SB})}{1+r_{\mathrm{ueff}}({\mathrm{SA}}_{\mathrm{ref}},{\mathrm{SB}}_{\mathrm{ref}})}{u}_{\mathrm{eff}0}---\left(1\right)$

U wherein _effrepresent the mobility recording, u _eff0represent initial mobility, SA, SB is corresponding to u _effgrid (or channel region) at directions X (orientation) distance apart from STI isolated area 201 borders, both sides, SA _ref, SB _reffor corresponding to u _eff0grid at directions X the initial distance (as mentioned above, being 5um) apart from STI isolated area border, both sides, the r in expression formula _ueffbe grid at directions X the function apart from the distance on STI isolated area border, both sides, function expression is:

$r_{\mathrm{ueff}}(X,Y)=\frac{\mathrm{KU}0}{\mathrm{Kstress}\_u0}(\frac{1}{X}+\frac{1}{Y})---\left(2\right)$

X wherein, Y be grid at directions X the distance apart from STI isolated area border, both sides, value SA, SB and SA respectively in (1) _ref, SB _refsubstitution.

The data that obtain in conjunction with test, just can extract parameter K U0 and Kstress u0 in (2) formula.In the present embodiment, more than the first group measurement data that in integrating step S 103, test is arrived, through said extracted process, the stress model parameter value that obtains first kind device is KU01 and Kstress u01.More than the second group measurement data that in integrating step S103, test is arrived, through said extracted process, the stress model parameter value that obtains Second Type device is KU02 and Kstress u02.Parameter K U01 and Kstress u01 and KU02 and Kstress u02 are applied to the model of setting up in step 101, completed to source isolated area 301 use VSTI structure drain terminal isolated areas 302 use for the modeling of the MOS device of the conventional sti structure of SOI device.

Above-described embodiment is preferably embodiment of the present invention; but embodiments of the present invention are not restricted to the described embodiments; other any do not deviate from change, the modification done under Spirit Essence of the present invention and principle, substitutes, combination, simplify; all should be equivalent substitute mode, within being included in protection scope of the present invention.

Claims (4)

1. a modeling method for mos device, described mos device comprises the sti structure of the first kind in source, comprise the sti structure of Second Type at drain terminal, the method comprises:

A) channel region of setting up definition device is to the distance of the sti structure of the first kind and to one group of parameter of the distance of the sti structure of Second Type;

B) set up the analytic model of described one group of parameter on the impact of mobility, described analytic model comprises coefficient to be determined;

C) at source and drain terminal, all comprise the first kind sti structure first kind mos device and at the Second Type mos device that source and drain terminal all comprise the sti structure of Second Type, test, obtain test data;

D) according to described test data, determine the coefficient of described analytic model;

By following formula to effective mobility μ _effmodeling:

$u_{\mathrm{eff}}=\frac{1+r_{\mathrm{ueff}}(\mathrm{SA},\mathrm{SB})}{1+r_{\mathrm{ueff}}({\mathrm{SA}}_{\mathrm{ref}},{\mathrm{SB}}_{\mathrm{ref}})}{u}_{\mathrm{eff}0},$ Wherein

$r_{\mathrm{ueff}}(\mathrm{SA},\mathrm{SB})=\frac{\mathrm{KU}1}{\mathrm{Kstress}\_u1}*\frac{1}{\mathrm{SA}}+\frac{\mathrm{KU}2}{\mathrm{Kstress}\_u2}*\frac{1}{\mathrm{SB}},$ Wherein

SA is that the channel region of device is to think that the impact of sti stress is zero larger size substantially to the STI of the first kind; SA _refand SB _ref, SA and SB unit be um; μ _eff0for SA=SA _refand SB=SB _reftime the mobility measured, ku1 and kstress_u1 and ku2 and kstress_u2 are coefficient to be determined; r _ueffbe grid in x direction the function apart from the distance on STI isolated area border, both sides, its unit is 1/um.

2. method according to claim 1, wherein the sti structure of the first kind and the sti structure of Second Type have the different degree of depth.

3. method according to claim 1, wherein the sti structure of the first kind is super shallow sti structure, the sti structure of Second Type is conventional sti structure.

4. method according to claim 1, wherein mos device is soimos device.