CN104037164A - Testing structure and method for grid coupling efficiency - Google Patents
Testing structure and method for grid coupling efficiency Download PDFInfo
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- CN104037164A CN104037164A CN201410287029.2A CN201410287029A CN104037164A CN 104037164 A CN104037164 A CN 104037164A CN 201410287029 A CN201410287029 A CN 201410287029A CN 104037164 A CN104037164 A CN 104037164A
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Abstract
The invention discloses a testing structure and method for grid coupling efficiency. The testing structure for the grid coupling efficiency comprises a first testing structure and a second testing structure, wherein the first testing structure comprises a first floating grid that is formed on a substrate, and a control grid formed on the first floating grid; the second testing structure comprises a second floating grid that is structured the same as the first floating grid and formed on the substrate; a source leakage end is formed in the substrate. The testing method comprises the step of testing a transconductance of the first testing structure and the second testing structure, wherein the grid coupling efficiency is the quotient obtained by dividing the transconductance of the second testing structure by the transconductance of the first testing structure. With the adoption of the testing structure and method for the grid coupling efficiency, the obtained grid coupling efficiency data is high in reliability; in addition, the operation is simple, convenient and efficient; WAT (Wafer Acceptance Test) test applies conveniently.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of grid coupling efficiency test structure and method of testing.
Background technology
Along with the high speed development of portable electric appts, more and more higher to the requirement of data storage.Be divided into volatile memory and nonvolatile memory for the semiconductor memory of storing data.In nonvolatile memory, flash memory (flash memory) is due to its very high chip-stored density, and Technological adaptability preferably, become a kind of very important device.And the flash memory of floating gate structure is the big hot topic in flash memory.
In floating gate flash memory product, grid coupling efficiency is one of most important index.Grid coupling efficiency is defined as the control ability of control gate to floating boom, and coupling efficiency is larger, and on control gate, to be coupled to voltage above floating boom just larger for added voltage, means that control gate is stronger to the control ability of floating boom.
From electrical angle analysis, coupling efficiency is higher, and the speed that memory cell writes and wipes is just faster.
From physical angle analysis, grid coupling efficiency can reflect the technique change above structure such as control gate size, floating boom size, active area size, floating boom-control gate thickness of dielectric layers, tunnel oxide layer thickness, floating boom height, shallow trench isolating oxide layer height.
But due to the complexity of this parameter, in existing wafer WAT test, do not have special or unified method of testing.At present, in the industry this parameter is mainly contained to two kinds of characterizing methods, the one, simply use without the threshold voltage of two different components or the ratio of saturation current of control gate structure and floating boom-control gate structure and reflect grid coupling efficiency.But the result distortion factor that the method obtains is larger, the diversity factor of the result obtaining with threshold voltage or by the method for saturation current is up to 30%.
Another kind method is in the test of wafer yield, memory cell is operated with different write/erase voltage graphs, then obtains real grid coupling efficiency with complex calculations.But this method of testing is very complicated, cannot in wafer production factory, before shipment, test.
Summary of the invention
The object of the invention is to, a kind of grid coupling efficiency test structure and method of testing are provided, with the convenient grid coupling efficiency that records accurately.
To this, the invention provides a kind of grid coupling efficiency test structure, comprising:
The first test structure, described the first test structure comprises the control gate on the first floating boom and the first floating boom being formed on substrate;
The second test structure, described the second test structure comprises the second floating boom being formed on substrate;
Described the first floating boom is identical with the second floating gate structure, forms active drain terminal in described substrate.
Optionally, for described grid coupling efficiency test structure, described the first test structure is identical with memory cell structure.
The invention provides the method for utilizing above-mentioned grid coupling efficiency test structure to test, comprising: record the mutual conductance of the first test structure and the mutual conductance of the second test structure, the mutual conductance of mutual conductance/the first test structure of grid coupling efficiency=the second test structure.
Optionally, for the method for testing of described grid coupling efficiency, the mutual conductance of described the first test structure=(threshold voltage under threshold voltage-the first test structure the second electric current under first test structure the first electric current)/(the first electric current-the second electric current);
Mutual conductance=(threshold voltage under threshold voltage-the second test structure 1 the 4th electric current under the second test structure the 3rd electric current)/(three electric current-, tetra-electric currents) of the second test structure.
Optionally, for the method for testing of described grid coupling efficiency, the threshold voltage method of testing of described the first test structure comprises:
Apply respectively voltage at drain terminal, control gate and substrate, source ground connection, test source-leakage current curve, the voltage while reading a certain electric current on grid, threshold voltage while being this electric current.
Optionally, for the method for testing of described grid coupling efficiency, described drain terminal voltage 0.1～0.5V, control-grid voltage 0～9V, underlayer voltage-6～-8V.
Optionally, for the method for testing of described grid coupling efficiency, the threshold voltage method of testing of described the second test structure comprises:
Apply respectively voltage at drain terminal, floating boom and substrate, source ground connection, test source-leakage current curve, the voltage while reading a certain electric current on grid, threshold voltage while being this electric current.
Optionally, for the method for testing of described grid coupling efficiency, described drain terminal voltage 0.1～0.5V, control-grid voltage 0～9V, underlayer voltage-6～-8V.
Optionally, for the method for testing of described grid coupling efficiency, described current range is 1E-12A～1E-6A.
Compared with prior art, in grid coupling efficiency test structure provided by the invention and method of testing, by forming the first test structure and the second test structure, described the first test structure has floating boom and control gate, the second test structure has floating boom, and the two floating boom is identical, in the time of test, be divided by by the mutual conductance of the second test structure and the mutual conductance of the first test structure, can obtain grid coupling efficiency.Compared to existing technology, the grid coupling efficiency data reliability that this method obtains is high, and easy and simple to handle efficient, also can be used in WAT test.
Brief description of the drawings
Fig. 1 is the schematic diagram of the first test structure of embodiment of the present invention grid coupling efficiency test structure;
Fig. 2 is the schematic diagram of the second test structure of embodiment of the present invention grid coupling efficiency test structure;
Fig. 3 is the flow chart of the method for testing of embodiment of the present invention grid coupling efficiency.
Embodiment
Below in conjunction with schematic diagram, grid coupling efficiency test structure of the present invention and method of testing are described in more detail, the preferred embodiments of the present invention are wherein represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of grid coupling efficiency test structure is provided, and comprising: the first test structure, and described the first test structure comprises the control gate on the first floating boom and the first floating boom being formed on substrate; The second test structure, described the second test structure comprises the second floating boom being formed on substrate; Described the first floating boom is identical with the second floating gate structure, forms active drain terminal in described substrate.
By recording the mutual conductance of the first test structure and the mutual conductance of the second test structure, the mutual conductance of mutual conductance/the first test structure of grid coupling efficiency=the second test structure.This is the method for testing of grid coupling efficiency in the present invention.
Below enumerate the preferred embodiment of described grid coupling efficiency test structure, to clearly demonstrate content of the present invention, will be clear that, content of the present invention is not restricted to following examples, and other improvement by those of ordinary skill in the art's routine techniques means are also within thought range of the present invention.
Please refer to Fig. 1 Fig. 2 and Fig. 3, Fig. 1 is embodiment of the present invention grid coupling efficiency test structure the first test structure schematic diagram, Fig. 2 is embodiment of the present invention grid coupling efficiency test structure the second test structure schematic diagram, and Fig. 3 is the flow chart of embodiment of the present invention grid coupling efficiency method of testing.The grid coupling efficiency test structure of the present embodiment comprises:
The first test structure 1 as shown in Figure 1, described the first test structure 1 comprises the control gate 13 on the first floating boom 11 and the first floating boom 11 being formed on substrate 10.Between described the first floating boom 11 and control gate 13, be also formed with dielectric layer 12, in substrate 10, between the first floating boom 11, also form active drain terminal 14.
Described the first test structure 1 can be identical with the forming process of existing memory cell areas and structure, therefore the explanation of omitting manufacture method at this.
The second test structure 2 as shown in Figure 2, described the second test structure 2 comprises the second floating boom 21 being formed on substrate 20.In substrate 20, between the second floating boom 21, also form active drain terminal 22.
Described the first floating boom 11 is identical with the second floating boom 21 structures.
The forming process of described the second test structure 2 is summarized as follows:
The first step is carried out the deposition of floating gate polysilicon on substrate, is included in memory cell areas and external zones.Second step, carries out the etching of floating gate polysilicon, and floating boom is etched into the bar shaped floating gate structure identical with memory cell size, also identical with the first floating boom 11 of the first test structure 1.The 3rd step, carries out floating boom-control gate cvd dielectric layer.The 4th step, control gate polysilicon deposition.The 5th step, the etching of control gate polysilicon, this etching covers memory cell areas and external zones completely, and control gate figure after this etching is existed completely.The 6th step, external zones polysilicon gate etching: now memory cell areas is covered by mask, external zones is used to form test structure and can be opened, and control gate figure is eaten out completely, and is parked in above floating boom-control gate dielectric layer.The 7th step, abutment wall etching, completes the etching of floating boom-control gate dielectric layer, is parked in above floating gate polysilicon, thereby obtains the second test structure 2 as shown in Figure 2.
In described the first test structure 1 and the second test structure 2, the constituent material of stating substrate 10,20 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.As example, in the present embodiment, described substrate 10,20 selects single crystal silicon material to form.In described substrate 10,20, can also be formed with buried regions (not shown) etc.
The method of utilizing grid coupling efficiency test structure as above to test is provided below.Please refer to Fig. 3, the method comprises:
Step S101: record the mutual conductance of the first test structure and the mutual conductance of the second test structure.Concrete, mutual conductance adopts following form to record: drain terminal, control gate and substrate at the first test structure apply respectively voltage, source ground connection, test source-leakage current curve, the voltage while reading a certain electric current on grid, threshold voltage while being this electric current.It should be noted that, the threshold voltage in the present invention refers to the voltage under the state of not opening.Preferably, described drain terminal voltage 0.1～0.5V, control-grid voltage 0～9V, underlayer voltage-6～-8V.Described current range is 1E-12A～1E-6A, in the present embodiment, reads the first electric current and is 10 and receive peace and 1 voltage of receiving on ampere-hour grid.Mutual conductance=(threshold voltage under threshold voltage-the first test structure the second electric current under first test structure the first electric current)/(first electric current-the second electric current) of described the first test structure.
The mutual conductance of the second test structure adopts similar method to record.Concrete, apply respectively voltage at drain terminal, floating boom and the substrate of the second test structure, source ground connection, test source-leakage current curve, the voltage while reading a certain electric current on grid, threshold voltage while being this electric current.Preferably, described drain terminal voltage 0.1～0.5V, control-grid voltage 0～9V, underlayer voltage-6～-8V.Described current range is 1E-12A～1E-6A, in the present embodiment, reads the first electric current and is 10 and receive peace and 1 voltage of receiving on ampere-hour grid.Mutual conductance=(threshold voltage under threshold voltage-the second test structure the 4th electric current under the second test structure the 3rd electric current)/(three electric current-, tetra-electric currents) of the second test structure.
Then, carry out step S102, according to the mutual conductance of mutual conductance/the first test structure of formula grid coupling efficiency=the second test structure, by each mutual conductance substitution recording in step S101, can obtain grid coupling efficiency.
For example, according to above-mentioned grid coupling efficiency computing formula, in actual production process, under current range 1NA～10NA, can be regarded as to such an extent that grid coupling efficiency is 0.611,1sigma=0.118, under current range 1NA～100NA, can be regarded as to such an extent that grid coupling efficiency is 0.611,1sigma=0.098, therefore the degree of convergence is also fine.
By section and Electronic Speculum tem analysis, record relative dimensions, according to existing theoretical analysis method, calculate to such an extent that theoretical grid coupling efficiency is 0.614.Very nearly the same with the data that record according to the inventive method.And method of the present invention not only can obtain enough accurate data, and easy and simple to handle, efficient, and in WAT test, cost is also low, therefore has good practical value.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (9)
1. a grid coupling efficiency test structure, comprising:
The first test structure, described the first test structure comprises the control gate on the first floating boom and the first floating boom being formed on substrate;
The second test structure, described the second test structure comprises the second floating boom being formed on substrate;
Described the first floating boom is identical with the second floating gate structure, forms active drain terminal in described substrate.
2. grid coupling efficiency test structure as claimed in claim 1, is characterized in that, described the first test structure is identical with memory cell structure.
3. the method for utilizing grid coupling efficiency test structure as claimed in claim 1 or 2 to test, comprise: record the mutual conductance of the first test structure and the mutual conductance of the second test structure, the mutual conductance of mutual conductance/the first test structure of grid coupling efficiency=the second test structure.
4. the method for testing of grid coupling efficiency as claimed in claim 3, it is characterized in that mutual conductance=(threshold voltage under threshold voltage-the first test structure the second electric current under first test structure the first electric current)/(first electric current-the second electric current) of described the first test structure;
Mutual conductance=(threshold voltage under threshold voltage-the second test structure the 4th electric current under the second test structure the 3rd electric current)/(three electric current-, tetra-electric currents) of the second test structure.
5. the method for testing of grid coupling efficiency as claimed in claim 4, is characterized in that, the threshold voltage method of testing of described the first test structure comprises:
Apply respectively voltage at drain terminal, control gate and substrate, source ground connection, test source-leakage current curve, the voltage while reading a certain electric current on grid, threshold voltage while being this electric current.
6. the method for testing of grid coupling efficiency as claimed in claim 5, is characterized in that, described drain terminal voltage 0.1～0.5V, control-grid voltage 0～9V, underlayer voltage-6～-8V.
7. the method for testing of grid coupling efficiency as claimed in claim 4, is characterized in that, the threshold voltage method of testing of described the second test structure comprises:
Apply respectively voltage at drain terminal, floating boom and substrate, source ground connection, test source-leakage current curve, the voltage while reading a certain electric current on grid, threshold voltage while being this electric current.
8. the method for testing of grid coupling efficiency as claimed in claim 7, is characterized in that, described drain terminal voltage 0.1～0.5V, control-grid voltage 0～9V, underlayer voltage-6～-8V.
9. the method for testing of the grid coupling efficiency as described in claim 5 or 7, is characterized in that, described current range is 1E-12A～1E-6A.
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Cited By (3)
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| CN104916562A (en) * | 2015-04-17 | 2015-09-16 | 上海华虹宏力半导体制造有限公司 | Flash memory cell coupling ratio monitoring method |
| CN106092517A (en) * | 2016-06-01 | 2016-11-09 | 上海大学 | The test device of extra small GRIN fiber lens coupling efficiency and method of testing |
| CN109461669A (en) * | 2018-10-18 | 2019-03-12 | 上海华力微电子有限公司 | A kind of device and preparation method thereof detecting flush memory device coupling efficiency |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104916562A (en) * | 2015-04-17 | 2015-09-16 | 上海华虹宏力半导体制造有限公司 | Flash memory cell coupling ratio monitoring method |
| CN104916562B (en) * | 2015-04-17 | 2018-01-26 | 上海华虹宏力半导体制造有限公司 | Flash cell coupling ratio monitoring method |
| CN106092517A (en) * | 2016-06-01 | 2016-11-09 | 上海大学 | The test device of extra small GRIN fiber lens coupling efficiency and method of testing |
| CN109461669A (en) * | 2018-10-18 | 2019-03-12 | 上海华力微电子有限公司 | A kind of device and preparation method thereof detecting flush memory device coupling efficiency |
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