CN101783179A - Erasing method for improving durability of grid-split flash memory - Google Patents
Erasing method for improving durability of grid-split flash memory Download PDFInfo
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- CN101783179A CN101783179A CN201010102344A CN201010102344A CN101783179A CN 101783179 A CN101783179 A CN 101783179A CN 201010102344 A CN201010102344 A CN 201010102344A CN 201010102344 A CN201010102344 A CN 201010102344A CN 101783179 A CN101783179 A CN 101783179A
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Abstract
The invention provides an erasing method for improving the durability of a grid-split flash memory, which comprises the following steps: adding a nonzero voltage VBL into word lines of source regions and drain regions; adding voltage VWL on the word lines, wherein VWL=V0+0.6*VBL; and carrying out idle connection on a first control grid and a second control grid, wherein V0 refers to the erasing voltage of the flash memory when the source regions and the drain regions are grounded. On the premise of ensuring the erasing function of the flash memory, the erasing method provided by the invention reduces the defect of tunneling oxide in erasing process, thereby improving the durability of the flash memory.
Description
Technical field
The present invention relates to the method for deleting of the data-carrier store of semiconductor applications, relate in particular to a kind of method for deleting of gate-division type flash memory of shared word line.
Background technology
Flash memory is convenient with it, the storage density height, and advantages such as good reliability become the focus of studying in the non-volatility memorizer.Since first flash memory products comes out from the 1980s, development and the demand of each electronic product along with technology to storing, flash memory is widely used in mobile phone, notebook, palm PC and USB flash disk etc. move and communication apparatus in, flash memory is a kind of non-volatility storer, its operation principles is to control the switch of gate pole passage to reach the purpose of storage data by the critical voltage that changes transistor or storage unit, make the data that are stored in the storer can be, and flash memory be a kind of special construction of electric erasable and programmable ROM (read-only memory) because of power interruption does not disappear.Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
Yet existing flash memory utilizes reduction of device size to improve storage density in the high storage density of marching toward more usually, gate-division type flash memory since its special structure compare the stacking gate flash memory and all embody its particular performances advantage in programming with when wiping.
How improving the durability of gate-division type flash memory in various programming processes is the problem that industry is comparatively paid close attention to.
Summary of the invention
The present invention proposes a kind of (Erase) method of wiping that improves the gate-division type flash memory durability, and it can be under the constant prerequisite of the erase feature that keeps chip, effectively the durability of gate-division type flash memory.
To achieve these goals, the present invention proposes a kind of method for deleting that improves the gate-division type flash memory durability, described flash memory comprises: Semiconductor substrate, have the source region and the drain region that are provided with at interval on it, and described source region and drain region are respectively arranged with bit line; Word line is arranged between described source region and the drain region; First storage bit unit, between described word line and described source region, described first storage bit unit has first control gate and first floating boom that is provided with at interval; Second storage bit unit, between described word line and described drain region,, described second storage bit unit has second control gate and second floating boom that is provided with at interval; Separate by tunnel oxide between wherein said two storage bit unit and the described word line and between described word line and the described Semiconductor substrate, it is characterized in that described method for deleting comprises: the word line in described source region, drain region adds non-vanishing voltage V
BL, making alive V on described word line
WL=V
0+ 0.6*V
BL, described first control gate, the second control gate sky connect, wherein V
0Erasing voltage for flash memory when source region, the drain region ground connection.
Optionally, described source region, drain region to be applied voltage be 1V, described word line is applied voltage is 11.6V.
Optionally, described two control gates are polysilicon control grid, and described two floating booms are multi-crystal silicon floating bar, and described word line is that polysilicon is selected grid.
Optionally, described tunnel oxide is a silicon oxide layer.
A kind of useful technique effect that improves the method for deleting of gate-division type flash memory durability of the present invention is: method for deleting provided by the invention, by reducing the voltage that on word line, is applied, reduce the voltage that the oxide layer of flash chip is born largely, slow down oxide layer because high energy electron injects the lattice imperfection that is caused, and then improve the durability of flash chip integral body.
Description of drawings
Fig. 1 is the cross-sectional view of gate-division type flash memory among the present invention.
Fig. 2 is to the alive synoptic diagram of the each several part of flash memory in the common method for deleting.
Fig. 3 is to the alive synoptic diagram of the each several part of flash memory in the method for deleting of preferred embodiment of the present invention.
Fig. 4 is for adding the relation curve of the voltage that bear each position in different voltage and the flash memory on the storage bit unit.
The numerical curve of Fig. 5 interior electric current of different pressurized conditions lower channel for flash memory is in.
Fig. 6 is the numerical curve of voltage between word line under flash memory the is in different pressurized conditions and the raceway groove.
Fig. 7 is the permanance checking curve of flash memory under the method for deleting of first condition and preferred embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing a kind of method for deleting that improves the gate-division type flash memory durability of the present invention is further elaborated.
At first, please refer to Fig. 1, Fig. 1 is the cross-sectional view of gate-division type flash memory among the present invention.
As can be seen from Figure 1, gate-division type flash memory comprises: Semiconductor substrate 100 has the source region 200 and the drain region 300 that are provided with at interval on it; Word line 400 is arranged between described source region 200 and the drain region 300, and described source region 200 and drain region 300 are respectively arranged with bit line (figure does not show); First storage bit unit 500, between described word line 400 and described source region 200, described first storage bit unit 500 has first control gate 510 and first floating boom 520 that is provided with at interval; Second storage bit unit 600, between described word line 400 and described drain region 300, described second storage bit unit 600 has second control gate 610 and second floating boom 620 that is provided with at interval, separate described two control gates 510,610 by tunnel oxide 700 between wherein said two storage bit unit 500,600 and the described word line 400 and be polysilicon control grid, described two floating booms 520,620 are multi-crystal silicon floating bar, described word line 400 is selected grid for polysilicon, and described tunnel oxide 700 is a silicon oxide layer.
When flash memory being wiped when handling, between word line 400 and two storage bit unit 500,600, form pressure reduction, thereby in flash memory, form raceway groove, the electron charge on two floating booms 520,620 discharges by this raceway groove, thus the wiping of realization flash memory.
Fig. 2 is to the alive synoptic diagram of the each several part of flash memory in the common method for deleting.
As shown in Figure 2, common method for deleting for example is making alive V on word line 400
WL=V
0, V wherein
0Numerical value be the erasing voltage of flash memory, for example be 11V; Source region 200, drain region 300 skies connect, i.e. V
BL1=0V, V
BL2=0V; First control gate 510, second control gate, 610 skies connect, i.e. V
CG1=0V, V
CG2=0V.
In this case, the voltage that tunnel oxide 700 bears is the voltage at raceway groove two ends,
V
oxide＝V
WL-V
BL1＝11V-0V＝11V (1)
Certainly, the V in the calculating formula (1)
BL1Also can be V
BL2
In the voltage that tunnel oxide 700 bears, electron charge may rest in the tunnel oxide 700, thereby forms the defective of tunnel oxide 700, causes tunnel oxide 700 quick agings, and then influences the permanance of whole flash memory.This effect is that the voltage swing that bears with tunnel oxide 700 is proportional.
Fig. 3 is to the alive synoptic diagram of the each several part of flash memory in the method for deleting of preferred embodiment of the present invention.
As shown in Figure 3, the method for deleting among the present invention be in the source region 200, drain region 300 adds non-vanishing voltage V
BL, V
BL1=V
BL2=V
BL≠ 0, V for example wherein
BLBe 1V; Making alive V on word line 400
WL=V
0+ 0.6*V
BL, wherein, in order to compare V in the present embodiment with the making alive mode shown in Fig. 2
WL=11V+0.6*1V=11.6V; First control gate 510, second control gate, 610 skies connect, i.e. V
CG1=0V, V
CG2=0V.
In this case, the voltage that tunnel oxide 700 bears is the voltage at raceway groove two ends,
V
oxide＝V
WL-V
BL1＝11.6V-1V＝10.6V (2)
Certainly, the V in the calculating formula (2)
BL1Also can be V
BL2
Compare with the common method for deleting among Fig. 2, the voltage that tunnel oxide 700 in the present embodiment bears is less than the voltage that is born in the common method for deleting, so the defective that electron charge is caused in tunnel oxide 700 also is less than the defective that is caused in the common method for deleting, therefore, present embodiment can slow down the aging of tunnel oxide 700 in the flash memory, and then improves the permanance of flash memory.
Below will provide the experimental data of inventor in design process, and can guarantee to wipe effect with the method for deleting in explanation the foregoing description.
In order to verify whether the voltage that is increased on the word line 400 must be identical with the voltage that source region 200, drain region 300 are increased, the inventor is in the experimental phase, in the source region 200, drain region 300 making alive V respectively
BL=1V, making alive V on word line 400
0+ 1V=12V, and monitor when flash memory is realized wiping the voltage difference V between word line 400 and the raceway groove
EraseChecking through above-mentioned experiment, invent the voltage that artificial word line 400 increased must be not identical with the voltage that source region 200, drain region 300 are increased, and released the relation of the voltage that voltage that word line 400 increased and source region 200, drain region 300 increased.Below will provide concrete experimental technique.
Figure 4 shows that on source that software simulation obtains, the drain region add the relation curve of the voltage that bear each position in different voltage and the flash memory.
Among Fig. 4, the residing environment of flash memory is: in the source region 200, drain region 300 adds non-vanishing voltage V
BL=V
BL1=V
BL2=V
BL=1V/2V/3V...; Making alive V on word line 400
WL=V
0+ V
BL=12V/13V/14V...; First control gate 510, second control gate, 610 skies connect, i.e. V
CG1=0V, V
CG2=0V.
Horizontal ordinate among Fig. 4 is source region 200,300 making alives in drain region, and ordinate is the voltage value that software simulation obtains.Wherein dotted line is by along with alive change on source region 200, the drain region 300, and word line 400 that simulates and the voltage value between the raceway groove; Solid line is by along with alive change on source region 200, the drain region 300, and the voltage value between word line 400 that simulates and the floating boom 520,620.As can be seen from Figure 4, along with alive change on source region 200, the drain region 300, voltage between word line 400 and the raceway groove is maintained fixed numerical value, and the voltage value between word line 400 and the floating boom 520,620 increases along with the alive increase of institute on source region 200, the drain region 300.
When Fig. 4 had illustrated on increasing source region 200, drain region 300 and word line 400 institute's making alive, the ability of wiping of flash memory can be enhanced.
Flash memory shown in Figure 5 is in the numerical curve of different pressurized conditions lower channel electric currents; Flash memory shown in Figure 6 is under the different pressurized conditions numerical curve of voltage between the word line and raceway groove.
Get a plurality of flash memories, respectively flash memory is placed under first condition and the second condition, measure the electric current in the raceway groove, and when flash memory is wiped free of, measure the voltage value V between word line 400 and the raceway groove
Erase
First condition (common method for deleting) is: source region 200, drain region 300 sky respectively connect, i.e. V
BL1=V
BL2=0V; Making alive V on the word line 400
0=11V; First control gate 510, second control gate, 610 skies connect, i.e. V
CG1=0V, V
CG2=0V.In this second condition (method for deleting that needs checking), on source region 200, drain region 300, add non-vanishing voltage V
BL1=V
BL2, for example be 1V; Making alive V on word line 400
WL=V
0+ V
BL=12V; First control gate 510, second control gate, 610 skies connect, i.e. V
CG1=0V, V
CG2=0V.
Among Fig. 5, dotted line is in the first condition (common method for deleting), each flash memory when the erasing flash memory data, the electric current in the raceway groove; Solid line is in the second condition (need checking method for deleting), each flash memory when the erasing flash memory data, the electric current in the raceway groove.
Among Fig. 6, dotted line is in the first condition (common method for deleting), each flash memory when obliterated data, the voltage value between word line 400 and the raceway groove; Solid line is in the second condition (method for deleting that needs checking), the voltage value between word line 400 and the raceway groove.
From the curve of Fig. 6 as can be seen, when each flash memory is performed erase operation, the voltage value V in the flash memory under first condition and the second condition between word line 400 and the raceway groove
EraseDifference is approximately 0.6V, and wherein the word line 400 of second condition is than the big 1V of the word line in the first condition 400 voltage value that applies.For example in the sampling of second flash memory, when flash memory was wiped, the voltage value between word line 400 and the raceway groove was 9.6V in the first condition, and when flash memory was wiped, the voltage value between word line 400 and the raceway groove was 10.2V in the second condition.
When 300 making alives in word line 400, source region 200, the drain region of flash memory increase 1V respectively, when erasing flash memory, voltage between word line 400 and the raceway groove only increases 0.6V, can reach a conclusion: source region 200,300 making alives in drain region are increased 1V, 400 making alives of word line increase 0.6V simultaneously, can guarantee the ability of wiping of flash memory.Simultaneously,, thereby reduce the magnitude of voltage that bears of tunnel oxide 700, can improve the permanance of flash memory because the voltage difference between word line 400 and the raceway groove is reduced to V0-1V+0.6V=V0-0.4V.
Further, the voltage that source region 200, drain region 300 are increased is not limited only to 1V, when the voltage value of its increase is V
BLThe time, then the voltage that increased of word line 400 is 0.6*V
BL, so, both can guarantee the ability of wiping of flash memory, more can improve the permanance of flash memory.
Figure 7 shows that the permanance checking curve of flash memory under the method for deleting of first condition and preferred embodiment of the present invention.
Horizontal ordinate is the cycle index of erase operation among Fig. 7, and ordinate is the decline ratio of channel current in the flash memory.Whether the channel current when wiping stabilizes to an index judging flash memory performance.
The curve that square point was connected to form is the checking of the permanance under first condition referred to above curve; The curve that Diamond spot was connected to form is that flash memory is in the permanance checking curve in the method for deleting of preferred embodiment of the present invention.In the method for deleting of preferred embodiment of the present invention, on source region 200, drain region 300, add non-vanishing voltage V
BL1=V
BL2, for example be 1V; Making alive V on word line 400
WL=V
0+ 0.6*V
BL, for example be 11.6V; First control gate 510, second control gate, 610 skies connect, i.e. V
CG1=0V, V
CG2=0V.
From Fig. 7, can clearly find out, through erase operation repeatedly the time, the very fast decline of internal memory performance under the first condition, and the decline of the internal memory performance under the method for deleting of preferred embodiment of the present invention comparatively relaxes, promptly, the method for deleting that preferred embodiment of the present invention provided can guarantee to wipe under the prerequisite of ability the permanance of raising gate-division type flash memory than classic method.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have in the technical field of the present invention and know the knowledgeable usually, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (4)
1. method for deleting that improves the gate-division type flash memory durability, described flash memory comprises: Semiconductor substrate, have the source region and the drain region that are provided with at interval on it, described source region and drain region are respectively arranged with bit line; Word line is arranged between described source region and the drain region; First storage bit unit, between described word line and described source region, described first storage bit unit has first control gate and first floating boom that is provided with at interval; Second storage bit unit, between described word line and described drain region, described second storage bit unit has second control gate and second floating boom that is provided with at interval; Separate by tunnel oxide between wherein said two storage bit unit and the described word line and between described word line and the described Semiconductor substrate; It is characterized in that described method for deleting comprises:
Add non-vanishing voltage V in described source region, drain region
BLMaking alive V on described word line
WL=V
0+ 0.6*V
BLDescribed first control gate, the second control gate sky connect, wherein V
0Erasing voltage for flash memory when source region, the drain region ground connection.
2. the method for deleting of raising gate-division type flash memory durability according to claim 1 is characterized in that, the voltage that the voltage that described source region, drain region are applied is 1V, apply described word line is 11.6V.
3. the method for deleting of raising gate-division type flash memory durability according to claim 1 is characterized in that described two control gates are polysilicon control grid, and described two floating booms are multi-crystal silicon floating bar, and described word line is that polysilicon is selected grid.
4. the method for deleting of raising gate-division type flash memory durability according to claim 1 is characterized in that described tunnel oxide is a silicon oxide layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366810A (en) * | 2013-07-26 | 2013-10-23 | 上海宏力半导体制造有限公司 | EEPROM memory array |
| CN107331419A (en) * | 2017-07-05 | 2017-11-07 | 上海华虹宏力半导体制造有限公司 | The method for screening out initial failure in flash cell |
| CN114283867A (en) * | 2021-12-24 | 2022-04-05 | 北京大学 | Method for improving durability of memory based on metal tunneling junction |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6248633B1 (en) * | 1999-10-25 | 2001-06-19 | Halo Lsi Design & Device Technology, Inc. | Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory |
| JP3606231B2 (en) * | 2001-05-31 | 2005-01-05 | セイコーエプソン株式会社 | Nonvolatile semiconductor memory device |
| CN100372101C (en) * | 2005-04-25 | 2008-02-27 | 联华电子股份有限公司 | Non-volatile memory unit and its production |
| CN101465161A (en) * | 2008-12-30 | 2009-06-24 | 上海宏力半导体制造有限公司 | Gate-division type flash memory sharing word line |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366810A (en) * | 2013-07-26 | 2013-10-23 | 上海宏力半导体制造有限公司 | EEPROM memory array |
| CN103366810B (en) * | 2013-07-26 | 2017-07-28 | 上海华虹宏力半导体制造有限公司 | EEPROM memory array |
| CN107331419A (en) * | 2017-07-05 | 2017-11-07 | 上海华虹宏力半导体制造有限公司 | The method for screening out initial failure in flash cell |
| CN114283867A (en) * | 2021-12-24 | 2022-04-05 | 北京大学 | Method for improving durability of memory based on metal tunneling junction |
| CN114283867B (en) * | 2021-12-24 | 2024-05-24 | 北京大学 | Method for improving durability of memory based on metal tunneling junction |
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| CN101783179B (en) | 2012-10-31 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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