CN104934064A - Block erasing method for NAND type flash memory - Google Patents
Block erasing method for NAND type flash memory Download PDFInfo
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- CN104934064A CN104934064A CN201510395047.7A CN201510395047A CN104934064A CN 104934064 A CN104934064 A CN 104934064A CN 201510395047 A CN201510395047 A CN 201510395047A CN 104934064 A CN104934064 A CN 104934064A
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Abstract
The invention discloses a block erasing method for a NAND type flash memory. The method comprises erasing operation, erasing examination operation, soft programming operation and soft programming examination operation. By means of soft programming operation, all memory cells of a block of the NAND type flash memory are programmed together, and time for programming the memory cells can be saved greatly. By means of soft programming examination operation, all the memory cells of the block of the NAND type flash memory are examined together, the operating mode of soft programming examination operation is identical with that of erasing examination operation, and soft programming examination operation is different from erasing examination operation only in bit line discharging time or examination judgment voltage. By the adoption of the method, the threshold voltage distribution of the memory units of the block of the NAND type flash memory can be made compact, sound initial threshold voltage distribution is provided for page programming operation, so that programming time is saved, the channel bootstrap efficiency of page programming operation is improved, and programming disturbance is reduced.
Description
Technical field
The present invention relates to NAND flash memories field, especially a kind of block method for deleting of NAND flash memories.
Background technology
Flash memories is a kind of nonvolatile memory, the feature that after having power down, information remains unchanged.Flash memories is divided into NOR type flash memories and NAND flash memories according to storage unit structure in an array.NOR type flash memories is forming array in parallel, has the advantage that speed of random access is fast, is mainly used in storage code; And NAND flash memories is the mode forming array of connecting, there is the advantage that per bit area is little, for storing a large amount of data.The block structured circuit diagram of NAND flash memories as shown in Figure 1, comprise n bar wordline (WL1, WL2 ..., WLn), m bit lines (BL1, BL2 ..., BLm), source select lines (SSL), a drain terminal select lines (DSL) and a source line (SL), the storage unit part that dotted line frame 11 identifies out is called a memory cell string.
The basic operation of NAND flash memories comprises programming operation, erase operation, read operation.The erase operation of NAND flash memories does based on block, and Fig. 2 is the process flow diagram of the block method for deleting of the typical NAND flash memories of prior art, and as shown in Figure 2, the block method for deleting of the typical NAND flash memories of prior art comprises:
Step one (101): erase operation: erase operation is done to all storage unit in the block of NAND flash memories, concrete grammar is: the n bar wordline shown in Fig. 1 is applied to 0V voltage or negative voltage, substrate applied to the high voltage of about 20V, this high voltage can be transferred on all bit lines and source line by PN junction forward conduction, allows source select lines and drain terminal select lines be in suspended state.
Step 2 (102), whether erasing verification operation, check the voltage of the bit line of all storage unit after precharge is discharged again lower than decision content, concrete method: first to carry out precharge to the m bit lines shown in Fig. 1; Then pairs of bit line is discharged, the discharge capability of pairs of bit line depends on that storage unit that threshold voltage is the highest, then the bit-line voltage after electric discharge and judgement voltage are carried out, when all bit-line voltages are all less than judgement voltage, represent the success of erasing verification operation, operation terminates, otherwise, just turn back to step 2 to continue to do erase operation, until the success of erasing verification operation.
Because the initial threshold voltage of each storage unit before erase operation is different, and electron tunneling in the floating boom of each storage unit is different to the speed of raceway groove, and erase operation operates together the storage unit in whole piece, so the slow-footed storage unit of tunnelling determines the time of whole erase operation, this just causes the fast storage unit of part erasing speed can be wiped free of excessively dark, after causing erasing verification succeeds, the threshold voltage distribution of the storage unit in block is very wide, this can cause the channel bootstrap efficiency of page programming operation to reduce, programming time increases, programming interference increases.
Summary of the invention
The object of this invention is to provide a kind of block method for deleting of NAND flash memories, the threshold voltage distribution after the erase operation of NAND flash memories can be reduced, reduce the programming interference of storage unit, improve the performance of NAND flash memories programming operation.
Technical scheme provided by the invention is as follows:
A block method for deleting for NAND flash memories, comprises the following steps:
Step one: erase operation: 0V voltage or negative voltage are applied to all wordline in the block of NAND flash memories, the first positive voltage is applied to substrate;
Step 2: erasing verification operation: the first voltage is applied to all wordline in the block of NAND flash memories, all bit lines are charged to the first pre-charge voltage in advance; Then all bit lines are carried out to the electric discharge of the very first time, then the bit-line voltage and first after electric discharge is judged that voltage compares, if the voltage of all bit lines all judges voltage lower than described first, then enter next step; Otherwise, then return step one and re-start erase operation;
Step 3: soft programming operation: apply the second positive voltage to all wordline in the block of NAND flash memories, applies 0V voltage to all bit lines;
Step 4: soft programming verification operation: the second voltage is applied to all wordline in the block of NAND flash memories, all bit lines are charged to the second pre-charge voltage in advance; Then all bit lines are carried out to the electric discharge of the second time, then the bit-line voltage and second after electric discharge is judged that voltage compares, if the voltage that at least there is a bit lines judges voltage higher than described second, then operate end, otherwise, then return step 3 and re-start soft programming operation.
The block method for deleting of a kind of NAND flash memories of the present invention, when doing soft programming operation, the storage unit that initial threshold voltage is lower, the storage unit that the ascensional range of its threshold voltage is higher than initial threshold voltage is higher, can make in erase operation, be wiped free of dark storage unit after soft programming operation, obtain larger threshold voltage amount of increase, and the more shallow storage unit be wiped free of obtains less threshold value amount of increase, thus tighten up the threshold voltage distribution of the storage unit of the block of NAND flash memories.
Further preferably, the first positive voltage of the present invention is 20V.
Further preferably, the scope of the first voltage of the present invention is-1V to 0V.
Further preferably, the scope of the first pre-charge voltage of the present invention is 1v to 1.2v.
Further preferably, the scope of the very first time of the present invention is 1us to 10us.
Further preferably, of the present invention first judges that voltage is as 0.8V.
Further preferably, the scope of the second positive voltage of the present invention is 12V to 16V.
Further preferably, the first pre-charge voltage of the present invention is equal with described second pre-charge voltage.
Further preferably, the second voltage of the present invention is equal with described first voltage.
Further preferably, of the present invention second judges that voltage is greater than described first and judges voltage.
Further preferably, the value of the second time of the present invention is greater than the value of the described very first time.
Technique effect of the present invention is:
The present invention, after erase operation and erasing verification operation, introduces a kind of simple soft programming operation and soft programming verification operation.Soft programming operation of the present invention is programmed together to all storage unit of the block of NAND flash memories, instead of programme page by page as page programming operation, greatly can save the programming time of storage unit.Soft programming verification operation of the present invention is also do together all storage unit of the block of NAND flash memories, and its mode of operation is identical with the mode of erasing verification operation, and the time difference or the erasing that are bit line discharges verify the judgement voltage difference judged.The present invention introduces soft programming operation and soft programming verification operation, first without the need to increasing new hardware circuit, can not increase the chip area of NAND flash memories; Secondly the threshold voltage distribution of the storage unit of the block of NAND flash memories can be tightened up significantly, for the operation of page programming instruction provides good initial threshold voltage distribution, thus saving programming time, and increase the channel bootstrap efficiency of page programming operation, reduce programming interference.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail:
Fig. 1 is the block structured circuit diagram of the typical NAND flash memories of prior art;
Fig. 2 is the process flow diagram of the block method for deleting of the typical NAND flash memories of prior art;
Fig. 3 is the process flow diagram of the block method for deleting of NAND flash memories provided by the invention;
Fig. 4 is the comparison diagram that threshold voltage that the threshold voltage distribution that obtains of the block method for deleting of typical NAND flash memories and the block method for deleting of NAND flash memories provided by the invention obtain distributes.
Embodiment
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 3 is the process flow diagram of the block method for deleting of a kind of NAND flash memories provided by the invention.Next describe the block method for deleting of a kind of NAND flash memories of the present invention for the block structure of the NAND flash memories shown in Fig. 1, as shown in Figure 3, the block method for deleting of NAND flash memories of the present invention comprises the following steps:
Step one (201): erase operation, erase operation is done to all storage unit in the block of NAND flash memories, concrete method is: to applying 0V voltage or negative voltage to the n bar wordline in the block of NAND flash memories, applying the first positive voltage to substrate shown in Fig. 1, this first positive voltage is preferably 20V voltage, this first positive voltage can be transferred on all bit lines (BL) and source line (SL) by substrate PN junction forward conduction, allows source select lines (SSL) and drain terminal select lines (DSL) be in suspended state.The time of erase operation is generally hundreds of microsecond.
Step 2 (202): erasing verification operation, the bit-line voltage of all bit lines after precharge and electric discharge is checked whether to judge voltage lower than first, concrete method is: first apply the first voltage to the n bar wordline in the block of the NAND flash memories shown in Fig. 1, m bit lines is pre-charged to the first pre-charge voltage, first voltage range preferably from-1V to 0V, the first pre-charge voltage range preferably from 1v to 1.2v.Because bit line has larger stray capacitance, the bit-line voltage therefore after precharge remains unchanged substantially.Then, n bar wordline is applied to 0V voltage or negative voltage, applies 0V voltage to source line, and metal-oxide-semiconductor that voltage makes it be connected is applied as transfer tube to source select lines and drain terminal select lines, now the electric current meeting pairs of bit line of storage unit carries out the electric discharge of the very first time, and the discharge capability of pairs of bit line depends on that storage unit that threshold voltage is the highest.Then the bit-line voltage and first after electric discharge is judged that voltage compares, first judges that voltage is preferably 0.8V.When all bit-line voltages are all less than the first judgement voltage, represent the success of erasing verification operation, can next step be entered; Otherwise, then return step one and re-start erase operation, until functional check successful operation.
Step 3 (203): soft programming operation, in block to NAND flash memories, all storage unit do soft programming operation, concrete method is: the n bar wordline in the block of the NAND flash memories shown in Fig. 1 is applied to the second positive voltage, applies 0V voltage to m bit lines, described second positive voltage range preferably from 12V to 16V.Within certain soft programming time, storage unit its threshold voltage delta after soft programming operation that initial threshold voltage is lower is larger, otherwise threshold voltage delta is less.At this, those of ordinary skill in the art can understand, when carrying out soft programming operation, usually also needs the metal-oxide-semiconductor conducting that the voltage applying about 4v to drain terminal select lines makes it connect, and applies 0V voltage to source select lines.
Step 4 (204): soft programming verification operation, all bit lines are after precharge and electric discharge, the voltage whether inspection at least exists a bit lines judges voltage higher than second, concrete method of operating is: first apply the second voltage to the n bar wordline in the block of the NAND flash memories shown in Fig. 1, m bit lines is pre-charged to the second pre-charge voltage, preferably, described second voltage is equal with described first voltage, and the second pre-charge voltage is equal with described first pre-charge voltage.Then, 0V voltage or negative voltage are applied to n bar wordline, apply metal-oxide-semiconductor that voltage makes it be connected as transfer tube to source select lines and drain terminal select lines, and apply 0V voltage to source line (SL), now the electric current pairs of bit line of storage unit carries out the electric discharge of the second time.Preferably, described second can be made to judge, and voltage is greater than described first and judges voltage, or makes the value of the second time be greater than the value of the described very first time.Then the bit-line voltage and second after electric discharge is judged that voltage compares, if the voltage that at least there is a bit lines judges voltage higher than described second, then represent the success of soft programming verification operation, now whole piece of erase operation terminates, otherwise, then return step 3 and re-start soft programming operation until the success of soft programming verification operation.
Fig. 4 is the comparison diagram that threshold voltage that the threshold voltage distribution that obtains of the block method for deleting of typical NAND flash memories and the block method for deleting of NAND flash memories provided by the invention obtain distributes, as shown in Figure 4, transverse axis is threshold voltage, and the longitudinal axis is distribution probability.Curve 1 is the threshold voltage distribution after the success of erasing verification operation, and curve 2 is the threshold voltage distributions after the success of soft programming verification operation.The low side threshold voltage of curve 2 is obviously a lot of than the height of curve 1, simultaneously slightly higher only than curve 1 of the high-end threshold voltage of curve 2, and the threshold voltage distribution of such curve 2 is tightened up a lot than curve 1.Illustrate that the threshold voltage distribution adopting of the present invention piece of method for deleting to obtain obviously diminishes than common piece of method for deleting.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. a block method for deleting for NAND flash memories, comprises the following steps:
Step one: erase operation: 0V voltage or negative voltage are applied to all wordline in the block of NAND flash memories, the first positive voltage is applied to substrate;
Step 2: erasing verification operation: the first voltage is applied to all wordline in the block of NAND flash memories, all bit lines are charged to the first pre-charge voltage in advance; Then all bit lines are carried out to the electric discharge of the very first time, then the bit-line voltage and first after electric discharge is judged that voltage compares, if the voltage of all bit lines all judges voltage lower than described first, then enter next step; Otherwise, then return step one and re-start erase operation;
Step 3: soft programming operation: apply the second positive voltage to all wordline in the block of NAND flash memories, applies 0V voltage to all bit lines;
Step 4: soft programming verification operation: the second voltage is applied to all wordline in the block of NAND flash memories, all bit lines are charged to the second pre-charge voltage in advance; Then all bit lines are carried out to the electric discharge of the second time, then the bit-line voltage and second after electric discharge is judged that voltage compares, if the voltage that at least there is a bit lines judges voltage higher than described second, then operate end, otherwise, then return step 3 and re-start soft programming operation.
2. the block method for deleting of a kind of NAND flash memories according to claim 1, is characterized in that: described first positive voltage is 20V.
3. the block method for deleting of a kind of NAND flash memories according to claim 1, is characterized in that: the scope of described first voltage is-1V to 0V.
4. the block method for deleting of a kind of NAND flash memories according to claim 1, is characterized in that: the scope of described first pre-charge voltage is 1v to 1.2v.
5. the block method for deleting of a kind of NAND flash memories according to claim 1, it is characterized in that: the scope of the described very first time is 1us to 10us, and the value of described second time is greater than the value of the described very first time.
6. the block method for deleting of a kind of NAND flash memories according to claim 1, is characterized in that: described first judges that voltage is as 0.8V.
7. the block method for deleting of a kind of NAND flash memories according to claim 1, is characterized in that: the scope of described second positive voltage is 12V to 16V.
8. the block method for deleting of a kind of NAND flash memories according to claim 1, is characterized in that: described first pre-charge voltage is equal with described second pre-charge voltage.
9. the block method for deleting of a kind of NAND flash memories according to claim 1, is characterized in that: described second voltage is equal with described first voltage.
10. the block method for deleting of a kind of NAND flash memories according to claim 1, is characterized in that: described second judges that voltage is greater than described first and judges voltage.
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| CN201510395047.7A CN104934064A (en) | 2015-07-07 | 2015-07-07 | Block erasing method for NAND type flash memory |
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Cited By (6)
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| CN106158034A (en) * | 2016-07-06 | 2016-11-23 | 北京兆易创新科技股份有限公司 | A kind of method for deleting of memory cell |
| CN110838323A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Programming method and system of memory |
| CN110838327A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Memory erasing method and system |
| CN110838318A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Method and system for improving data reliability of memory |
| CN110838322A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Method and system for improving data reliability of memory |
| CN110888519A (en) * | 2018-08-17 | 2020-03-17 | 北京兆易创新科技股份有限公司 | Programming method and system of memory |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106158034A (en) * | 2016-07-06 | 2016-11-23 | 北京兆易创新科技股份有限公司 | A kind of method for deleting of memory cell |
| CN110838323A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Programming method and system of memory |
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| CN110838318A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Method and system for improving data reliability of memory |
| CN110838322A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Method and system for improving data reliability of memory |
| CN110888519A (en) * | 2018-08-17 | 2020-03-17 | 北京兆易创新科技股份有限公司 | Programming method and system of memory |
| CN110888519B (en) * | 2018-08-17 | 2024-02-20 | 兆易创新科技集团股份有限公司 | Method and system for programming memory |
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