CN110838327A - Memory erasing method and system - Google Patents

Memory erasing method and system Download PDF

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Publication number
CN110838327A
CN110838327A CN201810941458.5A CN201810941458A CN110838327A CN 110838327 A CN110838327 A CN 110838327A CN 201810941458 A CN201810941458 A CN 201810941458A CN 110838327 A CN110838327 A CN 110838327A
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voltage
erase
verification
memory
erasing
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贺元魁
潘荣华
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GigaDevice Semiconductor Beijing Inc
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GigaDevice Semiconductor Beijing Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/345—Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification

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Abstract

The invention discloses a method and a system for erasing a memory. The erasing method of the memory comprises the following steps: erasing timing sequence C1, applying a step erase voltage to the memory cell, the step erase voltage having a step-like rising voltage waveform including a predetermined number of voltage steps, each voltage step having a predetermined step width, and a predetermined step increase D between adjacent voltage steps‑erase(ii) a When the time sequence Y1 is verified, applying verification voltage to the memory cell, and finishing verification if verification is successful; if the verification fails, the magnitude of the erase voltage is increased again after the verification timing Y1 to perform the verification again. The erasing method and the erasing system of the memory have the advantage of improving the reliability of the memory when in use.

Description

Memory erasing method and system
Technical Field
The embodiment of the invention relates to the technical field of memories, in particular to a memory erasing method and system.
Background
The Nand flash memory is a nonvolatile memory and has the advantages of high rewriting speed, large storage capacity and the like. When the Nand flash memory is erased, verification failure occurs, and after each verification failure, the amplitude of the erasing voltage needs to be increased. In the prior art, when data is erased, a higher erasing voltage is applied to a substrate of a memory cell of a memory for the first time, and the higher erasing voltage causes a large voltage difference between a floating gate and the substrate of the memory cell, so that the reliability of the use of the memory cell is reduced.
Therefore, how to improve the reliability of the memory usage becomes a demand in the memory technology field.
Disclosure of Invention
The invention provides a method and a system for erasing a memory, which aim to solve the technical problem that the reliability of the memory is reduced during erasing.
In a first aspect, an embodiment of the present invention provides an erasing method for a memory, including the following steps: erasing timing sequence C1, applying a step erase voltage to the memory cell, the step erase voltage having a step-like rising voltage waveform including a predetermined number of voltage steps, each voltage step having a predetermined step width, and a predetermined step increase D between adjacent voltage steps-erase(ii) a When the time sequence Y1 is verified, applying verification voltage to the memory cell, and finishing verification if verification is successful; if the verification fails, the magnitude of the erase voltage is increased again after the verification timing Y1 to perform the verification again.
Preferably, at the erase timing C1, the first voltage step of the step erase voltage has a preliminary erase voltage, the last voltage step of the step erase voltage has a target erase voltage, and the preliminary erase voltage is 20% to 70% of the target erase voltage.
Preferably, the step increase D is preset-eraseThe value of (b) is 5% to 30% of the target erase voltage value.
Preferably, the step erase voltage is increased by an amount D-eraseRemain unchanged or decrease as the step rises.
Preferably, the preset number of voltage steps is 2 to 5.
Preferably, the target erase voltage ranges from 18V to 24V.
Preferably, the preset step width is 0.05-0.5 s.
Preferably, at erase timing C1, the first voltage is applied to all word lines and the step erase voltage is applied to the substrate of the memory cell.
Preferably, at the time of verifying timing Y1, a verification voltage is applied to all word lines, and all bit lines are precharged to a precharge voltage; and then discharging all the bit lines for the first time, comparing the voltage of the discharged bit lines with a first judgment voltage, if the voltages of the discharged bit lines are lower than the first judgment voltage, indicating that the verification is successful and the operation can be finished, otherwise, indicating that the verification fails and erasing and verifying the memory again, wherein the verification voltage ranges from 0V to 1V, and the pre-charging voltage ranges from 1V to 1.2V.
In a second aspect, the present invention further provides an erasing system of a memory, the erasing system of the memory comprising: an erase module for applying a step erase voltage to the memory cell when erasing timing sequence C1, the step erase voltage having a voltage waveform with a step rise, the voltage waveform including a preset number of voltage steps, each voltage step having a preset step width, a preset step amplification D between adjacent voltage steps-erase(ii) a The verification module is used for applying verification voltage to the storage unit when verifying the time sequence Y1, and the verification is finished if the verification is successful; if the verification fails, the erase module increases the magnitude of the erase voltage again after verifying the timing Y1, and the verification module performs the verification again.
Compared with the prior art, the invention provides the erasing method and the erasing system of the memory, the step erasing voltage is applied to the memory unit, the step erasing voltage has a voltage waveform with step ascending, the voltage waveform comprises a preset number of voltage steps, each voltage step has a preset step width, and a preset step increasing D is arranged between adjacent voltage steps-eraseThe erase voltage is not increased to the maximum value of the step erase voltage at one time, so that the voltage difference between the floating gate and the substrate of the memory cell is small, the peak current during the erase period can be effectively reduced, and the reliability of the memory cell is improved.
Drawings
FIG. 1 is a flowchart illustrating a method for erasing a memory according to an embodiment of the present invention.
Fig. 2 is a schematic chip structure diagram of a memory cell in embodiment a of the invention.
FIG. 3 is a circuit diagram of a memory array according to an embodiment of the present invention.
FIG. 4 is a waveform diagram of voltages at different times of the erasing method of the memory according to embodiment A of the present invention.
FIG. 5 is a graph showing the variation of the magnitude of the erase voltage with the increase of the number of verification failures in the embodiment A.
FIG. 6 is a block diagram of an erasing system of a memory according to embodiment B of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example A
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an erasing method of a memory according to an embodiment a of the present invention, the erasing method of the memory is used for improving the endurance and the usability of read data of the memory to improve the lifetime of the memory, and the erasing method of the memory includes the following steps:
step S1: erasing timing C1, applying a step erase voltage having a step-like rising voltage waveform including a preset number of voltage steps each having a preset step width to the memory cellDegree, with a predetermined step increase D between adjacent voltage steps-erase；
Step S2: when the time sequence Y1 is verified, applying verification voltage to the memory cell, and finishing verification if verification is successful;
step S3: if the verification fails, the magnitude of the erase voltage is increased again after the verification timing Y1 to perform the verification again.
Referring to fig. 2, fig. 2 is a schematic diagram of a chip structure of the memory unit 111. The memory cell 111 includes a substrate 1111, a source 1112, a drain 1113, a tunnel oxide film 1114, a floating gate 1115, and a control gate 1116, the substrate 1111 includes a P-well region thereon, the source 1112 and the drain 1113 are disposed in the P-well region, a channel is formed between the source 1112 and the drain 1113, the tunnel oxide film 1114 is formed over the channel between the source 1112 and the drain 1113, the floating gate 1115 is disposed on the tunnel oxide film 1114, and the control gate 1116 is disposed on the floating gate 1115. It will be appreciated that a dielectric film 1117 is disposed between the control gate 1116 and the floating gate 1115. When no charge is accumulated in the floating gate 1115, that is, when data "1" is written, the threshold value is in a negative state, and the memory cell 111 is turned on by the control gate 1116 being 0V. When electrons are accumulated in the floating gate 1115, that is, when data "0" is written, the threshold shift is positive, and the memory cell is turned off by the control gate 1116 being 0V. However, the memory cell is not limited to storing a single bit, and may store a plurality of bits.
In step S1, step S1 is an erasing step, and the data is erased from the memory. The memory is preferably a NAND type memory. Referring to fig. 3, fig. 3 is a schematic circuit structure diagram of the memory array. The memory includes n word lines (WL1, WL2, …, WLn), m bit lines (BL1, BL2, …, BLm), a select gate line SGS, a select gate line SGD, and a common source line SL, and a memory cell portion identified by a dashed box 11 is referred to as a memory cell string. Each memory cell string includes a plurality of the above-described memory cells 111 (i.e., MC1 to MCn); a bit line side selection transistor TD connected to the memory cell MCn as one end portion; and a source-line-side selection transistor TS connected to the memory cell MC1 as the other end, the drain of the bit-line-side selection transistor TD being connected to the corresponding 1 bit line BL, and the source of the source-line-side selection transistor TS being connected to the common source line SL. The control gate of the memory cell 111 is connected to a word line WLi (i is 0 to n), the gate of the bit line side selection transistor TD is connected to the selection gate line SGD, and the gate of the source line side selection transistor TS is connected to the selection gate line SGS.
Referring to fig. 4 and 5 together, fig. 4 is a schematic diagram of waveforms at different times of an erasing method of a memory according to the present invention, fig. 5 is a schematic diagram of an amplitude variation of an erase voltage amplitude with an increase of a verification failure frequency in embodiment a, and this embodiment provides a specific erasing step, in which, during an erasing timing C1, a first voltage is applied to all word lines WL 1-WLn, a step erase voltage is applied to a substrate 1111 of a memory cell 111, the step erase voltage has a voltage waveform with a step rise, the voltage waveform includes a predetermined number of voltage steps, each voltage step has a predetermined step width, and a predetermined step rise D is provided between adjacent voltage steps-erase. The first voltage is 0V or a negative voltage. It is understood that the voltages applied to the substrate 1111 of the memory cell 111 after the erase timing C1 and the erase timing C1 are the erase voltage VersErase voltage VersThe range of (A) is 18 to 24V, preferably 19 to 23V. Erase voltage VersIt will be transferred to all bit lines BL and the common source line SL through the substrate PN junction of the memory module in a forward conduction state, leaving the select gate line SGD and the select gate line SGS in a floating state.
In this embodiment, the preset number of voltage steps is 3. The first voltage step of the step erase voltage has a preliminary erase voltage Vers1The last voltage step of the step erase voltage has the target erase voltage. The target erase voltage ranges from 18V to 24V. Specifically, at the erase timing C1, a first voltage is applied to all word lines WL1 WLn, and a first voltage step of a step erase voltage, i.e., a preliminary erase voltage V, is applied to the substrate 1111 of the memory cell 111ers1Maintaining the magnitude V of the step erase voltageers1Keeping the first time constant, and then making the amplitude V of the step erasing voltageers1Increasing step amplification D-eraseEraser for cleaning stepsThe amplitude of the divided voltage is Vers1+D-erase(ii) a Amplitude V of re-dimensional step erase voltageers1+D-eraseKeeping the first time constant, and then making the amplitude V of the step erasing voltageers1+D-eraseIncreasing step amplification D-eraseThe magnitude of the step erase voltage is Vers1+D-erase+D-erase＝Vers1+2D-erase(ii) a Then maintaining the amplitude V of the step erase voltageers1+2D-eraseKeeping the first time constant, and then making the amplitude V of the step erasing voltageers1+2D-eraseIncreasing step amplification D-eraseThe magnitude of the step erase voltage is Vers1+2D-erase+D-erase＝Vers1+3D-erase. Amplitude V of step erase voltage at this timeers1+3D-eraseMaximum value for step erase voltage: a target erase voltage.
Step erase voltage VersThat is, an erase voltage which should be applied to the substrate 1111 of the memory cell 111 for the first time when erasing data in the memory in the related art. The invention applies the first voltage step of the step erasing voltage to the substrate 1111 first, then the step erasing voltage is gradually increased to the target erasing voltage in a step shape, the step erasing voltage is not increased to the target erasing voltage at one time, the voltage difference between the floating grid 1115 and the substrate 1111 of the memory unit 111 is smaller, the peak current in the erasing period can be effectively reduced, and the reliability of the memory unit 111 is improved. Preferably, the preliminary erase voltage value Vers1The erase voltage is 20% to 70% of the target erase voltage, for example, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%. Step amplification D-eraseI.e. an increase of the step erase voltage once per step-like rise, preferably a step increase D-erasThe value of (b) is 5% to 30% of the target erase voltage value, and may be, for example, 10%, 15%, 20%, 25%. Preferably, the preset step amplitude D is increased at the time of erasing timing C1-erasKeeping the original shape; or step amplification D-erasDecreasing with step rise, e.g. step increase D-erasComprising a first amplification D-eras1And a second amplification D-eras2When the step erase voltage applied to the substrate 1111 of the memory cell 111 for the first time is increased in a stepwise manner, the step erase voltage is increased by an increase D-eras1When the step erase voltage applied for the second time is increased, the step erase voltage is increased by D-eras2。D-eras1＞D-eras2. Preferably, the preset number of voltage steps is 2 to 5, further preferably 3 or 4. It will be appreciated that the step width is preset as the time for which the voltage step maintains its magnitude. Preferably, the preset step width is 0.05-0.5s, such as 0.1s, 0.2s, 0.3s, 0.4s, and the preset step width of each voltage step may be equal or different. Preferably, in erase timing C1, all adjacent two steps are equal in width.
In step S2, when verifying the timing Y1, a verification voltage is applied to all word lines WL1 to WLn in the memory, and all bit lines BL1 to BLm are precharged to a precharge voltage; and then discharging all the bit lines BL 1-BLm for the first time, comparing the voltage of the discharged bit lines with a first judgment voltage, if the voltages of all the bit lines BL 1-BLm are lower than the first judgment voltage, indicating that the erasing verification operation is successful, and finishing the operation, otherwise, failing the verification, and needing to erase the memory again and verifying the memory. Preferably, the verify voltage ranges from 0V to 1V. The precharge voltage is in a range of 1V to 1.2V, and the first determination voltage is 06 ° to 1V, preferably 0.8V. It is understood that the erase timing C1 is a period of erasing data from all memory cells in a block of memory cells, and the verify timing Y1 is a period of verifying all memory cells after erasing data at the erase timing C1.
In step S3, the verify timing Y1 fails, and the memory cell is again applied with the increased amplitude D at the erase timing C2-CnversUntil the nth erase voltage Vers+(n-1)Dvers(where n is a positive integer, and n ≧ 1) is greater than or equal to the erase threshold, and verification succeeds at the verification timing Yn. In this embodiment, the increase D of the erase voltageversAnd magnitude V of erase voltageers+(n-1)DversIn inverse proportion, wipeThe larger the erase voltage is, the larger the erase voltage isversThe smaller, preferably, the magnitude V with the erase voltageers+(n-1)DversIs increased in stages, DversAnd decreases.
Specifically, when the first threshold of the erase voltage amplitude is m1, the second threshold of the erase voltage amplitude is m2, and the amplitude V of the erase voltage isers+(n-1)DversLess than the first threshold m1, an increase D in the erase voltageversIs Dvers1When the magnitude V of the erase voltageers+(n-1)DversAn increase D in the erase voltage when the first threshold value m1 is not less than the second threshold value m2versIs Dvers2When the magnitude V of the erase voltageers+(n-1)DversAn increase D of the erase voltage at a level not less than a second threshold value m2versIs Dvers3. In this embodiment, the increase D of the erase voltagevers1Amplification D greater than erase voltagevers2Increase of erase voltage Dvers2Amplification D greater than erase voltagevers3The first threshold value of the magnitude of the erase voltage is m1 smaller than the first threshold value of the magnitude of the erase voltage is m 2.
Specifically, the magnitude V of the step erase voltage at the erase timing C2ersLess than the first threshold m1, a first voltage is applied to all word lines WL1 WLn, and an erase voltage V is applied to the substrate of the memory cell 111ers+Dvers1。
When verifying the timing Y2, applying a verification voltage to all word lines WL1 to WLn in the memory, and precharging all bit lines BL1 to BLm to a precharge voltage; all the bit lines BL 1-BLm are then discharged for a first time, and the discharged bit line voltages are compared with a first determination voltage, wherein the bit line voltages are higher than the first determination voltage, and the verification fails.
At the time of erasing timing C3, the magnitude V of the erasing voltageers+Dvers1Less than the first threshold m1, a first voltage is applied to all word lines WL1 WLn, and an erase voltage V is applied to the substrate of the memory cell 111ers+Dvers1+Dvers1＝Vers+2Dvers1。
When verifying the timing Y3, applying a verification voltage to all word lines WL1 to WLn in the memory, and precharging all bit lines BL1 to BLm to a precharge voltage; all the bit lines BL 1-BLm are then discharged for a first time, and the discharged bit line voltages are compared with a first determination voltage, wherein the bit line voltages are higher than the first determination voltage, and the verification fails.
According to the above erase and verify method, the magnitude of the erase voltage applied to the substrate of the memory cell 111 until the erase timing C5 is Vers+2Dvers1+Dvers2+Dvers3When the bit line voltage after discharging is lower than the first judgment voltage, the verification can be successful. At this time, the magnitude V of the erase voltageers+2Dvers1+Dvers2+Dvers3Greater than the erase threshold.
I.e. the magnitude V of the erase voltageers+(n-1)DversIf m1, the erase voltage amplitude of each verification failure is Dvers1，m1≤Vers+(n-1)DversIf m2, the erase voltage amplitude of each verification failure is Dvers2Amplitude V of the erase voltageers+(n-1)DversWhen the voltage is not less than m2, the increase of the erasing voltage is Dvers3. In this embodiment, the erase voltage is amplified by DversThe variation is adjusted in three stages. It is understood that m1, m2, Dvers1、Dvers2And Dvers3The values of (A) can be varied as desired, e.g. m1, m2, Dvers1、Dvers2And Dvers3The value of (c) may vary depending on the erase threshold. Preferably, m2-m1 > Dvers1At Vers+(n-1)Dvers< m1, the magnitude of the erase voltage is increased by Dvers1Nor will the magnitude of the erase voltage be greater than m 2. It is understood that the increase change of the erase voltage can be divided into two stages or more than three stages, and the invention is not limited thereto, and falls within the protection scope of the invention without departing from the concept of the invention.
As the magnitude of the erase voltage increases, the erase voltage gradually approaches the erase threshold. Due to the increased magnitude of the erase voltage, the increase D of the erase voltageversTherefore, after the amplitude of the erase voltage is close to the erase threshold, the amplitude of the erase voltage is increased again due to verification failure, and even if the amplitude of the erase voltage exceeds the erase threshold, the amplitude of the erase voltage does not exceed the erase threshold so as not to affect the tunneling oxide film 1114 of the memory cell 111, thereby reducing the transient erase effect, prolonging the service life of the memory cell of the memory, and ensuring the erase success rate.
Example B
Referring to fig. 6, fig. 6 is a block diagram of the erasing system 12 of the memory according to the present invention. The memory erasing system 12 can perform the memory erasing method provided by any embodiment of the invention. The memory erase system 12 includes:
an erase block 121 for applying a step erase voltage to the memory cell when erasing timing C1, the step erase voltage having a voltage waveform with a step rise, the voltage waveform including a preset number of voltage steps, each voltage step having a preset step width, and a preset step increase D between adjacent voltage steps-erase；
The verification module 122 is configured to apply a verification voltage to the memory cell when verifying the timing sequence Y1, and end the verification if the verification is successful;
if the verification fails, the erase module 121 increases the magnitude of the erase voltage again after the verification timing Y1, and the verification module 122 performs the verification again.
The invention applies step erasing voltage to the substrate 1111, the step erasing voltage has voltage waveform with step rising, the voltage waveform comprises a preset number of voltage steps, each voltage step has a preset step width, and a preset step amplification D is arranged between adjacent voltage steps-eraseThe step erase voltage rises in a step shape for a plurality of times to reach the maximum value of the step erase voltage, and the step erase voltage is not increased to the target erase voltage once, so that the voltage difference between the floating gate 1115 and the substrate 1111 of the memory unit 111 is small, the peak current in the erase period can be effectively reduced, and the reliability of the memory unit is improved.
It is understood that the contents of embodiment a and embodiment B of the present invention can be supplemented and described.
Compared with the prior art, the invention provides the erasing method and the erasing system of the memory, the step erasing voltage is applied to the memory unit, the step erasing voltage has a voltage waveform with step ascending, the voltage waveform comprises a preset number of voltage steps, each voltage step has a preset step width, and a preset step increasing D is arranged between adjacent voltage steps-eraseThe erase voltage is not increased to the maximum value of the step erase voltage at one time, so that the voltage difference between the floating gate and the substrate of the memory cell is small, the peak current during the erase period can be effectively reduced, and the reliability of the memory cell is improved.
It should be noted that, in all the above embodiments, the included units and modules are only divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. An erasing method of a memory, comprising the steps of:
erasing timing C1, applying a step erase voltage having a step-like rising voltage waveform including a preset number of voltage steps each having a preset number of voltage steps to the memory cellWith a predetermined step width D between adjacent voltage steps-erase；
When the time sequence Y1 is verified, applying verification voltage to the memory cell, and finishing verification if verification is successful;
if the verification fails, the magnitude of the erase voltage is increased again after the verification timing Y1 to perform the verification again.
2. An erasing method of a memory according to claim 1, wherein: at the erasing timing sequence C1, the first voltage step of the step erase voltage has a preliminary erase voltage, the last voltage step of the step erase voltage has a target erase voltage, and the preliminary erase voltage is 20% to 70% of the target erase voltage.
3. An erasing method of a memory according to claim 1, wherein: a predetermined step increase D-eraseThe value of (b) is 5% to 30% of the target erase voltage value.
4. An erasing method of a memory according to claim 1, wherein: an increase D of the step erase voltage-eraseRemain unchanged or decrease as the step rises.
5. An erasing method of a memory according to claim 1, wherein: the preset number of the voltage steps is 2 to 5.
6. An erasing method of a memory according to claim 2, characterized in that: the target erase voltage ranges from 18V to 24V.
7. An erasing method of a memory according to claim 1, wherein: the preset step width is 0.05-0.5 s.
8. An erasing method of a memory according to claim 1, wherein: at erase timing C1, a first voltage is applied to all word lines and a step erase voltage is applied to the substrate of the memory cell.
9. An erasing method of a memory according to claim 1, wherein: at the time of verifying timing Y1, a verification voltage is applied to all word lines, and all bit lines are precharged to a precharge voltage; and then discharging all the bit lines for the first time, comparing the voltage of the discharged bit lines with a first judgment voltage, if the voltages of the discharged bit lines are lower than the first judgment voltage, indicating that the verification is successful and the operation can be finished, otherwise, indicating that the verification fails and erasing and verifying the memory again, wherein the verification voltage ranges from 0V to 1V, and the pre-charging voltage ranges from 1V to 1.2V.
10. An erasing system of a memory, the erasing system of the memory comprising:
an erase module for applying a step erase voltage to the memory cell when erasing timing sequence C1, the step erase voltage having a voltage waveform with a step rise, the voltage waveform including a preset number of voltage steps, each voltage step having a preset step width, a preset step amplification D between adjacent voltage steps-erase；
The verification module is used for applying verification voltage to the storage unit when verifying the time sequence Y1, and the verification is finished if the verification is successful;
if the verification fails, the erase module increases the magnitude of the erase voltage again after verifying the timing Y1, and the verification module performs the verification again.
CN201810941458.5A 2018-08-17 2018-08-17 Memory erasing method and system Pending CN110838327A (en)

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CN107924700A (en) * 2015-08-28 2018-04-17 桑迪士克科技有限责任公司 Adaptive multistage erasing

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934064A (en) * 2015-07-07 2015-09-23 合肥恒烁半导体有限公司 Block erasing method for NAND type flash memory
CN106486169A (en) * 2015-08-24 2017-03-08 北京兆易创新科技股份有限公司 A kind of method for deleting of Nand Flash
CN107924700A (en) * 2015-08-28 2018-04-17 桑迪士克科技有限责任公司 Adaptive multistage erasing

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Application publication date: 20200225