CN106486169A - A kind of method for deleting of Nand Flash - Google Patents
A kind of method for deleting of Nand Flash Download PDFInfo
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- CN106486169A CN106486169A CN201510523195.2A CN201510523195A CN106486169A CN 106486169 A CN106486169 A CN 106486169A CN 201510523195 A CN201510523195 A CN 201510523195A CN 106486169 A CN106486169 A CN 106486169A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
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- 230000005669 field effect Effects 0.000 description 3
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- 239000010410 layer Substances 0.000 description 2
- 230000005055 memory storage Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
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- 238000005260 corrosion Methods 0.000 description 1
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- 125000004122 cyclic group Chemical group 0.000 description 1
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Abstract
The invention discloses a kind of method for deleting of Nand Flash, including：S101, to wipe block carry out soft-erase operation；In S102, the verification erasing block, whether memory cell meets erased conditions；If memory cell meets erased conditions in the S103 erasing block, terminate erasing operation；Otherwise execution step S104；S104, to set the current erasure voltage that step value lifting is applied to the erasing block, erasing operation is carried out to the erasing block, return to step S102 afterwards.The method for deleting that the present invention is provided can reduce the charge trap in erase process in Nand Flash memory cell, alleviate the skew of memory cell threshold voltage, and the erasing so as to slow down Nand Flash is failed, and increases its erasing times and then extends its service life.
Description
Technical field
The present invention relates to hardware of memory device technical field, more particularly to a kind of method for deleting of Nand Flash.
Background technology
Nand Flash is one kind of Flash internal memory, belong to non-volatile memory device (Non-volatile Memory Device), which is internal using non-linear macroelement pattern, big with capacity, the advantages of rewriting speed is fast, it is adaptable to the storage of mass data.Fig. 1 is an easy structure figure of Nand Flash in prior art, it is made up of the control unit 15 of memory cell array 11, wordline select unit 12, bit line select unit 13, voltage pump 14 and whole Nand Flash chip, wherein, memory cell array 11 includes memory cell, and the wordline based on each memory cell and bit lines are formed.Specifically, memory cell is first respectively with wordline, bit line connection composition page, and by multiple pages of blockings, the memory cell array 11 for finally constituting a Nand Flash by multiple pieces.Operation to Nand Flash includes three parts：Erasing operation, programming (write operation) and read operation, are carried out erasing operation wherein in units of block, are programmed and read operation in units of page.
In Nand Flash, a memory cell can see a metal oxide semiconductcor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) as.Fig. 2 is a kind of common MOSFET structure figure, including grid 20, source electrode 21, drain electrode 22, P-type silicon Semiconductor substrate 23 and tunnel oxide 24.Its mutual connection is：P-type silicon Semiconductor substrate 23 diffuses out two N-type region, 23 top of P-type silicon Semiconductor substrate covers one layer of tunnel oxide 24, last make two holes with the method for corrosion above N-type region, with metallized method respectively on the insulating layer and two in the holes make three electrodes：Grid 20, source electrode 21 and drain electrode 22, source electrode 21 and drain electrode 22 correspond to two N-type region respectively and grid 20 for memory cell wordline, drain electrode 22 is the bit line of memory cell.Further, grid 20 includes control gate 201, IPD 202 (Inter Poly Dielectric, IPD), floating grid 203 again, and floating grid 203 stores electric charge.In a memory cell, if the setting voltage (as read voltage) of control gate 201 stores charge threshold voltage more than in floating grid 203, show that memory cell is in the conduction state, now state of memory cells is 1；If the setting voltage (as read voltage) of control gate 201 stores charge threshold voltage less than in floating grid 203, show memory cell in not on-state, now state of memory cells is 0.
In Nand Flash, the erasing to Nand Flash and programming operation are realized by applying the threshold voltage of relevant voltage change memory cell floating grid 203 to erasing block or programmed page.The threshold voltage of memory cell floating grid 203 changes the change that can affect state of memory cells, it should be noted that erase and program operations are opposed, existing erasing or operation scheme for programming, once the erasing pulse that erasing or programming process apply or programming pulse are changeless.Based on existing programmed and erased method, in programming operation, some electronics reach floating grid 203 without enough energy during floating grid is tunneling to, but be absorbed in tunnel oxide 24, when erasing operation is carried out, these electronics for being absorbed in tunnel oxide 24 can not be moved in half conductive substrate 23 of p-type by high pressure erasing from tunnel oxide 24.Increase with programmed and erased number of times, the electronics being trapped in tunnel oxide 24 is more and more, can occur the electronics of migration fewer and feweri by erasing operation, cause the skew of memory cell threshold voltage in erase process, the regulation window for making programmed threshold voltage and wiping threshold voltage is less and less, Nand Flash erasing times are reduced, and then shortens the service life of Nand Flash internal memory.
Content of the invention
In view of this, the embodiment of the present invention provides a kind of method for deleting of Nand Flash, to extend the service life of Nand Flash internal memory.
A kind of method for deleting of Nand-Flash is embodiments provided, including：
S101, to wipe block carry out soft-erase operation；
In S102, the verification erasing block, whether memory cell meets erased conditions；
If memory cell meets erased conditions in the S103 erasing block, terminate erasing operation；Otherwise execution step S104；
S104, to set the current erasure voltage that step value lifting is applied to the erasing block, erasing operation is carried out to the erasing block, return to step S102 afterwards.
Further, described to wipe block carry out soft-erase operation, including:
A, apply initial soft-erase voltage for erasing block, and persistently press in Preset Time；
B, with the current soft-erase voltage of setting voltage increment size lifting, equally persistently press in the Preset Time；
If the current soft-erase magnitude of voltage of c is not reaching to preset voltage value, repeat step b.
Further, described to wiping before block carries out soft-erase operation, also include：
Selected by wordline based on the control unit in Nand Flash and bit line selects memory block to be wiped is chosen, be designated as wiping block.
Further, described for wiping the soft initial erasing voltage of block applying, and persistently press in Preset Time, including：
Initial soft-erase voltage is applied to the erasing block by the voltage pump in Nand Flash, and is continued to erasing block pressure from voltage pump in Preset Time, in 5V or so, the scope of the Preset Time is in 10 μ s～150 μ s for the initial soft-erase voltage.
Further, the range set of the preset voltage value is in 12V～15V.
Further, described with the current soft-erase voltage of setting voltage increment size lifting, including：
The current soft-erase voltage that voltage pump is applied with erasing block described in setting voltage increment size lifting is regulated and controled by the control unit in Nand Flash.
Further, described to set the current erasure voltage that step value lifting is applied to the erasing block, including：
Voltage pump is regulated and controled to set the current erasure voltage that step value lifting is applied to the erasing block by the control unit in Nand Flash.
Further, the erase status of the memory cell refer to that the calibration voltage in the memory cell control gate is more than the current threshold voltage of the memory cell.
A kind of method for deleting of Nand Flash provided in an embodiment of the present invention, soft-erase operation is carried out first to wiping block when erasing operation is carried out, if after having carried out soft-erase operation, erasing block internal memory storage unit is not fully achieved erase status yet, then apply erasing voltage to its circulation again and progressively lifting erasing voltage in circulating every time.The method can reduce the charge trap in erase process in Nand Flash memory cell, alleviate the skew of memory cell threshold voltage, and the erasing so as to slow down Nand Flash is failed, and increases its erasing times and then extends its service life.
Description of the drawings
Fig. 1 is the easy structure figure of Nand Flash；
Fig. 2 is a kind of structure chart of the metal oxide semiconductcor field effect transistor as memory cell in Nand Flash；
Fig. 3 is a kind of flow chart of the method for deleting of Nand Flash that the embodiment of the present invention one is provided；
Fig. 4 is a kind of flow chart of the method for deleting of Nand Flash that the embodiment of the present invention two is provided.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that specific embodiment described herein is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, for the ease of description, in accompanying drawing, illustrate only part related to the present invention rather than full content.
Embodiment one
Fig. 3 is a kind of flow chart of the method for deleting of Nand Flash that the embodiment of the present invention one is provided, and the method is executed by Nand Flash, is one kind improvement to existing method for deleting, as shown in figure 3, the method includes：
Step S101, to wipe block carry out soft-erase operation.
In the present embodiment, the erasing block concretely in the memory cell array of Nand Flash for erasing operation a memory cell block.The erasing operation is carried out in units of memory cell block, the memory cell array of the Nand Flash is made up of multiple memory cell blocks, the memory cell block is made up of multiple memory cell pages, and the memory cell page is made up of with ranks connection multiple memory cell.In a memory cell page, often go by multiple memory cell and connected with wordline, each column is connected with bit line by multiple memory cell, and a memory cell page shares a wordline, a memory cell block shares a bit line.
Exemplary, in single layer cell (the Single-Level Cell that a memory size is 8GB, SLC) in Nand Flash particle, one memory cell page includes the main memory area of 4KB and the shared region of 0.125KB, one memory block is made up of 64 memory pages, i.e., the main memory area of a memory block is 256KB, and shared region is 8KB, one Nand Flash particle is made up of 4096 memory cell blocks, and its memory size is total up to 8448MB and is about 8GB.
In the present embodiment, the improvement to existing erasing operation can be divided into two parts：Soft-erase operation and circulation erasing operation, when soft-erase operation does not make erasing block reach erase status, are then circulated erasing operation.In existing erasing operation, it is initially erasing block and directly applies a higher initial erasing voltage value, the electronics for being now absorbed in tunnel oxide smoothly can not be moved in half conductive substrate of p-type under the high erasing voltage value for being applied, and thereby result in the skew of memory cell threshold voltage.
The soft-erase operation can regard the part improved by existing erasing operation as.The soft-erase that the present embodiment is proposed is operated concretely：First apply relatively low initial erasing voltage value for erasing block, and erasing voltage is slowly increased, and increased erasing voltage is finally not more than the initial erasing voltage value in existing erasing operation.Erasing block can effectively reduce the electronics of the delay in tunnel oxide by soft-erase operation.
In S102, the verification erasing block, whether memory cell meets erased conditions.
In the present embodiment, the course of work of Nand Flash includes programming operation, erasing operation etc., these operate whether the current state generally to judge memory cell changes to realize, the change of the memory cell current state is based primarily upon the electric charge of floating grid in memory cell how much judging, judged with the size of setting voltage according to the threshold voltage of memory cell, if the threshold voltage of memory cell is less than setting voltage, then the state of explanation memory cell is 0, it is in and wants erase status, if the threshold voltage of memory cell is more than setting voltage, then the state of explanation memory cell is 1, in programmable state.
In the present embodiment, after the soft-erase operation of execution of step S101, first the erasing block can be verified, judge whether memory cell meets erased conditions in the erasing block, in Nand Flash, meet the erased conditions and can specifically refer to that the threshold value for wiping most memory cell in block below wipes calibration voltage, the memory cell number of erase status is not reaching to less than error checking and correct algorithm (Error Correcting Code, ECC) the ability that can be corrected, the ECC is the technology that one kind can realize " error checking and correction ", ECC internal memory is exactly the internal memory for applying this technology, typically apply on server and graphics workstation more, this will make whole computer system operationally more they tend to safety and stability.
If memory cell meets erased conditions in the S103 erasing block, terminate erasing operation；Otherwise execution step S104；
In the present embodiment, the memory cell of erasing block can be made to reach erased conditions if the soft-erase for only carrying out step S101 to wiping block is operated, following step need not so be executed, but the erasing operation of Nand Flash is often a cyclic process, only carrying out soft-erase operation possibly cannot make the state of memory cells of erasing block reach 1 and then meet erased conditions, need to be circulated erasing further.
Exemplary, if the current state in the erasing block in memory cell is not 1 for not meeting the current state of erased conditions, i.e. memory cell, just need execution step S104 to be circulated erasing operation；If the current state in the erasing block in memory cell is erase status, shows erasing operation is completed, erasing operation can be terminated.If it should be noted that being not over erasing operation after carrying out soft-erase operation, the current erasure voltage for being applied to erasing block when step S104 is started is the erasing voltage at the end of soft-erase operation.
S104, to set the current erasure voltage that step value lifting is applied to the erasing block, erasing operation is carried out to the erasing block, return to step S102 afterwards.
In the present embodiment, in two stages, the stage one refers specifically to the current erasure voltage：After soft-erase operation terminates, the soft-erase voltage that the erasing block applies, stage two are referred specifically to：Circulate in erasing, again execution step S102 and the after-applied erasing voltage on erasing block of S103.
In the present embodiment, as erase process is storage process of the electric charge to the mobile change threshold voltage of P-type silicon Semiconductor substrate in memory cell floating grid, if the memory cell for wiping block after soft-erase operation is not reaching to erase status, then in order to reduce the charge trap in erase process in Nand Flash memory cell, the present embodiment is in an erasing operation of circulation erasing operation, using the strategy of gradually lifting erasing voltage, the current erasure voltage is to set step value lifting.
Further, voltage pump can be regulated and controled to set the current erasure voltage that step value lifting is applied to the erasing block by the control unit in Nand Flash.
In the present embodiment, the excursion of the step value is typically in 0.1V～2V, described in erasing operation depending on concrete condition of the setting of step value size according to Nand Flash chip.
A kind of method for deleting of Nand Flash that the embodiment of the present invention one is provided, its erase process is divided into soft-erase operation and following cycle erasing operation.Soft-erase operation is carried out for erasing block first, if after completing soft-erase operation, erasing block internal memory storage unit is not fully achieved erase status yet, then apply erasing voltage to its circulation again and progressively lifting erasing voltage in circulating every time.Method for deleting based on the embodiment of the present invention, Nand Flash can weaken the effect for producing charge trap in erase process, so as to the threshold voltage of floating grid is altered in steps, the memory cell in block to be wiped is made to progressively reach erase status, alleviate the problem of threshold window skew in erase process and programming process, it is possible thereby to increase the erasing times of Nand Flash, the effect for extending Nand Flash service life is reached.
Embodiment two
Fig. 4 is a kind of flow chart of the method for deleting of Nand Flash provided in an embodiment of the present invention, and the present embodiment is optimized based on above-described embodiment, and in the present embodiment, step is carried out soft-erase operation optimization for erasing block is：A, apply initial soft-erase voltage for erasing block, and persistently press in Preset Time；B, with the current soft-erase voltage of setting voltage increment size lifting, equally persistently press in the Preset Time；If the current soft-erase magnitude of voltage of c is not reaching to preset voltage value, repeat step b.
Further, before step applies initial soft-erase voltage for erasing block, step also add：
Selected by wordline based on the control unit in Nand Flash and bit line selects memory block to be wiped is chosen, be designated as wiping block.
Accordingly, the method for the present embodiment comprises the steps：
S201, selected by wordline based on the control unit in Nand Flash and bit line selects memory block to be wiped is chosen, be designated as wiping block.
In the present embodiment, the reading of whole Nand Flash, programming, erasing operation are all realized by described control unit, in the erasing operation of Nand Flash, need to select erasing block before carrying out erasing operation, the erasing block chooses to be wiped memory block according to its logical address by addressing by wordline select unit and bit line select unit by control unit.
S202, apply initial soft-erase voltage for erasing block, and persistently press in Preset Time.
In the present embodiment, described apply initial soft-erase voltage and concretely wipe the control gate of block in Nand Flash extremely to apply low pressure, apply positive high voltage in the p-well that P-type silicon semiconductor is formed, so that the electric charge in floating grid is moved in P-type silicon Semiconductor substrate.Preferably, the low pressure extremely applied in the control gate of erasing block is less than 1V, and the positive high voltage applied in the p-well is not more than 5V.
Further, initial soft-erase voltage can be applied to the erasing block by the voltage pump in Nand Flash, and continued to erasing block pressure from voltage pump in Preset Time, in 5V or so, the scope of the Preset Time is in 10 μ s～150 μ s for the initial soft-erase voltage.
S203, with the current soft-erase voltage of setting voltage increment size lifting, equally persistently press in the Preset Time.
In the present embodiment, the setting voltage increment size is a fixed value, i.e., the soft-erase magnitude of voltage of lifting is constant every time, it is preferred that the scope control of the voltage increment value is in 0.5V～1.5V.The current soft-erase voltage of the lifting is easy to the electric charge in memory cell floating grid to the movement of P-type silicon Semiconductor substrate.
Further, the current soft-erase voltage that voltage pump is applied with erasing block described in setting voltage increment size lifting can be regulated and controled by the control unit in Nand Flash.
S204, judge whether current soft-erase magnitude of voltage reaches preset voltage value, if so, then execution step S205；If it is not, then return to step S203.
In the present embodiment, there is the restriction of magnitude of voltage for wiping the soft-erase voltage that block applies in the soft-erase operation, compared with existing erasing operation, therefore soft-erase operation can not can be interpreted as circulating the pre- erasing operation before erasing by the peak of the soft-erase voltage more than for wiping the initial voltage that block applies in existing erasing operation.Usually, in existing erasing operation, the initial voltage value for being applied is usually 12V～15V or so.
Further, the range set of the preset voltage value is in 12V～15V.
S205, judge described erasing block in memory cell whether meet erased conditions, if it is not, then execution step S206；If so, then execution step S207.
In the present embodiment, the verification whether memory cell in the erasing block meets erased conditions is executed by the control unit of Nand Flash.
Further, the erase status of the memory cell refer to that the calibration voltage in the memory cell control gate is more than the current threshold voltage of the memory cell.
In the present embodiment, the setting voltage in the memory cell control gate is a specific voltage, exemplary, can apply read voltage to control gate.The setting voltage is used for the comparison with floating grid threshold voltage, and when threshold voltage value is less than setting voltage, the state of memory cell is 1, shows that the memory cell reaches erase status.
S206, to set the current erasure voltage that step value lifting is applied to the erasing block, erasing operation is carried out to the erasing block, return to step S204 afterwards.
In the present embodiment, the excursion of the step value is typically in 0.1V～2V, described in erasing operation depending on concrete condition of the setting of step value size according to Nand Flash chip.In each erasing operation of circulation erasing, step value is transformable, and the amplitude of variation of the step value is not limited, it is preferred that be set as increasing 1V every time by the amplitude of variation of step value.Lifting erasing voltage can increase storage moving number of the electric charge to P-type silicon Semiconductor substrate in memory cell floating grid, faster change threshold voltage, accelerate the speed that memory cell reaches erase status, so as to complete erasing operation as early as possible.
S207, end erasing operation.
In the present embodiment, if memory cell meets erased conditions in the erasing block, show to complete the erasing operation for being chosen erasing block in Nand Flash, so as to terminate erasing operation.
A kind of method for deleting of Nand Flash that the embodiment of the present invention two is provided, it is the optimization to the embodiment of the present invention one, soft-erase operation will be carried out for erasing block first to be embodied as applying initial soft-erase voltage, judge whether soft-erase voltage reaches to pre-set, if reaching preset value, then the operation after carrying out, otherwise, with certain voltage increment size lifting soft-erase voltage；Meanwhile, selecting to select to choose memory block to be wiped with bit line by wordline based on the control unit in Nand Flash for before wiping the initial soft-erase voltage of block applying, increased step.Method for deleting based on the embodiment of the present invention, by executing soft-erase operation and circulation erasing operation afterwards, generation charge trap in Nand Flash erase process can effectively be weakened, alleviate the problem of threshold window skew in erase process and programming process, thus increase the erasing times of Nand Flash, reach the effect for extending Nand Flash service life.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that the invention is not restricted to specific embodiment described here, various obvious changes can be carried out for a person skilled in the art, readjusted and substitute without departing from protection scope of the present invention.Therefore, although being described in further detail to the present invention by above example, the present invention is not limited only to above example, without departing from the inventive concept, other Equivalent embodiments more can also be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (8)
1. a kind of method for deleting of Nand Flash, it is characterised in that include：
S101, to wipe block carry out soft-erase operation；
In S102, the verification erasing block, whether memory cell meets erased conditions；
If memory cell meets erased conditions in the S103 erasing block, terminate erasing operation；Otherwise
Execution step S104；
S104, with set step value lifting be applied to described erasing block current erasure voltage, to the erasing
Block carries out erasing operation, afterwards return to step S102.
2. method according to claim 1, it is characterised in that described carry out soft-erase behaviour to wiping block
Make, including:
A, apply initial soft-erase voltage for erasing block, and persistently press in Preset Time；
B, with the current soft-erase voltage of setting voltage increment size lifting, equally persistently apply in the Preset Time
Pressure；
If the current soft-erase magnitude of voltage of c is not reaching to preset voltage value, repeat step b.
3. method according to claim 1, it is characterised in that described carry out soft-erase behaviour to wiping block
Before work, also include：
Selected by wordline based on the control unit in Nand Flash and bit line selects to choose storage to be wiped
Block, is designated as wiping block.
4. method according to claim 2, it is characterised in that described apply soft initial wiping for wiping block
Except voltage, and persistently press in Preset Time, including：
Initial soft-erase voltage is applied to the erasing block by the voltage pump in Nand Flash, and default
Continued to erasing block pressure from voltage pump in time, the initial soft-erase voltage is in 5V or so, described pre-
If the scope of time is in 10 μ s～150 μ s.
5. method according to claim 2, it is characterised in that the range set of the preset voltage value
In 12V～15V.
6. method according to claim 2, it is characterised in that described with setting voltage increment size lifting
Current soft-erase voltage, including：
Voltage pump is regulated and controled to wipe described in setting voltage increment size lifting by the control unit in Nand Flash
The current soft-erase voltage that block applies.
7. method according to claim 2, it is characterised in that described applied with setting step value lifting
To described erasing block current erasure voltage, including：
Voltage pump is regulated and controled by the control unit in Nand Flash the wiping is applied to set step value lifting
Current erasure voltage except block.
8. method according to claim 2, it is characterised in that the erase status of the memory cell refer to
Calibration voltage in the memory cell control gate threshold voltage current more than the memory cell.
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| CN109407385A (en) * | 2017-08-15 | 2019-03-01 | 肯特显示器公司 | The erasable electronic writing device of selectivity with user's adjustment |
| CN109407385B (en) * | 2017-08-15 | 2022-08-30 | 肯特显示器公司 | Selectively erasable electronic writing instrument with user adjustment |
| CN110838327A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Memory erasing method and system |
| CN110838328A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Memory erasing method and system |
| CN110838329A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Memory erasing method and system |
| CN110838328B (en) * | 2018-08-17 | 2021-09-10 | 北京兆易创新科技股份有限公司 | Memory erasing method and system |
| CN110838329B (en) * | 2018-08-17 | 2022-04-01 | 北京兆易创新科技股份有限公司 | Memory erasing method and system |
| US10892025B2 (en) | 2019-06-13 | 2021-01-12 | Western Digital Technologies, Inc. | Soft erase and programming of nonvolatile memory |
| CN110289038A (en) * | 2019-07-02 | 2019-09-27 | 珠海创飞芯科技有限公司 | The connection method of the bit line and sense amplifier of nand flash memory and sense amplifier |
| CN113284539A (en) * | 2020-02-20 | 2021-08-20 | 桑迪士克科技有限责任公司 | Program voltage modulation during cycling |
| CN113284539B (en) * | 2020-02-20 | 2024-06-04 | 桑迪士克科技有限责任公司 | Programming voltage modulation during cycling |
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