CN107331419A - The method for screening out initial failure in flash cell - Google Patents
The method for screening out initial failure in flash cell Download PDFInfo
- Publication number
- CN107331419A CN107331419A CN201710543541.2A CN201710543541A CN107331419A CN 107331419 A CN107331419 A CN 107331419A CN 201710543541 A CN201710543541 A CN 201710543541A CN 107331419 A CN107331419 A CN 107331419A
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- Prior art keywords
- voltage
- flash cell
- initial failure
- screening out
- wordline
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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- Non-Volatile Memory (AREA)
Abstract
Screened out what the present invention was provided in flash cell in the method for initial failure, the voltage difference in the flash cell at tunnel oxide is controlled in 4V~10V, and the voltage difference at oxide layer is controlled in 4V~8V.It can so make the existing voltage difference of voltage difference ratio at the voltage difference and oxide layer in the flash cell at tunnel oxide low, it is to avoid the oxide in the flash cell is damaged by high pressure, the flash memory is kept endurance quality.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of side for screening out initial failure in flash cell
Method.
Background technology
The standard physical structure of flash memory is referred to as flash cell (bit).The structure and conventional MOS transistor of flash cell are not
Together：The grid (gate) of conventional MOS transistor is separated between conducting channel by gate insulator, generally oxide layer；And dodge
There is control gate (CG：Control gate, equivalent to the grid of conventional MOS transistor) also there is floating boom between conducting channel
(FG：floating gate).Due to the presence of floating boom, flash memory is set to complete three kinds of basic manipulation modes：Read and write, program,
Erasing.Even if in the case where no power supply is supplied, the presence of floating boom can keep the integrality of data storage.Adjacent flash memory
Separated between unit by isolation structure.
Flush memory device (flash memory) is with performance advantages such as its low cost, low-power consumption, in nonvolatile storage
Field occupies leading position.Constantly sent out with the flash cell of memory device towards the direction of high integration and high capacity
Exhibition, manufacturing process is more and more cumbersome, and the possibility for occurring defect in the fabrication process is also lifted therewith.
The definition of reliability (reliability) is：Product under prescribed conditions with complete relevant regulations in the stipulated time
The ability of effect.When testing for flash memory, it is commonly applied high pressure to filter out initial failure to ensure the reliable of flash memory
Property.When the IP address to flash memory is operated (such as erasing-programming/reading), the maximum position of voltage difference is easy in flash memory
Suffered damage because of the presence of initial failure.
Therefore, it is necessary to propose a kind of new method to screen out the initial failure in flash cell, it is to avoid the durability of flash memory
It can incur loss.
The content of the invention
It is an object of the invention to provide a kind of method for screening out initial failure in flash cell, to solve existing screening out
During initial failure, the problem of oxide that the high pressure of application is easily damaged in flash memory, influence flash memory endurance quality.
In order to solve the above technical problems, the present invention provides a kind of method for screening out initial failure in flash cell, carrying out
Screen out in flash cell during initial failure, tunnel through the voltage difference at oxide layer and control in 4V~10V, at oxide layer
Voltage difference control in 4V~8V.
Optionally, in the method for initial failure in screening out flash cell, the initial failure in progress screens out flash cell
During, apply first voltage at the wordline in the flash cell, meanwhile, at the control gate in the flash cell
Apply second voltage；Voltage difference between the second voltage applied at the first voltage applied at the wordline and the control gate
Scope is 15V~20V.
Optionally, in the method for initial failure in screening out flash cell, the first voltage applied at the wordline is just
Voltage.
Optionally, in the method for initial failure in screening out flash cell, the first voltage range applied at the wordline
For 4V~8V.
Optionally, in the method for initial failure in screening out flash cell, the first voltage applied at the wordline is 8V.
Optionally, in the method for initial failure in screening out flash cell, the second voltage applied at the control gate is
Negative voltage.
Optionally, in the method for initial failure in screening out flash cell, the second voltage model applied at the control gate
Enclose for -9V~-7V.
Optionally, in the method for initial failure in screening out flash cell, at the control gate apply second voltage for-
9V。
Optionally, the first voltage applied in the method for initial failure in screening out flash cell at the wordline and institute
It is 7 seconds~9 seconds to state the second voltage time range applied at control gate.
Optionally, the first voltage applied in the method for initial failure in screening out flash cell at the wordline and institute
It is 8 seconds to state the second voltage time applied at control gate.
Optionally, in the method for initial failure in screening out flash cell, the flash cell includes substrate and formation
Wordline and control gate on the substrate surface.
Optionally, in the method for initial failure in screening out flash cell, the tunnel oxide is located at wordline and control
Between grid.
Optionally, in the method for initial failure in screening out flash cell, the oxide layer is located between wordline and substrate.
For 90nm flash cells, in erasing operation is carried out, the position of maximum voltage deviation wordline and control gate it
Between.When carrying out wafer sort, by wiping function, word line position voltage is set to 9V, control gate position is set to -8V, and
Potential initial failure is screened out with the stress time of 8 seconds.But the test condition also generates side effect simultaneously：Now tunnelling
The voltage difference that voltage difference at oxide layer is more than at 10V, oxide layer is 9V, and voltage difference is too high slightly to have damaged oxide, shadow
The endurance quality of flash memory is rung.
Screened out what the present invention was provided in flash cell in the method for initial failure, by tunnel oxide in the flash cell
Voltage difference at layer is controlled in 4V~10V, and the voltage difference at oxide layer is controlled in 4V~8V.The sudden strain of a muscle can so be made
The existing voltage difference of voltage difference ratio at voltage difference and oxide layer in memory cell at tunnel oxide is low, it is to avoid the flash memory
Oxide in unit is damaged by high pressure, the flash memory is kept endurance quality.
Brief description of the drawings
Fig. 1 is the structural representation of flash cell in the embodiment of the present invention；
Shown in figure：1- tunnel oxides；2- oxide layers；3- wordline；4- control gates；41- floating booms；5- substrates；6- bit lines.
Embodiment
The method proposed by the present invention for screening out initial failure in flash cell is made below in conjunction with the drawings and specific embodiments
It is further described.According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted
That accompanying drawing is using very simplified form and uses non-accurately ratio, only to it is convenient, lucidly aid in illustrating this hair
The purpose of bright embodiment.
It is flash memory unit structure schematic diagram as shown in Figure 1.Existing flash memory unit structure mainly includes substrate 5 and formed
Wordline 3, control gate 4 and bit line 6 on the surface of substrate 5, control gate 4 also include floating boom 41；Specifically, the flash cell
Also include tunnel oxide 1 and oxide layer 2.Further, the tunnel oxide 1 is located at the wordline 3 and the control gate 4
Between；The oxide layer 2 is located between the wordline 3 and the substrate 5.
For flash cell, in erasing operation usually, word line voltage (corresponding to first voltage) is set to 8V,
Control-grid voltage (corresponding to second voltage) is set to -7V；In programming operation usually, word line voltage is set to 1.5V, control
Gate voltage processed is set to 8V, and bit-line voltage is set to 5V；In read operation usually, word line voltage is set to 4V, control gate
Voltage is set to 4V, and bit-line voltage is set to 0.8V.It follows that for flash cell, when carrying out erasing operation, word
Voltage between line and control gate is maximum, therefore, in the method for considering to screen out initial failure in flash cell in flash cell
Oxide high pressure damage and endurance quality influence factor in, erasing operation test in wordline 3 and control gate 4 between
Voltage between voltage, and wordline 3 and substrate 5 is most important.
Inventor has found to calculate by the capacitive coupling coefficient of tunnel oxide 1 between wordline and control gate, and combines meter
The result of calculation each voltage is adjusted the cooperation realizing voltage, you can at the same realize flash cell initial failure screen out and
Reduce the influence to endurance quality.
In erasing operation usually, word line voltage is 8V, and control-grid voltage is -7V, and stress time is 300 seconds, then leads to
The voltage difference crossed at the calculating of capacitive coupling coefficient, tunnel oxide 1 is 8- (8*15%-7*35%)=9.25V, oxide layer 2
The voltage difference at place is 8V；And in the initial failure of prior art screens out experiment, word line voltage is 9V, control-grid voltage is -8V,
Stress time is 8 seconds, then by the calculating of capacitive coupling coefficient, and the voltage difference at tunnel oxide 1 is 9- (9*15%-8*
35%) voltage difference at=10.45V, oxide layer 2 is 9V；As can be seen here, 10.45V is far longer than 9.25V, will necessarily be to tunnelling
Endurance quality at oxide layer 1 causes a devastating effect；9V is also far longer than 8V, also will necessarily be to the durability at oxide layer 2
It can cause a devastating effect.
At present in erasing operation is carried out to flash cell, the position of maximum voltage deviation in wordline 3 (word line) and
Between control gate 4 (control gate).It is existing carry out wafer sort when, by wiping function, generally by the position of wordline 3
Voltage is set to 9V, and the position of control gate 4 is set to -8V, and screens out with the stress time of 8 seconds potential initial failure.Inventor
It was found that, the test condition also generates side effect simultaneously：Now in flash cell, the voltage difference at tunnel oxide 1 is more than
2 voltage difference is 9V at 10V, oxide layer, and the oxide that too high voltage difference has been damaged in flash cell have impact on the resistance to of flash memory
Long performance.
Therefore, the method for screening out initial failure in flash cell that the present invention is provided, early in the flash cell is screened out
During phase fails, by controlling the voltage difference in the flash memory at tunnel oxide 1 and at oxide layer 2, it is to avoid too high
The oxide that voltage difference is damaged in the flash cell.The method for screening out initial failure in flash cell includes：
Screen out in flash cell during initial failure, tunneling through the voltage difference at oxide layer 1 and control in 4V
~10V, the voltage difference at oxide layer 2 is controlled in 4V~8V.
In the initial failure in screening out the flash cell, apply the at the wordline 3 in the flash cell
One voltage, while applying second voltage at the control gate 4 in the flash cell.Further, applied at the wordline 3
Plus first voltage and the control gate 4 at apply second voltage time range be 7 seconds~9 seconds, so as to as best one can
Screen out potential initial failure in the flash cell.Further, the first voltage being applied at the wordline 3 and application
The sustained stress time of second voltage at the control gate 4 is 8 seconds.
In the initial failure method screened out in the flash cell in the present invention, if necessary to be carried out to initial failure
Effectively screen out, then the voltage between wordline and control gate has to keep 17.5V or so, if avoiding durability loss of energy,
Then the voltage difference at tunnel oxide 1 and at oxide layer 2 must be reduced.
Therefore, calculating of the inventor based on capacitive coupling coefficient, is improved to the existing method that screens out, by word line voltage
(i.e. first voltage) is set to 8V, and control-grid voltage (i.e. second voltage) is set into -9V, and stress time is 8 seconds.
So both the voltage between wordline 3 and control gate 4 can be made to be maintained at 17V, realize screening out for initial failure, and
By the calculating of capacitive coupling coefficient, the voltage difference at tunnel oxide 1 is 8- (8*15%-9*35%)=9.95V, compared to
10.45V in existing method, having significantly reduces；Voltage difference at oxide layer 2 is 8V, compared in existing method
9V, also achieves and is greatly lowered, it is to avoid the oxide that too high voltage difference is damaged in the flash cell, realizes reduction pair
The infringement of endurance quality.
Specifically, the first voltage applied at the wordline 3 is positive voltage.Referring to Fig. 1, in the flash cell,
The oxide layer 2 is located between the wordline 3 and the substrate 5, and (not shown) is grounded at the wordline 3, therefore
The size of first voltage of the size of voltage difference with applying at the wordline 3 is identical at the oxide layer 2.There is provided in the present invention
Screen out in flash cell in the method for initial failure, the voltage difference at the oxide layer 2 is controlled in 4V~8V, the wordline
First voltage range at 3 is 4V~8V.The second voltage scope applied at the control gate is -9V~-7V.
Specifically, the second voltage applied at the control gate 4 is negative voltage.Further, by the wordline 3 and described
Voltage difference control is in the range of 15V~20V between control gate 4.
According under the new test condition of above-mentioned offer, the voltage difference described in the flash cell at tunnel oxide 1
Scope is 4V~10V；Meanwhile, the voltage difference scope described in the flash cell at oxide layer 2 is 4V~8V；Surveyed with existing
Strip part is compared, the effective voltage difference and the voltage difference at oxide layer reduced in flash cell at tunnel oxide, is kept away with this
Exempt from the oxide that overtension is damaged in the flash memory, influence the endurance quality of the flash memory.
The method that what the present invention was provided screen out initial failure in flash cell, ensure that the reliability of flash memory, put down simultaneously
Weighing apparatus screens out the efficiency of initial failure, effectively screens out the defective workmanship of flash memory.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (13)
1. a kind of method for screening out initial failure in flash cell, it is characterised in that
Screen out in flash cell during initial failure, tunneling through the voltage difference at oxide layer and control in 4V~10V,
Voltage difference at oxide layer is controlled in 4V~8V.
2. the method as claimed in claim 1 for screening out initial failure in flash cell, it is characterised in that carrying out screening out flash memory
In unit during initial failure, apply first voltage at the wordline in the flash cell, meanwhile, in the flash memory list
Apply second voltage at control gate in member；The second electricity applied at the first voltage applied at the wordline and the control gate
The scope of voltage difference is 15V~20V between pressure.
3. the method as claimed in claim 2 for screening out initial failure in flash cell, it is characterised in that apply at the wordline
First voltage be positive voltage.
4. the method as claimed in claim 4 for screening out initial failure in flash cell, it is characterised in that apply at the wordline
First voltage range be 4V~8V.
5. the method as claimed in claim 5 for screening out initial failure in flash cell, it is characterised in that apply at the wordline
First voltage be 8V.
6. the method as claimed in claim 2 for screening out initial failure in flash cell, it is characterised in that applied at the control gate
Plus second voltage be negative voltage.
7. the method as claimed in claim 7 for screening out initial failure in flash cell, it is characterised in that applied at the control gate
Plus second voltage scope be -9V~-7V.
8. the method as claimed in claim 8 for screening out initial failure in flash cell, it is characterised in that applied at the control gate
Plus second voltage be -9V.
9. the method as claimed in claim 2 for screening out initial failure in flash cell, it is characterised in that apply at the wordline
First voltage and the control gate at apply second voltage time range be 7 seconds~9 seconds.
10. the method as claimed in claim 7 for screening out initial failure in flash cell, it is characterised in that applied at the wordline
Plus first voltage and the control gate at apply the second voltage time be 8 seconds.
11. the method as claimed in claim 1 for screening out initial failure in flash cell, it is characterised in that the flash cell
Including substrate and the wordline formed on the substrate surface and control gate.
12. the method as claimed in claim 1 for screening out initial failure in flash cell, it is characterised in that the tunnel oxide
Layer is located between wordline and control gate.
13. the method as claimed in claim 1 for screening out initial failure in flash cell, it is characterised in that the oxide layer position
Between wordline and substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710543541.2A CN107331419A (en) | 2017-07-05 | 2017-07-05 | The method for screening out initial failure in flash cell |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710543541.2A CN107331419A (en) | 2017-07-05 | 2017-07-05 | The method for screening out initial failure in flash cell |
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| CN107331419A true CN107331419A (en) | 2017-11-07 |
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Citations (5)
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|---|---|---|---|---|
| CN101783179A (en) * | 2010-01-28 | 2010-07-21 | 上海宏力半导体制造有限公司 | Erasing method for improving durability of grid-split flash memory |
| CN101853704A (en) * | 2010-05-28 | 2010-10-06 | 上海宏力半导体制造有限公司 | Erasing method of split-gate flash memory of shared word line |
| CN103345939A (en) * | 2013-06-26 | 2013-10-09 | 上海宏力半导体制造有限公司 | Method for erasing split gate type flash memory |
| CN104575614A (en) * | 2015-02-10 | 2015-04-29 | 武汉新芯集成电路制造有限公司 | Invalid screening method of memory units |
| US20170032846A1 (en) * | 2005-05-20 | 2017-02-02 | Silicon Storage Technology, Inc. | Split Gate NAND Flash Memory Structure And Array, Method Of Programming, Erasing And Reading Thereof, And Method Of Manufacturing |
-
2017
- 2017-07-05 CN CN201710543541.2A patent/CN107331419A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170032846A1 (en) * | 2005-05-20 | 2017-02-02 | Silicon Storage Technology, Inc. | Split Gate NAND Flash Memory Structure And Array, Method Of Programming, Erasing And Reading Thereof, And Method Of Manufacturing |
| CN101783179A (en) * | 2010-01-28 | 2010-07-21 | 上海宏力半导体制造有限公司 | Erasing method for improving durability of grid-split flash memory |
| CN101853704A (en) * | 2010-05-28 | 2010-10-06 | 上海宏力半导体制造有限公司 | Erasing method of split-gate flash memory of shared word line |
| CN103345939A (en) * | 2013-06-26 | 2013-10-09 | 上海宏力半导体制造有限公司 | Method for erasing split gate type flash memory |
| CN104575614A (en) * | 2015-02-10 | 2015-04-29 | 武汉新芯集成电路制造有限公司 | Invalid screening method of memory units |
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| 董国生: "闪存存储器的浮栅耦合电位研究", 《中国科技论文在线》 * |
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Application publication date: 20171107 |