WO2015149670A1 - Manufacturing method for nor flash memory - Google Patents

Manufacturing method for nor flash memory Download PDF

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WO2015149670A1
WO2015149670A1 PCT/CN2015/075442 CN2015075442W WO2015149670A1 WO 2015149670 A1 WO2015149670 A1 WO 2015149670A1 CN 2015075442 W CN2015075442 W CN 2015075442W WO 2015149670 A1 WO2015149670 A1 WO 2015149670A1
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shallow trench
flash memory
floating gate
trench isolation
substrate
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PCT/CN2015/075442
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French (fr)
Chinese (zh)
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周俊
黄建冬
洪齐元
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武汉新芯集成电路制造有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a method for fabricating a NOR flash memory that optimizes a gate coupling coefficient.
  • a semiconductor memory for storing data is classified into a volatile memory and a nonvolatile memory, and the volatile memory is easy to lose data when the power is turned off, and the nonvolatile memory can hold the data even when the power is interrupted. . Therefore, non-volatile memory has become the most important storage component in portable electronic devices and has been widely used.
  • FIG. 1 is a schematic structural diagram of a NOR flash memory in the prior art.
  • a substrate 10, shallow trench isolation (STI) 11, floating gate 12, ONO layer 13, and control gate 14 are included.
  • the gate coupling coefficient of the NOR flash memory is a relatively important parameter, which mainly depends on the capacitance between the control gate 14 and the floating gate 12.
  • the size of the capacitance between the control gate 14 and the floating gate 12 depends mainly on the thickness of the ONO layer 13, the dielectric constant, and the package area of the control gate 14 and the floating gate 12.
  • the thickness uniformity and dielectric constant of the ONO layer 13 are mainly determined by the process stability of the ONO layer 13, and the existing furnace tube process has matured. Therefore, in order to optimize the gate coupling coefficient, it is necessary to improve the uniformity of the wrapping area of the control gate 14 and the floating gate 12.
  • the wrapping area of the control gate and the floating gate is mainly determined by the surface area and steps of the floating gate 12.
  • Covering height A constitutes.
  • the surface area of the floating gate is determined by photolithography and etching process, and whether the stability of the step coverage height A can be ensured directly limits the advantages and disadvantages of the gate coupling coefficient.
  • the present invention provides a method for manufacturing a NOR flash memory, including:
  • Providing a front end structure comprising a shallow trench isolation and a patterned floating gate
  • An ONO layer and a control gate are formed.
  • the dry etching includes etching using CH 2 F 2 .
  • the front end structure further includes a substrate, the shallow trench isolation portion is located in the substrate, and the floating gate is located between adjacent shallow trench isolations on the substrate .
  • the patterned floating gate forming process includes:
  • the planarization process is a chemical mechanical polishing process.
  • a tunnel oxide layer is further included between the floating gate and the substrate.
  • the method for fabricating a NOR flash memory includes etching the shallow trench isolation by a dry etching process, and then growing the ONO layer and the control gate.
  • the wet etching process is avoided to cause the layer-to-layer gap to be laterally etched to destroy the overall topography, thereby enabling a better shallow trench isolation structure and solving the gate coupling coefficient. Poor question.
  • FIG. 1 is a schematic diagram of a prior art NOR flash memory
  • FIG. 2 is a flowchart of a method of manufacturing a NOR flash memory according to an embodiment of the present invention
  • FIG. 3 to FIG. 5 are schematic diagrams showing the structure of a device in a process of manufacturing a NOR flash memory according to an embodiment of the present invention.
  • the STI re-etching method uses a wet etching process. Before the wet process is carried out, the surface of the wafer is flat and consists of floating gate polysilicon and shallow trench isolation. However, the stress existing between the floating gate polysilicon and the shallow trench isolation causes a gap between the two layers of media, while the wet process is characterized by isotropic etching and lateral etching along the gap to destroy the overall morphology. The stability of the step coverage height is poor. Therefore, the inventors believe that switching to a dry etching process will solve this problem.
  • FIG. 2 is a flowchart of a method for manufacturing a NOR flash memory according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a device in a process of manufacturing a NOR flash memory according to an embodiment of the present invention.
  • the manufacturing method of the NOR flash memory of this embodiment includes:
  • Step S101 providing a front end structure, the front end structure includes a shallow trench isolation 21 and a patterned floating gate 22; specifically, first, a substrate 20 is provided, and the constituent material of the substrate 20 may be an undoped single crystal Silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), and the like.
  • the substrate 20 is made of a single crystal silicon material.
  • a buried layer (not shown) or the like may also be formed in the substrate 20. Shallow trenches are then etched into the substrate 20 and shallow trench isolations 21 are formed by filling the oxide.
  • Floating gate polysilicon is then deposited over substrate 20 such that the floating gate polysilicon fills between adjacent shallow trench isolations 21 and the floating gate polysilicon is higher than the shallow trench isolations 21. Then, using a planarization process, for example, a chemical mechanical polishing process may be used to planarize the portion located above the shallow trench isolation 21 to obtain a patterned Floating gate 22. Preferably, a tunnel oxide layer 24 is formed between the floating gate 22 and the substrate 20.
  • a planarization process for example, a chemical mechanical polishing process may be used to planarize the portion located above the shallow trench isolation 21 to obtain a patterned Floating gate 22.
  • a tunnel oxide layer 24 is formed between the floating gate 22 and the substrate 20.
  • the formation of the front end structure described above is not limited to the described process, and can be flexibly changed depending on the process requirements.
  • Step S102 is performed.
  • the shallow trench isolation 21 is etched back by a dry etching process to remove a portion located between the floating gates 22; preferably, an engraving including CH 2 F 2 may be employed.
  • the etching gas is etched.
  • the dry etching process can effectively prevent the damage caused by the etching solution penetrating into the gap during the wet etching process, thereby avoiding lateral over-etching, thereby obtaining a good morphology after etching, thereby Finally, the purpose of optimizing the gate coupling coefficient is achieved.
  • step S103 is performed to form an ONO layer and a control gate.
  • the coverage of the ONO layer 23 is schematically illustrated in Figure 5.
  • the formation of the ONO layer and the formation of the control gate can be accomplished using any of the processes currently known.
  • the stability of the step coverage height after completion of the ONO layer eg, the height at different locations on the same shallow trench isolation
  • the height between different shallow trench isolations and even the difference in step coverage height between different NOR devices in a series of products can be effectively guaranteed, thereby optimizing the gate coupling coefficient.

Abstract

A manufacturing method for a NOR flash memory. The method comprises: providing a front-end structure, the front-end structure including a shallow trench isolation (21) and patterned floating gates (22); etching back the shallow trench isolation (21) with dry etching process, removing the part between the floating gates (22); forming an ONO layer (23) and a control gate. By the use of dry etching, lateral over-etching during etch-back process is avoided, so that the shallow trench isolation with better appearance is obtained and the gate coupling coefficient is optimized.

Description

NOR闪存的制造方法NOR flash memory manufacturing method 技术领域Technical field
本发明涉及半导体技术领域，特别是涉及一种优化栅耦合系数的NOR闪存的制造方法。The present invention relates to the field of semiconductor technology, and in particular to a method for fabricating a NOR flash memory that optimizes a gate coupling coefficient.
背景技术Background technique
随着便携式电子设备的高速发展，对数据存储的要求越来越高。通常，用于存储数据的半导体存储器分为易失性存储器和非易失性存储器，易失性存储器易于在电源断电时丢失数据，而非易失性存储器即使在电源中断时仍可保持数据。因此，非易失性存储器成为便携式电子设备中最主要的存储部件，并已经被广泛的应用。With the rapid development of portable electronic devices, the requirements for data storage are getting higher and higher. Generally, a semiconductor memory for storing data is classified into a volatile memory and a nonvolatile memory, and the volatile memory is easy to lose data when the power is turned off, and the nonvolatile memory can hold the data even when the power is interrupted. . Therefore, non-volatile memory has become the most important storage component in portable electronic devices and has been widely used.
在非易失性存储器中，闪存(flash memory)由于其很高的芯片存储密度，以及较佳的工艺适应性，已经成为一种极为重要的器件。通常闪存可以分为NAND闪存和NOR闪存。如图1所示为现有技术中的NOR闪存的结构示意图。包括衬底10，浅沟槽隔离(STI)11，浮栅12、ONO层13及控制栅14。In non-volatile memory, flash memory has become an extremely important device due to its high chip storage density and better process adaptability. Usually flash memory can be divided into NAND flash and NOR flash. FIG. 1 is a schematic structural diagram of a NOR flash memory in the prior art. A substrate 10, shallow trench isolation (STI) 11, floating gate 12, ONO layer 13, and control gate 14 are included.
NOR闪存的栅耦合系数是一个较为重要的参数，其主要取决于控制栅14和浮栅12之间的电容，电容越大，栅耦合系数越大，反之亦然。而控制栅14和浮栅12之间的电容大小，主要取决于ONO层13的厚度、介电常数以及控制栅14和浮栅12的包裹面积。目前，ONO层13的厚度均匀性和介电常数主要有ONO层13的工艺稳定性决定，现有炉管工艺已经成熟。因此，为了优化栅耦合系数，就需要对控制栅14和浮栅12的包裹面积的均匀性加以改善。The gate coupling coefficient of the NOR flash memory is a relatively important parameter, which mainly depends on the capacitance between the control gate 14 and the floating gate 12. The larger the capacitance, the larger the gate coupling coefficient, and vice versa. The size of the capacitance between the control gate 14 and the floating gate 12 depends mainly on the thickness of the ONO layer 13, the dielectric constant, and the package area of the control gate 14 and the floating gate 12. At present, the thickness uniformity and dielectric constant of the ONO layer 13 are mainly determined by the process stability of the ONO layer 13, and the existing furnace tube process has matured. Therefore, in order to optimize the gate coupling coefficient, it is necessary to improve the uniformity of the wrapping area of the control gate 14 and the floating gate 12.
如图1所示，控制栅和浮栅的包裹面积主要由浮栅12的表面积和台阶 覆盖高度A构成。浮栅的表面积由光刻和蚀刻工艺决定，而台阶覆盖高度A的稳定性是否能够得到保证，就直接制约着栅耦合系数的优劣。As shown in FIG. 1, the wrapping area of the control gate and the floating gate is mainly determined by the surface area and steps of the floating gate 12. Covering height A constitutes. The surface area of the floating gate is determined by photolithography and etching process, and whether the stability of the step coverage height A can be ensured directly limits the advantages and disadvantages of the gate coupling coefficient.
发明内容Summary of the invention
本发明的目的在于，提供一种NOR闪存的制造方法，改善台阶覆盖高度的稳定性，优化栅耦合系数。It is an object of the present invention to provide a method of fabricating a NOR flash memory that improves the stability of the step coverage height and optimizes the gate coupling coefficient.
为解决上述技术问题，本发明提供一种NOR闪存的制造方法，包括：To solve the above technical problem, the present invention provides a method for manufacturing a NOR flash memory, including:
提供前端结构，所述前端结构包括浅沟槽隔离和图形化的浮栅；Providing a front end structure comprising a shallow trench isolation and a patterned floating gate;
利用干法刻蚀工艺对所述浅沟槽隔离进行回刻，去除位于浮栅之间的部分；Replacing the shallow trench isolation by a dry etching process to remove a portion between the floating gates;
形成ONO层及控制栅。An ONO layer and a control gate are formed.
进一步的，对于所述的NOR闪存的制造方法，所述干法刻蚀包括利用CH2F2进行刻蚀。Further, for the manufacturing method of the NOR flash memory, the dry etching includes etching using CH 2 F 2 .
进一步的，对于所述的NOR闪存的制造方法，所述前端结构还包括衬底，所述浅沟槽隔离部分位于衬底中，所述浮栅位于衬底上相邻浅沟槽隔离之间。Further, in the method of fabricating the NOR flash memory, the front end structure further includes a substrate, the shallow trench isolation portion is located in the substrate, and the floating gate is located between adjacent shallow trench isolations on the substrate .
进一步的，对于所述的NOR闪存的制造方法，所述图形化的浮栅形成过程包括：Further, for the manufacturing method of the NOR flash memory, the patterned floating gate forming process includes:
在所述衬底上的浅沟槽隔离之间沉积浮栅多晶硅，所述浮栅多晶硅高于所述浅沟槽隔离；Depositing floating gate polysilicon between shallow trench isolations on the substrate, the floating gate polysilicon being higher than the shallow trench isolation;
利用平坦化工艺去除所Use a flattening process to remove
述浮栅多晶硅位于浅沟槽隔离之上的部分。The portion of the floating gate polysilicon that is above the shallow trench isolation.
进一步的，对于所述的NOR闪存的制造方法，所述平坦化工艺为采用化学机械研磨工艺。Further, for the manufacturing method of the NOR flash memory, the planarization process is a chemical mechanical polishing process.
进一步的，对于所述的NOR闪存的制造方法，所述浮栅与衬底之间还包括一隧道氧化层。 Further, for the manufacturing method of the NOR flash memory, a tunnel oxide layer is further included between the floating gate and the substrate.
与现有技术相比，本发明提供的NOR闪存的制造方法中，包括利用干法刻蚀工艺对所述浅沟槽隔离进行回刻，然后生长ONO层和控制栅。相比现有技术，避免了利用湿法刻蚀工艺使得层与层的缝隙间被侧向刻蚀而破坏整体形貌，从而能够具有较佳的浅沟槽隔离结构，解决了栅耦合系数较差的问题。Compared with the prior art, the method for fabricating a NOR flash memory provided by the present invention includes etching the shallow trench isolation by a dry etching process, and then growing the ONO layer and the control gate. Compared with the prior art, the wet etching process is avoided to cause the layer-to-layer gap to be laterally etched to destroy the overall topography, thereby enabling a better shallow trench isolation structure and solving the gate coupling coefficient. Poor question.
附图说明DRAWINGS
图1为一种现有技术中NOR闪存的示意图；1 is a schematic diagram of a prior art NOR flash memory;
图2为本发明实施例NOR闪存的制造方法的流程图；2 is a flowchart of a method of manufacturing a NOR flash memory according to an embodiment of the present invention;
图3-图5为本发明实施例NOR闪存的制造方法的过程中器件结构示意图。3 to FIG. 5 are schematic diagrams showing the structure of a device in a process of manufacturing a NOR flash memory according to an embodiment of the present invention.
具体实施方式detailed description
下面将结合示意图对本发明的NOR闪存的制造方法进行更详细的描述，其中表示了本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。The method for fabricating the NOR flash memory of the present invention will now be described in more detail with reference to the accompanying drawings, wherein the preferred embodiments of the present invention are illustrated, and it will be understood that those skilled in the art can modify the invention described herein. effect. Therefore, the following description is to be understood as a broad understanding of the invention.
为了清楚，不描述实际实施例的全部特征。在下列描述中，不详细描述公知的功能和结构，因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中，必须做出大量实施细节以实现开发者的特定目标，例如按照有关系统或有关商业的限制，由一个实施例改变为另一个实施例。另外，应当认为这种开发工作可能是复杂和耗费时间的，但是对于本领域技术人员来说仅仅是常规工作。In the interest of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail, as they may obscure the invention in unnecessary detail. It should be understood that in the development of any actual embodiment, a large number of implementation details must be made to achieve a particular goal of the developer, such as changing from one embodiment to another in accordance with the limitations of the system or related business. Additionally, such development work should be considered complex and time consuming, but is only routine work for those skilled in the art.
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明 本发明实施例的目的。The invention is more specifically described in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the description and appended claims. It should be noted that the drawings are in a very simplified form and all use non-precision proportions, only for convenient and clear explanation. The purpose of the embodiments of the present invention.
本发明的核心思想在于，发明人在长期工作中发现，现有技术中获得的栅耦合系数不能够令人满意。经过深入分析发现，是由于台阶覆盖高度的稳定性较差，目前对STI的回刻都采用的是湿法刻蚀工艺。而在进行这步湿法工艺之前，晶圆表面是平整的，由浮栅多晶硅和浅沟槽隔离构成。但是浮栅多晶硅和浅沟槽隔离之间存在的应力导致这两层介质之间有缝隙，而湿法工艺的特点是各向同性蚀刻，并且会顺着缝隙不断侧向蚀刻而破坏整体形貌，导致台阶覆盖高度的稳定性很差。因此，发明人认为，改用干法刻蚀工艺，将能够解决这一问题。The core idea of the present invention is that the inventors have found in the long-term work that the gate coupling coefficient obtained in the prior art is not satisfactory. After in-depth analysis, it is found that the stability of the step coverage height is poor. At present, the STI re-etching method uses a wet etching process. Before the wet process is carried out, the surface of the wafer is flat and consists of floating gate polysilicon and shallow trench isolation. However, the stress existing between the floating gate polysilicon and the shallow trench isolation causes a gap between the two layers of media, while the wet process is characterized by isotropic etching and lateral etching along the gap to destroy the overall morphology. The stability of the step coverage height is poor. Therefore, the inventors believe that switching to a dry etching process will solve this problem.
以下列举所述NOR闪存的制造方法的较优实施例，以清楚说明本发明的内容，应当明确的是，本发明的内容并不限制于以下实施例，其他通过本领域普通技术人员的常规技术手段的改进亦在本发明的思想范围之内。The preferred embodiments of the manufacturing method of the NOR flash memory are listed below to clearly illustrate the contents of the present invention. It should be clarified that the content of the present invention is not limited to the following embodiments, and other conventional techniques are known to those skilled in the art. Improvements in the means are also within the scope of the inventive idea.
基于上述思想，下面提供所述NOR闪存的制造方法的较优实施例，请参考图2及图3-图5，图2为本发明实施例NOR闪存的制造方法的流程图，图3-图5为本发明实施例NOR闪存的制造方法的过程中器件结构示意图。本实施例的NOR闪存的制造方法包括：Based on the above idea, a preferred embodiment of the manufacturing method of the NOR flash memory is provided below. Please refer to FIG. 2 and FIG. 3 to FIG. 5. FIG. 2 is a flowchart of a method for manufacturing a NOR flash memory according to an embodiment of the present invention, and FIG. 5 is a schematic structural diagram of a device in a process of manufacturing a NOR flash memory according to an embodiment of the present invention. The manufacturing method of the NOR flash memory of this embodiment includes:
步骤S101：提供前端结构，所述前端结构包括浅沟槽隔离21和图形化的浮栅22；具体的，首先提供衬底20，所述衬底20的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)等。作为示例，在本实施例中，所述衬底20选用单晶硅材料构成。在所述衬底20中还可以形成有埋层(图中未示出)等。然后在衬底20上刻蚀出浅沟槽，并通过填充氧化物形成浅沟槽隔离21。接着在衬底20上沉积浮栅多晶硅，使得所述浮栅多晶硅充满相邻浅沟槽隔离21之间，且所述浮栅多晶硅高于所述浅沟槽隔离21。之后利用平坦化工艺，例如可以是采用化学机械研磨工艺，进行平坦化，去除位于所述浅沟槽隔离21之上的部分，从而获得图形化的 浮栅22。较佳的，在浮栅22与衬底20之间还形成有一隧道氧化层(tunnel oxide layer)24。当然，上述前端结构的形成并不限于所述的过程，可以视工艺需要灵活变动。Step S101: providing a front end structure, the front end structure includes a shallow trench isolation 21 and a patterned floating gate 22; specifically, first, a substrate 20 is provided, and the constituent material of the substrate 20 may be an undoped single crystal Silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), and the like. As an example, in the present embodiment, the substrate 20 is made of a single crystal silicon material. A buried layer (not shown) or the like may also be formed in the substrate 20. Shallow trenches are then etched into the substrate 20 and shallow trench isolations 21 are formed by filling the oxide. Floating gate polysilicon is then deposited over substrate 20 such that the floating gate polysilicon fills between adjacent shallow trench isolations 21 and the floating gate polysilicon is higher than the shallow trench isolations 21. Then, using a planarization process, for example, a chemical mechanical polishing process may be used to planarize the portion located above the shallow trench isolation 21 to obtain a patterned Floating gate 22. Preferably, a tunnel oxide layer 24 is formed between the floating gate 22 and the substrate 20. Of course, the formation of the front end structure described above is not limited to the described process, and can be flexibly changed depending on the process requirements.
进行步骤S102：请结合图4，利用干法刻蚀工艺对所述浅沟槽隔离21进行回刻，去除位于浮栅22之间的部分；优选的，可以采用包括有CH2F2的刻蚀气体进行刻蚀。采用干法刻蚀工艺，能够有效的防止湿法刻蚀过程中刻蚀液渗入缝隙中造成的破坏，避免了侧向的过度刻蚀，因此能够在刻蚀后获得较好的形貌，从而最终达到优化栅耦合系数的目的。Step S102 is performed. Referring to FIG. 4, the shallow trench isolation 21 is etched back by a dry etching process to remove a portion located between the floating gates 22; preferably, an engraving including CH 2 F 2 may be employed. The etching gas is etched. The dry etching process can effectively prevent the damage caused by the etching solution penetrating into the gap during the wet etching process, thereby avoiding lateral over-etching, thereby obtaining a good morphology after etching, thereby Finally, the purpose of optimizing the gate coupling coefficient is achieved.
之后，进行步骤S103：形成ONO层及控制栅。图5中示意性的示出了ONO层23的覆盖，在本发明中，ONO层的形成及控制栅的形成可以采用目前已知的任何工艺流程完成。基于在步骤S102中的干法刻蚀形成的较佳的浅沟槽隔离的形貌，在完成ONO层后，台阶覆盖高度的稳定性(例如在同一浅沟槽隔离上的不同位置处的高度、不同浅沟槽隔离之间的高度乃至一系列产品中不同NOR器件之间的台阶覆盖高度之间的差异)能够得到有效的保证，从而优化了栅耦合系数。Thereafter, step S103 is performed to form an ONO layer and a control gate. The coverage of the ONO layer 23 is schematically illustrated in Figure 5. In the present invention, the formation of the ONO layer and the formation of the control gate can be accomplished using any of the processes currently known. Based on the preferred shallow trench isolation topography formed by the dry etch in step S102, the stability of the step coverage height after completion of the ONO layer (eg, the height at different locations on the same shallow trench isolation) The height between different shallow trench isolations and even the difference in step coverage height between different NOR devices in a series of products can be effectively guaranteed, thereby optimizing the gate coupling coefficient.
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。 It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention

Claims (6)

  1. 一种NOR闪存的制造方法，包括：A method of manufacturing a NOR flash memory, comprising:
    提供前端结构，所述前端结构包括浅沟槽隔离和图形化的浮栅；Providing a front end structure comprising a shallow trench isolation and a patterned floating gate;
    利用干法刻蚀工艺对所述浅沟槽隔离进行回刻，去除位于浮栅之间的部分；Replacing the shallow trench isolation by a dry etching process to remove a portion between the floating gates;
    形成ONO层及控制栅。An ONO layer and a control gate are formed.
  2. 如权利要求1所述的NOR闪存的制造方法，其特征在于，所述干法刻蚀包括利用CH2F2进行刻蚀。A method of fabricating a NOR flash memory according to claim 1, wherein said dry etching comprises etching with CH 2 F 2 .
  3. 如权利要求2所述的NOR闪存的制造方法，其特征在于，所述前端结构还包括衬底，所述浅沟槽隔离部分位于衬底中，所述浮栅位于衬底上相邻浅沟槽隔离之间。The method of fabricating a NOR flash memory according to claim 2, wherein the front end structure further comprises a substrate, the shallow trench isolation portion is located in the substrate, and the floating gate is located on the adjacent shallow trench on the substrate Slot isolation between.
  4. 如权利要求3所述的NOR闪存的制造方法，其特征在于，所述图形化的浮栅形成过程包括：The method of fabricating a NOR flash memory according to claim 3, wherein the patterned floating gate formation process comprises:
    在所述衬底上的浅沟槽隔离之间沉积浮栅多晶硅，所述浮栅多晶硅高于所述浅沟槽隔离；Depositing floating gate polysilicon between shallow trench isolations on the substrate, the floating gate polysilicon being higher than the shallow trench isolation;
    利用平坦化工艺去除所述浮栅多晶硅位于浅沟槽隔离之上的部分。A portion of the floating gate polysilicon above the shallow trench isolation is removed using a planarization process.
  5. 如权利要求4所述的NOR闪存的制造方法，其特征在于，所述平坦化工艺为采用化学机械研磨工艺。The method of manufacturing a NOR flash memory according to claim 4, wherein the planarization process is a chemical mechanical polishing process.
  6. 如权利要求3所述的NOR闪存的制造方法，其特征在于，所述浮栅与衬底之间还包括一隧道氧化层。 The method of fabricating a NOR flash memory according to claim 3, further comprising a tunnel oxide layer between the floating gate and the substrate.
PCT/CN2015/075442 2014-04-04 2015-03-31 Manufacturing method for nor flash memory WO2015149670A1 (en)

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