KR20060080457A - Non-volatile memory cells having floating gate and method of forming the same - Google Patents

Abstract

Provided are nonvolatile memory cells having a floating gate and a method of forming the same. In this method, after forming mask patterns defining active regions on a semiconductor substrate and forming the isolation trenches defining the active regions by anisotropically etching the semiconductor substrate using this as an etching mask, the device filling the isolation trenches is then formed. Forming separator patterns. Thereafter, mask patterns are selectively removed to form gate trenches that expose the top surface of the active region, a gate insulating layer is formed on the active region to be exposed, and a floating gate electrode is formed on the gate insulating layer to fill the gate trenches. . In this case, the forming of the gate insulating film may include forming the gate insulating film to be thinner at the edge than the center portion of the active region.

Description

Non-Volatile Memory Cells Having Floating Gate And Method Of Forming The Same

1 is a cross-sectional view illustrating a unit cell of a general flash memory device.

FIG. 2 is an energy band diagram during program operation of a flash memory cell taken along the line II ′ of FIG. 1.

3 to 5 are cross-sectional views illustrating processes of nonvolatile memory cells according to exemplary embodiments of the present invention.

6 is a diagram showing a result of simulating the distribution of current density flowing through the gate insulating film to explain the technical effect according to the present invention.

FIG. 7 is a diagram illustrating a result of simulating electric field strength in a cross section taken along line II ′ of FIG. 6.

FIG. 8 is a diagram showing a result of simulating the magnitude of the tunneling current in the cross section of II-II 'of FIG.

9 is an energy band diagram in cross section of II ′ of FIG. 6, prepared for explaining the program operation of a nonvolatile memory cell according to the present invention.

10 through 16 are cross-sectional views illustrating a method of manufacturing nonvolatile memory cells in accordance with an embodiment of the present invention.

TECHNICAL FIELD The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to nonvolatile memory cells having a floating gate and a method of forming the same.

Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. A volatile memory device is a memory device that loses all stored data when a power supply is interrupted. For example, a DRAM device and an SRAM device are included. In contrast, a nonvolatile memory device includes a memory device such as a flash memory device that retains data stored in a memory cell even when power supply is interrupted.

FIG. 1 is a cross-sectional view illustrating a unit cell of a general flash memory device, and FIG. 2 is an energy band diagram during a program operation of a flash memory cell taken along line II ′ of FIG. 1.

1 and 2, a gate pattern 6 including a tunnel oxide film 2, a floating gate 3, a gate interlayer insulating film 4, and a control gate electrode 5 sequentially stacked on the semiconductor substrate 1. ) Is placed. Impurity diffusion layers 7 are formed in active regions on both sides of the gate pattern 6, respectively. The impurity diffusion layer 7 corresponds to a source / drain region. The semiconductor substrate 1 under the gate pattern 6 corresponds to the channel region 8. The floating gate 3 is electrically isolated as a place for storing charge. The control gate electrode 5 is responsible for a program operation or an erase operation. The program operation includes applying a program voltage to the control gate electrode 5 and applying a reference voltage to the semiconductor substrate 1 to tunnel the charges in the semiconductor substrate 1 by tunneling the tunnel oxide film 2 to the floating. The operation of flowing into the gate 3 is referred to. In contrast, the erase operation may be performed by applying an erase voltage to the control gate electrode 5 and applying a reference voltage to the semiconductor substrate 1 to transfer charges stored in the floating gate 3 to the semiconductor substrate 1. It refers to the action of emitting. Typically, the program voltage and erase voltage are higher than the power supply voltage.

In the above-described flash memory cell, the charges tunnel the tunnel oxide layer 2 using a Fowler-Nordheim tunneling method (hereinafter referred to as FN tunneling). At this time, charges tunnel the tunnel oxide film 2 over the channel region 8. The manner in which charges, ie electrons and holes, tunnel the tunnel oxide film 2 will be described with reference to the energy band diagram of FIG.

In a program operation of writing data into the flash memory cell, a program voltage is applied to the control gate electrode 5 and a reference voltage is applied to the semiconductor substrate 1. The source / drain regions 7 may be suspended. In this case, the program voltage is higher than the reference voltage. Accordingly, the energy band of the tunnel oxide film 2 is inclined so that the upper and lower energy band widths become thinner. As a result, electrons in the conduction band (Ec) of the channel region 8 are tunneled through the thinned upper energy band of the tunnel oxide film 2 into the floating gate 3 (A). The amount of FN tunneling electrons increases as the width 10 of the upper energy band becomes thinner. At this time, holes in the valence band (Ev) of the floating gate 3 move to the channel region 8 by FN tunneling the thinned lower energy band of the tunnel oxide film 2 (B). The amount of tunneling holes also increases as the width 11 of the lower energy band becomes thinner. The amount of tunneled holes is small compared to the amount of tunneled electrons. This is due to the effective mass of the holes being large compared to the effective mass of the electrons.

On the other hand, due to the trend toward high integration and low power consumption of semiconductor devices, reduction of the program voltage and the erase voltage is required. There is also a need for improved endurance for the flash memory device.

As the program and erase operations are repeated in the flash memory cell, durability may deteriorate. That is, interface traps may be formed at an interface of the tunnel oxide film 2 by charges tunneling the tunnel oxide film 2. Charges tunneling into the interface trap may be trapped, thereby degrading durability of the flash memory device. In particular, holes having a greater effective mass than electrons can have a greater impact on the generation of the interface traps.

In addition, as semiconductor devices become highly integrated, a conventional patterning process using a photoresist pattern as an etching mask has a technical problem that makes it difficult to accurately align the floating gate 3 on the active region. Correct alignment of the floating gate 3 is another technical challenge in the manufacturing process that must be ensured to increase the reliability of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide nonvolatile memory cells having floating gates capable of reducing program voltage or erase voltage and improving durability.

Another object of the present invention is to provide a method of forming a nonvolatile memory cell having a floating gate that can reduce a program voltage or an erase voltage and improve durability.

Another object of the present invention is to provide a method of forming a nonvolatile memory cell capable of correctly aligning a floating gate in an active region.

In order to achieve the above technical problem, the present invention provides a method of forming a nonvolatile memory cell comprising forming a floating gate electrode in a self-aligned manner. The method includes forming mask patterns defining active regions on a semiconductor substrate, forming device isolation trenches defining the active regions by anisotropically etching the semiconductor substrate using the mask patterns as an etch mask, and then forming the device isolation trenches defining the active regions. Forming device isolation layer patterns filling the isolation trenches. Thereafter, the mask patterns are selectively removed to form gate trenches that expose the top surface of the active region, a gate insulating layer is formed on the exposed active region, and then the floating trenches fill the gate trenches on the gate insulating layer. A gate electrode is formed. In this case, the forming of the gate insulating film may include forming the gate insulating film to be thinner at the edge of the active region than in the central portion of the active region.

In example embodiments, the removing of the mask patterns may be performed so that the upper sidewall of the active region is not exposed.

In the forming of the gate insulating layer, an oxidation reaction may be performed at an edge of the active region compared to a center portion of the active region by utilizing the effect that the upper sidewall of the active region is not exposed and the stress applied to the edge of the active region. Allow the reaction depth to be shallow.

In order to achieve the above technical problem, the present invention provides a non-volatile memory device having a gate insulating film having a thin edge. The device includes device isolation layer patterns formed in a predetermined region of a semiconductor substrate to define active regions, control gate electrodes crossing the active regions, floating gate electrodes disposed between the control gate electrode and the active region, and A gate interlayer insulating film disposed between a control gate electrode and the floating gate electrode, and a gate insulating film disposed between the floating gate electrode and the active region. In this case, the gate insulating layer is thinner at the edge of the active region than the central portion of the active region, and the floating gate electrodes are symmetrically disposed with respect to the active region below the gate insulating layer.                     

According to an embodiment of the present invention, an edge adjacent to the device isolation layer pattern protrudes upward from the center portion spaced apart from the device isolation layer pattern. According to another embodiment of the present invention, the floating gate electrodes protrude downward from the edge of the active region compared to the central portion of the active region disposed below it.

In addition, the floating gate electrodes may have a wider width than the active region disposed thereunder. In this case, the floating gate electrode is symmetrically disposed with respect to the active region disposed below the floating gate electrode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

3 to 5 are cross-sectional views illustrating processes of nonvolatile memory cells according to exemplary embodiments of the present invention.

3 to 5, device isolation layer patterns 125 defining active regions are disposed in a predetermined region of the semiconductor substrate 100. The device isolation layer patterns 125 fill the device isolation trenches 105 formed in the semiconductor substrate 100, and may include at least one selected from a silicon oxide layer, a silicon layer, a silicon germanium layer, or an SOG layer. Can be.

Control gate electrodes 170 may be disposed on the active region, and the floating gate electrodes 150 may be disposed between the control gate electrodes 170 and the active region. ) Is placed. In addition, gate insulating layers 140 may be disposed between the floating gate electrodes 150 and the active region, and gate interlayer insulating layers may be disposed between the floating gate electrodes 150 and the control gate electrodes 170. 160 is disposed.

The gate insulating layers 140 may be silicon oxide layers, and may be high dielectric layers such as aluminum oxide layers or hafnium oxide layers. The gate interlayer insulating layers 160 may be a silicon oxide film-silicon nitride film-silicon oxide film sequentially stacked. The floating gate electrodes 150 may be formed of a polycrystalline silicon film, and the control gate electrodes 170 may be formed of a polycrystalline silicon film and a silicide film that are sequentially stacked.

In example embodiments, the gate insulating layer 140 may be formed at an edge of the active region adjacent to the device isolation layer patterns 125 than at a center portion of the active region spaced apart from the device isolation layer pattern 125. It has a thin thickness. In addition, the floating gate electrodes 150 have a wider width than the active region below them. At this time, the first width d of the floating gate electrodes 150 disposed above the predetermined active region and protruding in one direction is the second width d of the protruding length in the opposite direction. same as d). That is, the floating gate electrodes 150 are symmetrically disposed with respect to the active region below them.

According to the first embodiment of the present invention, the shape of the active region is pointed upward at an edge thereof adjacent to the device isolation layer pattern 125 as compared with a central portion thereof separated from the device isolation layer pattern 125 (FIG. 3). Reference). According to the second embodiment of the present invention, the active region has a flat top surface, and the floating gate electrodes 150 have protrusions that are pointed downward from the edge (see FIG. 4). According to the third embodiment of the present invention, the active region, as described in the first embodiment, has not only a sharp edge upwards, but also the floating gate electrodes 150 as described in the second embodiment. It also has a sharp edge down (see FIG. 5). All of these embodiments disclose the gate insulating layers 140 having edges that are thinner than the center portion as described above.

6 to 8 are simulation results for explaining a technical effect obtained through the gate insulating layer 140 according to the present invention having a thin edge. More specifically, FIG. 6 is a simulation graph visually showing the spatial distribution of current density flowing through the gate insulating layer 140, and FIG. 7 is a simulation graph showing the electric field strength in the cross-section of II ′ of FIG. 6. 8 is a simulation graph showing the magnitude of the tunneling current in the cross section of II-II 'of FIG. 6. In the graph of FIG. 7, the x-axis represents the position along the cutting plane of II ′ in FIG. 6, and the y-axis represents the three forces of the electric field. In the graph of FIG. 8, the x axis represents a position along the cut plane of II-II ′ of FIG. 6, and the y axis represents the magnitude of the FN tunneling current.

6 to 8, 10 V is applied to the floating gate electrode 150, and 0 V (ground voltage) is applied to the semiconductor substrate 100. Impurity regions formed on both sides of the floating gate electrode 150 are floated.

In this case, as shown in FIG. 7, the intensity of the electric field increases from the floating gate electrode 150 to the end of the active region protrusion 99. That is, the electric field strength at the end of the active region protrusion 99 increases approximately 1.6 times with respect to the interface between the floating gate electrode 150 and the gate insulating layer 140. As a result, it can be seen that the electric field is concentrated at the end of the active region protrusion 99, thereby increasing the intensity of the electric field. Due to this increased intensity of the electric field, the magnitude of the current tunneled at the end of the active region protrusion 99 increases compared to the central portion of the active region.

8 shows the positional difference in the magnitude of this FN tunneling current. 8 shows the magnitude of the FN tunneling current according to the position as a ratio of the magnitude of the current tunneled at the center of the active region. The y-axis of FIG. 8 is represented by a log scale. Referring to FIG. 8, the magnitude of the FN tunneling current tunneling the active region protrusion 99 is about 10,000 times greater than the amount of FN tunneling current at the center of the active region. In addition to the electric field concentration according to the above-described protrusion, the thickness of the gate insulating layer 140 positioned on the end of the active region protrusion 99 becomes thinner than the thickness of the gate insulating layer 140 positioned at the center of the active region. It is also the result of the effect. When the thickness of the gate insulating layer 140 is excluded, the amount of FN current at the end of the active region protrusion 99 is increased by about 1,000 times the amount of FN tunneling current at the center of the active region.

The intensity of the electric field applied to the end of the active region protrusion 99 increases not only in the above-described program operation but also in the erasing operation. Thus, the amount of electrons emitted from the floating gate electrode 150 to the active region is greater in the active region protrusion 99 than in the central portion of the active region. As a result, in the program or erase operation, the amount of electrons tunneling the gate insulating layer 140 is increased in comparison with a general flash memory cell. As a result, the nonvolatile memory cell can reduce a program or erase voltage as compared with a general nonvolatile memory cell.

Meanwhile, according to the present invention, the amount of holes for tunneling the gate insulating layer 140 can be reduced, which will be described with reference to the energy band diagram shown in FIG. 9.

9 is an energy band diagram in cross section of II ′ of FIG. 6, prepared for explaining the program operation of a nonvolatile memory cell according to the present invention.

9, in the program operation, the energy band of the gate insulating layer 140 is inclined. In this case, since the intensity of the applied electric field increases as the active region protrudes 99, the upper energy band width 201 of the gate insulating layer 140 is narrower than the upper energy band width 10 of FIG. 2. Lose. As a result, the amount of electrons tunneling the upper energy band width 201 from the conduction band Ec of the active region protrusion 99 increases.

In contrast, the lower energy band width 202 of the gate insulating layer 140 through which holes in the floating gate electrode 150 tunnel is wider than the lower width 11 of the energy band of FIG. 2. Accordingly, the number of holes tunneling the gate insulating layer 140 from the floating gate electrode 150 is reduced. As a result, the amount of holes tunneling the gate insulating layer 140 is reduced, so that the interface traps formed at the interface of the gate insulating layer 140 are reduced, so that durability of the nonvolatile memory cell can be improved.

10 through 16 are cross-sectional views illustrating a method of manufacturing nonvolatile memory cells in accordance with an embodiment of the present invention.

Referring to FIG. 10, trench mask patterns 110 defining active regions are formed on the semiconductor substrate 100. The trench mask patterns 110 may be formed of a material having an etch selectivity with respect to the semiconductor substrate 100. In some embodiments, the trench mask patterns 110 may be formed of a pad oxide film 112 and a silicon nitride film 114 that are sequentially stacked. The pad oxide layer 112 may be a silicon oxide layer to buffer stress that may occur when the silicon nitride layer 114 and the semiconductor substrate 100 directly contact each other.

The trench mask patterns 110 expose the upper surface of the semiconductor substrate 100 in a predetermined region. The exposed semiconductor substrate 100 is anisotropically etched using the trench mask patterns 110 as an etch mask. Accordingly, the exposed semiconductor substrate 100 between the trench mask patterns 110 is etched to form device isolation trenches 105 that define active regions. The active regions correspond to regions of the semiconductor substrate 100 covered by the trench mask patterns 110.

Referring to FIG. 11, a device isolation layer filling the device isolation trenches 105 is formed on the entire surface of the resultant device on which the device isolation trenches 105 are formed. The device isolation film is preferably a silicon oxide film formed using a chemical vapor deposition process. A polycrystalline silicon film, a silicon germanium film, an SOG film, or the like may be used.

Subsequently, the device isolation layer is planarized etched using chemical mechanical polishing (CMP) until the upper surfaces of the trench mask patterns 110 are exposed. As a result, device isolation layer patterns 120 may be formed to fill the device isolation trenches 105.

According to other embodiments of the present invention, a thermal oxide film (not shown) may be further formed on an inner wall of the device isolation trench 105 before the device isolation film is formed. The thermal oxide film heals the etch damage of the semiconductor substrate 100 that occurs during the formation of the isolation trench 105. In addition, a silicon nitride film liner (not shown) may be further formed on the entire surface of the resultant product on which the thermal oxide film is formed. The silicon nitride film liner prevents impurities impinging on the semiconductor substrate 100 from penetrating into the semiconductor substrate 100 in a subsequent process.

Referring to FIG. 12, the exposed trench mask patterns 110 are removed to form gate trenches 130 exposing the top surface of the active region. The forming of the gate trenches 130 may include removing the silicon nitride layer 114 to expose the pad oxide layer 112 and removing the exposed pad oxide layer 112 by wet etching. Include.

Removing the silicon nitride film 114 may be performed by a wet etching method using an etching recipe having an etching selectivity with respect to the silicon oxide film. Subsequently, the removing of the pad oxide layer 112 may be performed using an etching recipe capable of etching the silicon oxide layer while having an etch selectivity with respect to the semiconductor substrate 100, that is, having an etch selectivity with respect to the silicon layer. It is preferable.

According to the present invention, the step of removing the pad oxide layer 112 is preferably to strictly control the etch intermediate time so that the upper sidewall of the active region is not exposed. In addition, it is preferable that the width of the gate trench 130 is wider than the width of the active region disposed below it, but an embodiment narrower than the width of the active region is possible. As described above, since the trench mask patterns 110 are used as an etching mask for defining the active region, the gate trench 130 formed by isotropically etching them may be left or right with respect to the active region below them. It is arranged symmetrically.

Referring to FIG. 13, a gate insulating layer 140 is formed on an upper surface of the exposed active region. According to the present invention, the gate insulating layer 140 is preferably a silicon oxide film formed through a thermal oxidation process.

In this case, the device isolation layer pattern 120 covers the sidewall of the active region, and due to the stress applied to the upper edge of the active region, the thermal oxidation process is more active at the center portion thereof than at the edge of the active region. As a result, as shown, the gate insulating layer 140 is formed to a thickness thinner at the edge than in the center portion of the active region. That is, the active region has a protrusion 99 having a tapered shape at an edge adjacent to the device isolation layer pattern 120.

The protrusion 99 of the active region may be formed by recessing an upper surface of the active region by using spacers (not shown) formed on an inner sidewall of the gate trench 130 as a mask. That is, before the gate insulating layer 140 is formed, the spacers are formed on the inner wall of the gate trench 130, and the recesses are used to etch the active region to a predetermined depth using the spacers as etch masks. By removing the spacer, the protrusion 99 may be formed. Subsequently, when the thermal oxidation process is performed, the active region and the gate insulating layer 140 having the shape as shown may be formed.

Referring to FIG. 14, a floating gate conductive layer filling the gate trenches 130 is formed on the entire surface of the resultant in which the gate insulating layer 140 is formed. The floating gate conductive film is preferably a polycrystalline silicon film doped with impurities. The impurities doped in the floating gate conductive layer are preferably en-type impurities.

Thereafter, the floating gate conductive layer is planarized and etched until the upper surface of the device isolation layer pattern 120 is exposed. The planarization etching is preferably performed using a chemical mechanical polishing technique. Accordingly, the floating gate patterns 150 are formed by filling the gate trench 130 and separated by the device isolation layer patterns 120.

15 and 16, the device isolation layer patterns 120 may be etched using an etching recipe having an etch selectivity with respect to the floating gate patterns 150, thereby lowering the floating gate patterns 150. A recessed device isolation layer pattern 125 having an upper surface is formed. Subsequently, the gate interlayer insulating layer 160 and the control gate electrode 170 are sequentially formed on the resultant device on which the recessed device isolation layer patterns 125 are formed. The gate interlayer insulating film 160 may be a silicon oxide film-silicon nitride film-silicon oxide film that is sequentially stacked. The control gate electrode 170 may be patterned in a direction crossing the active regions, and may preferably have a structure in which a polycrystalline silicon film and silicide are sequentially stacked.

According to the present invention, the nonvolatile memory cell of the present invention includes a protrusion on which a bottom surface of the floating gate or a portion of an active region disposed below the floating gate protrudes. Since the electric field applied in the program or erase operation is concentrated by the protruding shape of the floating gate or the active region, the nonvolatile memory cell can be programmed or erased at a lower voltage.

In addition, the width of the lower energy band of the tunnel insulating layer is increased due to the concentrated electric field, thereby reducing the amount of holes tunneling the gate insulating layer. As a result, the interface trap charge can be reduced, and the durability of the nonvolatile memory cell can be improved.

The present invention also provides a method of aligning the floating gate electrode to the active region in a self-aligned manner. Accordingly, it is possible to prevent a decrease in reliability due to misalignment of the floating gate electrodes.

Claims (8)

Device isolation layer patterns formed in predetermined regions of the semiconductor substrate to define active regions; Control gate electrodes across the active regions; Floating gate electrodes disposed between the control gate electrode and the active region; A gate interlayer insulating film disposed between the control gate electrode and the floating gate electrode; And A gate insulating layer disposed between the floating gate electrode and the active region, The gate insulating layer is thinner at an edge of the active region than in a central portion of the active region, And the floating gate electrodes are symmetrically disposed with respect to an active region below the floating gate electrodes. The method of claim 1, The active region is a non-volatile memory device, characterized in that the edge adjacent to the device isolation layer pattern protrudes upward compared to the center portion spaced apart from the device isolation layer pattern. The method according to claim 1 or 2, And the floating gate electrodes protrude downward from an edge of the active region compared to a central portion of the active region disposed below the floating gate electrodes. The method of claim 1, And the floating gate electrodes have a width wider than an active region disposed under the floating gate electrodes. The method of claim 4, wherein And the floating gate electrode is symmetrically disposed with respect to an active region below the floating gate electrode. Forming mask patterns defining active regions on the semiconductor substrate; Anisotropically etching the semiconductor substrate using the mask patterns as an etch mask to form device isolation trenches defining the active regions; Forming device isolation layer patterns filling the device isolation trenches; Selectively removing the mask patterns to form gate trenches that expose an upper surface of the active region; Forming a gate insulating film on the exposed active region; And Forming a floating gate electrode filling the gate trenches on the gate insulating layer, The forming of the gate insulating film may include forming the gate insulating film to be thinner at an edge of the active region than in the center portion of the active region. The method of claim 6, The removing of the mask patterns may be performed so that the upper sidewall of the active region is not exposed. The method of claim 7, wherein The forming of the gate insulating layer may include the effect that the upper sidewall of the active region is not exposed and the stress applied to the edge of the active region so that the reaction depth of the oxidation reaction is shallower at the edge of the active region than at the center portion of the active region. Method for manufacturing a nonvolatile memory device, characterized in that the use.

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