CN107478977B - Method for extracting trap state density of oxide semiconductor thin film transistor - Google Patents
Method for extracting trap state density of oxide semiconductor thin film transistor Download PDFInfo
- Publication number
- CN107478977B CN107478977B CN201710571427.0A CN201710571427A CN107478977B CN 107478977 B CN107478977 B CN 107478977B CN 201710571427 A CN201710571427 A CN 201710571427A CN 107478977 B CN107478977 B CN 107478977B
- Authority
- CN
- China
- Prior art keywords
- thin film
- film transistor
- trap state
- threshold voltage
- oxide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 239000010409 thin film Substances 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000012546 transfer Methods 0.000 claims abstract description 23
- 230000007246 mechanism Effects 0.000 claims abstract description 12
- 230000008859 change Effects 0.000 claims abstract description 10
- 238000012360 testing method Methods 0.000 claims abstract description 8
- 238000004364 calculation method Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 6
- 238000005286 illumination Methods 0.000 claims description 4
- 239000006185 dispersion Substances 0.000 claims description 3
- 230000005516 deep trap Effects 0.000 claims description 2
- 239000000969 carrier Substances 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 238000000605 extraction Methods 0.000 abstract description 7
- 230000008569 process Effects 0.000 abstract description 4
- 239000000284 extract Substances 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000001727 in vivo Methods 0.000 description 4
- 230000005527 interface trap Effects 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000338 in vitro Methods 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 230000001795 light effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005325 percolation Methods 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2648—Characterising semiconductor materials
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention relates to a method for extracting trap state density of an oxide semiconductor thin film transistor, and belongs to the technical field of semiconductor devices. A method for extracting trap state density of an oxide semiconductor thin film transistor comprises the steps of extracting trap states at the interface of a semiconductor and a gate insulating layer and extracting trap states in the semiconductor. The invention mainly comprises the following steps: 1) applying forward bias stress for different durations to the oxide semiconductor thin film transistor, and testing a corresponding transfer characteristic curve; 2) analyzing a threshold voltage drift mechanism based on a change rule of the transfer characteristic, and determining a change relation of the threshold voltage drift along with time; 3) if the threshold voltage drift and the applied stress time meet the extension index model, extracting the characteristic temperature of a trap state in the semiconductor body; 4) and extracting the interface state density of the semiconductor and the gate insulating layer and the trap state density in the semiconductor by utilizing the relationship between the subthreshold swing and the trap state. The trap state density extraction method provided by the invention can simultaneously extract the trap state on the thin film transistor interface and the trap state in the thin film transistor, and has the advantages of simpler calculation process, less limiting conditions and wide application range compared with the existing method.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a trap state density extraction method for an oxide semiconductor thin film transistor.
Background
The oxide semiconductor thin film transistor has the advantages of high mobility, transparency, compatibility with an amorphous silicon low-temperature preparation process, flexible display, high uniformity in large-area manufacturing and the like, is greatly concerned, and is widely applied to logic gates, sensors and the like of AMLCDs (advanced organic light-emitting diodes), AMOLEDs (active matrix organic light-emitting diodes), ring oscillators.
trap states of the thin film transistor include semiconductor and gate insulating layer interface trap states and in-semiconductor trap states. Similar to the hydrogenated amorphous silicon thin film transistor, the oxide semiconductor thin film transistor also has more non-uniformly distributed band gap defect states, and the band gap states closely related to the preparation process have a decisive role in the electrical characteristics and the like of the oxide semiconductor thin film transistor. The extraction method for researching the trap state density of the oxide semiconductor thin film transistor is beneficial to better analyzing the performance of the device, understanding the degradation and failure mechanism of the device, improving the process of the device, providing a basis for circuit design and being beneficial to the generation of a circuit.
At present, the existing method for extracting the trap state density of the oxide semiconductor thin film transistor mainly comprises the following steps: 1) capacitance-voltage (C-V) method: this method requires a long time to test the quasi-static C-V characteristic to improve the signal-to-noise ratio, and the high frequency C-V is susceptible to gate leakage current. In addition, the C-V method requires knowledge of the flat band voltage at which the device operates. 2) Field effect (F-E) method: the method assumes that the conduction mechanism of the transistor is mainly trap state limited conduction, and the existence of the precondition makes the method difficult to extract the acceptor type trap state of the oxide semiconductor thin film transistor. Since the main conduction mechanism is percolation conduction when the carrier concentration is large to some extent for oxide semiconductor thin film transistors. 3) A photo capacitance method and a photon excited charge collection spectroscopy method for extracting trap states by utilizing a light effect. However, the material characteristics are changed by the illumination, so that the trap state distribution is changed. 4) The extraction is performed by using the mel-fresnel principle, but the flat band voltage and mel-fresnel factor of the transistor are known in advance, and moreover, the method can be used only in the case where the device operates in the sub-threshold region.
In summary, there is an urgent need to develop a method for extracting trap states of an oxide semiconductor thin film transistor, and with the wide application of the oxide semiconductor thin film transistor in practical electronic circuits, the need for a trap state extraction method with simple calculation and wide application range is more and more urgent in order to evaluate the device characteristics more quickly, conveniently and effectively.
Disclosure of Invention
The trap state density extraction method is simpler in calculation process than the existing method, can simultaneously extract the interface trap state and the internal trap state distribution, and can be used for extracting the trap state of the oxide semiconductor thin film transistor with a single gate and a double gate.
The specific technical scheme of the invention is as follows: a method for extracting trap state density of an oxide semiconductor thin film transistor comprises the following steps:
1) Applying forward bias stress for different durations to the oxide semiconductor thin film transistor, and testing a corresponding transfer characteristic curve;
2) Analyzing a threshold voltage drift mechanism based on a change rule of the transfer characteristic, and determining a change relation of the threshold voltage drift along with time;
3) if the threshold voltage drift and the applied stress time meet the extension index model, extracting the characteristic temperature of a trap state in the semiconductor body;
4) And extracting the interface state density of the semiconductor and the gate insulating layer and the trap state density in the semiconductor by utilizing the relationship between the subthreshold swing and the trap state.
Furthermore, when the grid electrode is applied with forward bias stress for different time lengths without illumination, the transfer characteristic curve of the oxide semiconductor thin film transistor is or approximately moves in parallel, and the amplitude of the subthreshold swing is not obviously changed.
And analyzing a threshold voltage drift mechanism based on a transfer characteristic change rule. Under forward bias stress, the oxide semiconductor thin film transistor threshold voltage drift mechanism comprises:
1) Trapping electrons by trap states, including trapping of an interface state and a trap state in a body and trapping of a trap state of a gate insulating layer; in this case, the subthreshold swing of the thin film transistor is substantially unchanged; the gate bias voltage enables negative charges in the channel layer to be captured to enter the interface of the channel layer and the gate insulating layer or directly enter the gate insulating layer, so that part of the gate bias voltage is shielded, and the drift of the threshold voltage is caused; electrons at the interface of the gate insulating layer and the semiconductor can enter the gate insulating layer in two ways: 1) a trap state that tunnels directly from the semiconductor interface to the gate insulating layer; 2) entering a conduction band of the gate insulating layer from the semiconductor interface through Fowler-Nordheim tunneling, then being trapped by a deep trap state of the gate insulating layer close to the semiconductor interface, and carrying out charge redistribution; if the electrons captured by the trap of the gate insulating layer are not redistributed, the threshold voltage drift of the thin film transistor and the applied stress time meet the exponential relationship; if the trapped charges are redistributed in the gate insulating layer, the expansion exponential relationship is met; generally, when a gate insulating layer of an oxide semiconductor thin film transistor is silicon dioxide, threshold voltage drift and applied stress time meet an extension index model;
2) And (4) generation of trap states. At this time, the threshold voltage shift of the thin film transistor is logarithmically related to the applied stress time.
Under forward bias stress, when the threshold voltage drift and the applied stress time of the oxide semiconductor thin film transistor satisfy the extended exponential model, the change relationship of the threshold voltage drift Δ Vth with the stress time t can be expressed as follows: Δ Vth ═ (Vgs-Vth0) {1-exp [ - (T/τ) β ] }, where Vgs is the gate-source voltage, Vth0 is the initial threshold voltage of the thin film transistor, τ is the characteristic time constant, β is the dispersion factor satisfied, Tt is the characteristic temperature of the trap state in the semiconductor body, and T is the operating temperature of the transistor; and extracting the characteristic temperature of the trap state in the semiconductor body by fitting a curve by using the relational expression.
The sub-threshold swing SS of the oxide semiconductor thin film transistor can be expressed as:
wherein q is basic charge, k is Boltzmann constant, Cox is unit area gate insulation layer capacitance, Dit is interface state density of semiconductor and gate insulation layer, ε 0 and ε s are vacuum dielectric constant and relative dielectric constant of semiconductor respectively, td and tch are depletion layer and channel layer thickness respectively, and NT is trap state density extrapolated to the bottom of the conduction band EC.
Wherein the parameter td can be expressed as
Where φ b is the difference between the semiconductor Fermi level EF and the intrinsic Fermi level Ei, and Nch is the channel carrier concentration.
The parameter Nch can be expressed as
where Von is the turn-on voltage of the oxide semiconductor thin film transistor and is defined as the gate-source voltage corresponding to the initial increase of the drain-source current in the transfer characteristic curve of the transistor. By combining the above equations, the interface state density Dit of the semiconductor and the gate insulating layer and the trap state density NT of the semiconductor at the bottom of the conduction band can be calculated.
Substituting the extracted characteristic temperature Tt of the trap state in the semiconductor body and the trap state density NT extrapolated to the bottom of the conduction band into the following formula to obtain the trap state density Nt in the semiconductor body
Wherein E is energy.
Compared with the prior art, the beneficial effects are: based on the relationship between threshold voltage drift and applied stress time under no illumination and forward bias stress and the relationship between sub-threshold swing and trap state density, the interface and in-vivo trap states of the thin film transistor are extracted, so that a foundation is laid for constructing physical models of current, mobility, parasitic resistance and the like of the oxide semiconductor thin film transistor, the method can be used for analyzing the degradation mechanism of the electrical performance of a device, and theoretical guidance is provided for evaluating the influence of the thin film transistor structure, the preparation process, the active layer and the gate insulating layer on the electrical performance of the device.
Drawings
FIG. 1 is a flow chart of a method for extracting trap state density of an oxide semiconductor thin film transistor according to the present invention. Fig. 2 is a schematic structural diagram of an indium zinc oxide thin film transistor (IZO TFT) sample in a first embodiment of the present invention.
FIG. 3 is a graph showing the transfer characteristics of IZO TFT samples under a positive bias stress in the first embodiment of the present invention.
FIG. 4 is a graph of the change of threshold voltage with time under forward bias stress for IZO TFT samples in the first embodiment of the present invention.
FIG. 5 is a graph showing the distribution of in vivo trap states of IZO TFT samples extracted in the first embodiment of the present invention.
Detailed Description
the drawings are for illustrative purposes only and are not to be construed as limiting the patent; for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the present patent.
Example one
The invention aims to provide a method for extracting trap state density of an oxide semiconductor thin film transistor. A flow chart of the method is shown in fig. 1. The characteristic temperature of the trap state in the semiconductor body is obtained by extracting the relation satisfied by the threshold voltage drift and the applied stress time, and the trap state density pushed to the bottom of the conduction band in the semiconductor body and the interface state density of the semiconductor and the gate insulating layer are obtained by sub-threshold swing amplitude calculation.
The specific embodiment of the invention is to extract the IZO/SiO2 interface trap state and the IZO in-vivo trap state of an indium zinc oxide thin film transistor (IZO TFT) by adopting the method for extracting the trap state density of the oxide semiconductor thin film transistor. Fig. 2 is a schematic structural diagram of an IZO TFT sample in the first embodiment of the present invention. A12 nm IZO film was grown by a solution method on an n-type heavily-doped Si wafer substrate with a 100nm thick insulating layer of SiO2 formed by thermal oxidation. And placing the deposited film sample into a rapid thermal annealing furnace, and performing rapid thermal annealing in an O2 atmosphere to optimize the film quality. Aluminum (Al) was then deposited by electron beam evaporation to a thickness of 150nm as source/drain electrodes of the IZO TFT. The IZO TFT prepared had a channel width of 1000 μm and a channel length of 200 μm.
After the devices were fabricated, IZO TFT samples were tested for transfer characteristics after applying forward bias stress for various lengths of time using the agilent 1505 platform. And (3) testing conditions are as follows: the gate voltage sweep range and direction was-20V to 40V, resulting in a first transfer characteristic, labeled 0 s. And then loading a positive voltage Vg of 20V on the grid electrode, simultaneously keeping the voltage Vd of the source and drain electrode of 0V, setting the loading time to be 1s, then running the test, and after the test is finished, testing a second transfer characteristic curve, wherein the scanning range and the direction of the grid voltage are consistent with those of the first transfer characteristic curve, and obtaining a second transfer characteristic curve of the IZO TFT, and marking the second transfer characteristic curve as 1 s. According to the steps, the forward bias loading time is set to 10s, 100s, 200s, 1000s and 2000s in sequence, and corresponding transfer characteristic curves are tested and marked respectively. Fig. 3 shows the transfer characteristics of IZO TFT samples under positive bias stress at different durations in the first embodiment of the present invention. It can be seen from fig. 3 that as the time of the applied forward bias stress increases, the whole transfer characteristic curve moves in parallel in the forward direction, the sub-threshold swing amplitude is basically unchanged, and the main influence mechanism of the forward shift of the threshold voltage is trap state trapping.
FIG. 4 is a graph showing the variation of threshold voltage with time under forward bias stress for an IZO TFT sample according to the first embodiment of the present invention. In this sample, when the gate insulating layer is SiO2, the threshold voltage shift Δ Vth and the applied stress time T satisfy the spreading exponential model, that is, Δ Vth ═ (Vgs-Vth0) {1-exp [ - (T/τ) β ] }, where Vgs is the gate-source voltage, Vth0 is the initial threshold voltage of the thin film transistor, τ is the characteristic time constant, β is the dispersion factor, Tt is the trap state characteristic temperature in the IZO semiconductor body, and T is the transistor operating temperature. Using the above formula, in conjunction with the curve shown in fig. 4, the characteristic temperature Tt of the trap state in the IZO semiconductor can be obtained.
And because the sub-threshold swing SS of IZO TFT can be expressed as:
Wherein q is basic charge, k is Boltzmann constant, Cox is unit area gate insulation layer capacitance, Dit is interface state density of semiconductor and gate insulation layer, ε 0 and ε s are vacuum dielectric constant and relative dielectric constant of semiconductor respectively, td and tch are depletion layer and channel layer thickness respectively, and NT is trap state density extrapolated to the bottom of the conduction band EC.
Wherein the depletion layer thickness td satisfies
Where φ b is the difference between the semiconductor Fermi level EF and the intrinsic Fermi level Ei, and Nch is the channel carrier concentration. The channel charge density Nch can be expressed as
Where Von is the turn-on voltage of the oxide semiconductor thin film transistor and is defined as the gate-source voltage corresponding to the initial increase of the drain-source current in the transfer characteristic curve of the transistor. By combining the above equations, the IZO/SiO2 interface state density Dit and the IZO in-vitro pushed trap state density NT to the bottom of the conduction band can be calculated by substituting the relevant parameters of the IZO TFT sample.
substituting the extracted characteristic temperature Tt of the trap state in the IZO body and the trap state density NT extrapolated to the bottom of the conduction band into the following formula to obtain the trap state density Nt in the IZO body
wherein E is energy.
The trap state of IZO TFT is extracted by the trap state density extraction method provided by the invention, and the relevant parameters are shown in the following table. FIG. 5 is a graph showing the distribution of in vivo trap states of IZO TFT samples extracted in the first embodiment of the present invention.
parameter list
In summary, the method for extracting trap state density of an oxide semiconductor thin film transistor provided by the invention extracts trap state density at the interface of a semiconductor of the thin film transistor and a gate insulating layer and trap state density in the semiconductor based on the relationship between the threshold voltage drift and applied stress time of the thin film transistor and the relationship between the subthreshold swing and the trap state density under forward bias stress, lays a foundation for constructing physical models of current, mobility, parasitic resistance and the like of the oxide semiconductor thin film transistor, provides a basis for circuit design, and is greatly beneficial to generating circuits. The method not only distinguishes the interface trap state and the internal trap state of the transistor, but also has simpler calculation process, less limiting conditions and wide application range compared with the existing method. The method is favorable for better analyzing the performance of the device, understanding the degradation and failure mechanism of the device, and provides theoretical guidance for evaluating the influence of the structure, the preparation process, the active layer and the gate insulating layer material of the thin film transistor on the electrical performance of the device.
In the embodiment of the invention, the active layer material of the thin film transistor sample is Indium Zinc Oxide (IZO), but is not limited to IZO, and may be a binary or multi-component metal oxide semiconductor material such as IGZO, In2O3, and the like. In addition, in the example, the gate insulating layer silicon dioxide (SiO2) of the thin film transistor may also be other insulating layer materials, provided that the transfer characteristic curve of the prepared thin film transistor is or is approximately parallel to move after applying forward bias stress for different time periods, i.e. the sub-threshold swing of the thin film transistor is basically unchanged.
In addition, the method for extracting the trap state of the oxide semiconductor thin film transistor can be used for extracting the trap state of the n-type oxide semiconductor thin film transistor, can also be used for extracting the trap state of the p-type oxide semiconductor thin film transistor by slightly modifying, changing electrons into holes and changing a conduction band bottom EC into a valence band top EV.
it should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (4)
1. A method for extracting trap state density of an oxide semiconductor thin film transistor is characterized by comprising the following steps:
1) Applying forward bias stress for different durations to the oxide semiconductor thin film transistor, and testing a corresponding transfer characteristic curve;
2) Analyzing a threshold voltage drift mechanism based on a change rule of the transfer characteristic, and determining a change relation of the threshold voltage drift along with time;
3) if the threshold voltage drift and the applied stress time meet the extension index model, extracting the characteristic temperature of a trap state in the semiconductor body;
4) Extracting interface state density of the semiconductor and the gate insulating layer and trap state density in the semiconductor by utilizing the relation between the subthreshold swing and the trap state;
When the grid electrode is applied with forward bias stress for different time lengths without illumination, the transfer characteristic curve of the oxide semiconductor thin film transistor is approximately parallel movement, and the amplitude of the subthreshold swing is not obviously changed;
Under forward bias stress, the oxide semiconductor thin film transistor threshold voltage drift mechanism comprises:
1) Trapping electrons by trap states, including trapping of an interface state and a trap state in a body and trapping of a trap state of a gate insulating layer; at the moment, the sub-threshold swing of the thin film transistor is unchanged, and the threshold voltage drift and the applied stress time meet the exponential relation; if the trapped carriers enter a deep trap state in the gate insulating layer, the threshold voltage drift and the applied stress time of the thin film transistor accord with an expansion index relation; when the gate insulating layer of the oxide semiconductor thin film transistor is SiO2, the threshold voltage drift and the applied stress time meet the expansion index model;
2) generating a trap state; at the moment, the threshold voltage drift of the thin film transistor is in logarithmic relation with the applied stress time;
Under forward bias stress, when the threshold voltage drift and the applied stress time of the oxide semiconductor thin film transistor satisfy the extended exponential model, the change relationship of the threshold voltage drift Δ Vth with the stress time t can be expressed as follows: Δ Vth ═ (Vgs-Vth0) {1-exp [ - (T/τ) β ] }, where Vgs is the gate-source voltage, Vth0 is the initial threshold voltage of the thin film transistor, τ is the characteristic time constant, β is the dispersion factor, Tt is the characteristic temperature of the trap state in the semiconductor body, and T is the operating temperature of the transistor; extracting the characteristic temperature of the trap state in the semiconductor body by using the relational expression and fitting a curve;
The sub-threshold swing SS may be expressed as
Wherein q is basic charge, k is Boltzmann constant, Cox is unit area gate insulation layer capacitance, Dit is interface state density of semiconductor and gate insulation layer, ε 0 and ε s are vacuum dielectric constant and relative dielectric constant of semiconductor respectively, td and tch are depletion layer and channel layer thickness respectively, and NT is trap state density extrapolated to the bottom of the conduction band EC.
2. the method of claim 1, wherein the method comprises: the calculation method of the sub-threshold swing SS is characterized in that the parameter td can be expressed as
where φ b is the difference between the semiconductor Fermi level EF and the intrinsic Fermi level Ei, and Nch is the channel carrier concentration.
3. The method of claim 2, wherein the method comprises: method for calculating sub-threshold swing SS, characterized in that parameter Nch can be expressed as
Where Von is the turn-on voltage of the oxide semiconductor thin film transistor and is defined as the gate-source voltage corresponding to the initial increase of the drain-source current in the transfer characteristic curve of the transistor.
4. the method of claim 1, wherein the method comprises: extracting characteristic temperature Tt of trap state in the semiconductor body and trap state density NT extrapolated to the conduction band bottom, and obtaining trap state density Nt in the semiconductor body by using the following formula
wherein E is energy and EC is minimum value of conduction band bottom of oxide semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710571427.0A CN107478977B (en) | 2017-07-13 | 2017-07-13 | Method for extracting trap state density of oxide semiconductor thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710571427.0A CN107478977B (en) | 2017-07-13 | 2017-07-13 | Method for extracting trap state density of oxide semiconductor thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107478977A CN107478977A (en) | 2017-12-15 |
| CN107478977B true CN107478977B (en) | 2019-12-06 |
Family
ID=60596538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710571427.0A Active CN107478977B (en) | 2017-07-13 | 2017-07-13 | Method for extracting trap state density of oxide semiconductor thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107478977B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108196178B (en) * | 2017-12-28 | 2020-02-14 | 电子科技大学 | Measuring device for surface trap energy level distribution and photoconductive analysis method |
| CN108598005B (en) * | 2018-05-02 | 2021-05-07 | 华东师范大学 | Preparation method of indium oxide thin film transistor with low sub-threshold swing amplitude |
| CN108614203A (en) * | 2018-05-06 | 2018-10-02 | 北京工业大学 | A method of resistance-variable storing device internal trap is analyzed by transient current |
| CN109270423B (en) * | 2018-10-03 | 2020-11-20 | 大连理工大学 | Evaluation test method for low-temperature stability of SiC MOSFET device |
| CN109901038B (en) * | 2019-03-01 | 2021-06-08 | 西安太乙电子有限公司 | Method for determining trap state of gate dielectric layer for insulated gate HEMT |
| CN112955760B (en) * | 2020-04-02 | 2022-05-31 | 北京大学深圳研究生院 | Interface state analysis method and device of MIS-HEMT device |
| CN114152854B (en) * | 2021-11-08 | 2024-05-28 | 北京工业大学 | Method for carrying out nondestructive electrical detection on internal defects of flexible thin film transistor based on trap carrier trapping mechanism |
| CN116165504B (en) * | 2023-03-01 | 2024-03-22 | 安徽大学 | Method for detecting and correcting threshold voltage drift of gallium nitride transistor |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102053114B (en) * | 2010-11-02 | 2012-12-12 | 北京大学 | Method for testing density of grid dielectric layer trap of non-substrate semiconductor device |
| CN102353882B (en) * | 2011-06-09 | 2014-02-19 | 北京大学 | Method for testing trap density and position of gate dielectric layer of semiconductor device |
| CN102520331B (en) * | 2011-12-02 | 2013-12-11 | 北京大学 | Interface trap testing method for shallow trench isolation (STI) type laterally diffused metal oxide semiconductor (LDMOS) device |
| CN102708220A (en) * | 2011-12-28 | 2012-10-03 | 北京华大九天软件有限公司 | Method for modeling and emulating hysteresis effect of thin film transistor (TFT) |
| CN102832203B (en) * | 2012-08-29 | 2014-10-08 | 北京大学 | Structure and method for testing trap density of gate oxide interface |
| CN103367193B (en) * | 2013-07-24 | 2015-10-07 | 北京大学 | The method of testing of gate oxide trap density and position and device |
| CN106556789A (en) * | 2015-09-23 | 2017-04-05 | 中国科学院微电子研究所 | Method and system for extracting semiconductor defect energy level |
-
2017
- 2017-07-13 CN CN201710571427.0A patent/CN107478977B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107478977A (en) | 2017-12-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107478977B (en) | Method for extracting trap state density of oxide semiconductor thin film transistor | |
| Liu et al. | Device physics of contact issues for the overestimation and underestimation of carrier mobility in field-effect transistors | |
| Abe et al. | Amorphous In–Ga–Zn–O dual-gate TFTs: Current–voltage characteristics and electrical stress instabilities | |
| Wu et al. | Analytical extraction method for density of states in metal oxide thin-film transistors by using low-frequency capacitance–voltage characteristics | |
| CN105628262A (en) | Thin film transistor pressure sensor based on organic elastomer gate insulating layer | |
| Lee et al. | Hot carrier degradation of InGaZnO thin film transistors under light illumination at the elevated temperature | |
| Lee et al. | Effects of channel type and doping on hysteresis in low-temperature poly-Si thin-film transistors | |
| Liu et al. | Bias-stress-induced instability of polymer thin-film transistor based on poly (3-Hexylthiophene) | |
| Um et al. | P‐7: High Speed a‐IGZO TFT‐based Gate Driver by using Back Channel Etched Structure | |
| Najmzadeh et al. | 2D MOSFET operation of a fully-depleted bulk MoS 2 at quasi-flatband back-gate | |
| Xiang et al. | An analytical frequency-dependent capacitance-voltage model for metal oxide thin-film transistors | |
| Yang et al. | Physics-based compact model of current stress-induced threshold voltage shift in top-gate self-aligned amorphous InGaZnO thin-film transistors | |
| Zeumault et al. | Improved technique for quantifying the bias-dependent mobility of metal-oxide thin-film transistors | |
| Liu et al. | P‐169: A 31‐inch 4K2K Top‐emission OLED Display Using Good Uniformity and Long‐term Reliability Top‐gate Self‐aligned IGZO TFTs | |
| Han et al. | P‐7.6: Analysis between Subgap Density of State and NBIS of Top Gate a‐IGZO TFTs | |
| Pearman | Electrical characterisation and modelling of schottky barrier metal source/drain MOSFETs | |
| Yeh | Modeling and characterization of amorphous oxide semiconductor thin-film transistors | |
| Xie et al. | Effects of Static and Repetitive Uniaxial Bending Strains on the Electrical Properties and Trap Characteristics of Flexible Low-Temperature Polysilicon Thin-Film Transistors | |
| Wang et al. | Simplification of sub-gap density of states extraction method for amorphous In-Ga-Zn-O thin-film transistors by a single capacitance-voltage curve | |
| Chatterjee et al. | Modeling the Evolution of Trap States with Thermal Post-deposition Treatments in Sol-gel Indium Zinc Oxide TFTs | |
| Kim et al. | Performance and reliability enhancement of flexible low-temperature polycrystalline silicon thin-film transistors via activation-annealing temperature optimization | |
| Chen et al. | Impact of passivation layer on the subthreshold behavior of p-type CuO accumulation-mode thin-film transistors | |
| Mathews et al. | Influence of extended bias stress on the electrical parameters of mixed oxide thin film transistors | |
| Bae et al. | P. 14: Distinguished Poster Paper: Separate Extraction Technique for Intrinsic Donor‐and Acceptor‐like Density‐of‐States over Full‐Energy Range Sub‐Bandgap in Amorphous Oxide Semiconductor Thin Film Transistors by Using One‐Shot Monochromatic Photonic Capacitance‐Voltage Characteristics | |
| Wang et al. | Analysis of the temperature dependent contact resistance in amorphous InGaZnO thin film transistors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |