CN109901038B - Method for determining trap state of gate dielectric layer for insulated gate HEMT - Google Patents

Method for determining trap state of gate dielectric layer for insulated gate HEMT Download PDF

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CN109901038B
CN109901038B CN201910155810.7A CN201910155810A CN109901038B CN 109901038 B CN109901038 B CN 109901038B CN 201910155810 A CN201910155810 A CN 201910155810A CN 109901038 B CN109901038 B CN 109901038B
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毕志伟
张璨
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Xi'an Taiyi Electronics Co ltd
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Abstract

The invention discloses a grid dielectric layer trap state measuring method for an insulated grid type HEMT, which is characterized in that an HEMT device is manufactured on the same substrate by adopting a covering method, depletion voltage of a corresponding device is obtained by performing C-V characteristic test on the HEMT device and an MIS-HEMT device, gate voltage is selected near the depletion voltage as test point voltage, capacitance-to-frequency (Cm-f) and conductance-to-frequency (Gm-f) characteristic tests are performed on different grid voltages, barrier layer trap state density and MIS-HEMT total trap state density of a common HEMT device are obtained by model calculation, and then dielectric layer trap state density of the MIS-HEMT device is obtained by calculation, and accordingly dielectric layer quality can be determined.

Description

Method for determining trap state of gate dielectric layer for insulated gate HEMT
Technical Field
The invention belongs to the technical field of microelectronics, relates to the extraction problem of trap state density of a semiconductor device surface and a gate dielectric layer, is particularly suitable for a high electron mobility transistor of a III-V group compound semiconductor material heterojunction structure, and can be used for comparative analysis of the trap state density of the gate dielectric layer of the device.
Background
Semiconductor materials composed of group iii elements and group v elements, such as gallium nitride (GaN) -based and gallium arsenide (GaAs) -based semiconductor materials, have a large difference in their forbidden bandwidths, and thus, these group iii-v compound semiconductor materials are generally used to form various heterojunction structures. The high electron mobility transistor manufactured based on the heterojunction has the characteristics of high carrier mobility, high working frequency, high power, good radiation resistance and the like, and can be widely applied to the fields of microwave power systems, aerospace radiation-resistant systems and the like. In 1993, Khan et al reported the first AlGaN/GaN-HEMT device in the world with an output saturation current density of about 40 mA/mm. Since the research on high electron mobility transistors has progressed rapidly, Fuji corporation has recently developed A1GaN/GaN HEMTs with powers up to 250W.
In the development process of the gallium nitride-based HEMT, a key factor restricting the power characteristic and the reliability of the HEMT is found to be large grid leakage current of the HEMT device. In order to suppress the gate leakage current, a "metal-insulator-semiconductor (MIS)" structure has been introduced into the structural design of the gallium nitride HEMT, and many significant efforts have been made. The advantages of this structure are three-fold. Firstly, the grid leakage current of the device is greatly reduced, and the breakdown voltage of the device is improved; secondly, the Grid Voltage Swing (GVS) of the transconductance of the transistor is obviously improved; thirdly, the microwave performance of the device is improved significantly, since the dielectric layer functions as a passivation layer in addition to the insulating layer.
At present, the use of dielectric layers is still under the exploration stage, and the use of dielectric layers should comprehensively consider the factors of dielectric constant, insulating property, passivation effect and the like, for example, HfO2Has higher dielectric constant but excellent HfO2The film layer is difficult to obtain; al (Al)2O3The film has better film forming quality, lower trap state density and lower dielectric constant; SiO 22Has the advantages of simple deposition technique, easy operation, etc., but has dielectric constant higher than that of Al2O3And lower.
For MIS type or MOS type high electron mobility transistor, the difficulty of its manufacture lies in the deposition of dielectric layer, because various dielectric layers are grown on AlGaN and SiO is formed2The conditions for growing the corresponding dielectric layers are different, and the growth conditions of the existing growth equipment are generally directed to Si base, so that how to grow a high-quality film on AlGaN becomes a problem to be faced. Typically, growers are required to go through multiple growth and testing experiments to be able to confirm growth conditions. How to quickly and accurately determine various parameters related to trap states in the process of growth debugging of a dielectric layer and evaluation of a finished device is a subject of research of researchers. At present, the precision of I-V method tests and the like is relatively high, but the requirement on equipment is high, the processing method is complex, and the multilayer trap state density is difficult to characterize. The common characterization of trap states always depends on C-V hysteresis, variable frequency C-V frequency dispersion, illumination C-V, variable frequency conductivity method and the like, but the processing method only aims at the comprehensive trap state density of all layers (including a dielectric layer, a barrier layer, a channel layer and the like) of the whole device, cannot aim at the dielectric layer, and cannot erase the influence of two-dimensional electron gas of the channel layer on the test result. In 2000, E.J.Miller et al proposed a frequency conversion C-V and G-V method for measuring the barrier layer and channel layer of HEMT devices, which can significantly eliminate the influence of two-dimensional electron gas in the channel layer and realize the extraction method for the trap state density in HEMT devices.
However, this method is only applied to HEMT devices, and cannot be applied to extraction of trap state density of the dielectric layer itself in MIS-HEMT devices, and thus cannot determine the quality of the dielectric layer.
Disclosure of Invention
The invention aims to provide an extraction method suitable for the medium layer internal average trap density in an MIS structure HEMT device so as to overcome the defects of the existing method.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows: a method for determining the trap state of a gate dielectric layer of an insulated gate HEMT comprises the following steps:
s1, establishing a cross section model of the HEMT device and a cross section model of the MIS-HEMT device, and establishing an equivalent circuit for the cross section model of the HEMT device and the cross section model of the MIS-HEMT device; the substrate structure of the MIS-HEMT device is consistent with that of the HEMT device;
s2, selecting a plurality of test voltage points in the depletion voltage region for the HEMT device and the MIS-HEMT device;
s3, testing the change characteristic curves of the conductance-frequency and the capacitance-frequency of the test voltage point to obtain the relationship between the conductance Gm and the test frequency f and the relationship between the capacitance Cm and the test frequency f;
s4, measuring the barrier layer capacitance C of the HEMT devicebFitting to obtain the capacitance Cs of the spacer layer according to the equivalent circuit of the cross section model of the HEMT device established in the step S1, and obtaining the capacitance C of the barrier layer of the HEMT device according to the capacitance C of the barrier layerbCalculating the trap state density D of the barrier layer by the capacitance Cs of the spacing layeritb；
S5, for the MIS-HEMT device, fitting to obtain the sum Dit (b + i) of trap state densities of the barrier layer and the dielectric layer according to the equivalent circuit of the cross section model of the MIS-HEMT device established in S1; according to formula Diti＝Dit(b+i)-DitbAnd calculating the density D of trap states in the dielectric layers under different test pointsitiAnd calculating the average trap state density of the MIS-HEMT device.
Further, in step S1, a cross-sectional model of the HEMT device structure and a cross-sectional model of the MIS-HEMT device are established in a sequence from bottom to top; and manufacturing the HEMT device and the MIS-HEMT device on the same substrate by adopting a masking method, wherein the unmasked part is the MIS-HEMT device.
Further, in step S1, when the MIS-HEMT device is a multilayer composite gate dielectric, the composite gate dielectric is equivalent to a gate dielectric by: and solving the equivalent dielectric constant of the multilayer composite gate dielectric, and establishing a corresponding equivalent circuit model for the obtained equivalent dielectric layer.
Further, in step S2, the method for selecting the test voltage point includes: determining the depletion voltage of the corresponding device according to the capacitance-voltage characteristic of the selected device; and selecting a plurality of gate voltage values for testing between the depletion voltage and the starting voltage, wherein the gate voltage values are the testing voltage points.
Further, in step S2, the number of the selected test voltage points is 2 to 4.
Further, in step S3, the conductance-frequency and capacitance-frequency variation characteristic curves of the test voltage points are tested according to the test frequency of 10KHz to 10 MHz.
Further, in step S4, the capacitance Cs of the spacer layer is calculated as shown in formula (1) to formula (6):
Figure GDA0002802498470000041
Figure GDA0002802498470000042
ω＝2πf (3)
Figure GDA0002802498470000043
Figure GDA0002802498470000044
Dit＝Cit·q (6)
wherein Rs is a series resistor of a drain electrode, Cb is a barrier layer capacitor, Cit is a spacer interface trap capacitor, q is single electron electric quantity, tau is a trap state time constant, and omega is angular frequency;
Figure GDA0002802498470000045
and CpFor calculating the intermediate quantity, the measured value conductance-frequency and capacitance-frequency are obtained by the formulas (1) and (2); fitting by using the formulas (4) to (6) to obtain the capacitance Cs of the spacer layer, the series resistance Rs of the drain electrode and the trap state density D of the spacer layerit。
Further, in step S4, the barrier layer capacitance C is determined according to the capacitance-voltage characteristics of the HEMT deviceb(ii) a Density of trap states of the barrier layer DitbThe calculation method of (2) is shown in equations (7), (8), (9) and (10):
Figure GDA0002802498470000046
Figure GDA0002802498470000047
Figure GDA0002802498470000051
Figure GDA0002802498470000052
(10) wherein the content of the first and second substances,
Figure GDA0002802498470000053
and CpFor calculating the intermediate quantity, the measured value conductance-frequency and capacitance-frequency are obtained by the formulas (7) and (8); the capacitance Cs of the spacer layer is already a known quantity.
Further, the sum Dit (b + i) of trap state densities of the barrier layer and the dielectric layer in step S5 is determined according to equations (11), (12), (13), and (14):
Figure GDA0002802498470000054
Figure GDA0002802498470000055
Figure GDA0002802498470000056
Dit(b+i)＝Cit(b+i)·q (14)
wherein the content of the first and second substances,
Figure GDA0002802498470000057
and CpFor calculating the intermediate quantity, the conductance-frequency and the capacitance-frequency are obtained by the formulas (11) to (14); the capacitance Cs of the spacing layer is already a known quantity, and the sum Dit (b + i) of trap state densities of the barrier layer and the dielectric layer can be obtained through calculation.
Further, when the gate length of the HEMT device and the MIS-HEMT device is smaller than 1um, a capacitance ring is manufactured for the HEMT device and the MIS-HEMT device, and the trap state density is extracted by using the capacitance ring.
Compared with the prior art, the invention has at least the following beneficial effects:
compared with the traditional C-V method, the method of the invention has the following advantages:
1. the invention adopts a frequency dependence method, has wider frequency variation range, and can more comprehensively cover the trap states of different constants, thereby obviously improving the detection range of the trap states of different constants.
2. The method focuses on extracting trap state density in the gate dielectric layer, and the quality of the dielectric layer determines important factors such as breakdown voltage, frequency characteristics and power performance of the device to a great extent, so that the method is more beneficial to performance characterization of the device.
3. The traditional C-V method is greatly influenced by a bottom barrier layer, and because various passivation layers can be added to an HEMT device in order to improve the performance, an insertion layer is added below the barrier layer and the like, and the C-V characteristic of the device can be obviously influenced by excessive layers, the traditional C-V method can only carry out rough evaluation on trap state density, cannot achieve the precision of the method, and has different meanings for production guidance.
Compared with the traditional frequency dispersion method, the method of the invention has the following advantages:
1. the method can accurately extract the trap state density in the dielectric layer.
2. The invention creatively adopts the method of manufacturing HEMT devices on the same substrate by adopting the masking method, and the influence of the dielectric layer is removed, thereby obtaining the Cs of the spacing layer and the trap state density D of the barrier layeritbAccurate fitting provides the necessary conditions, extracted Cs and DitbThe method can be directly applied to MIS-HEMT devices which are grown and manufactured on the same wafer, so that the extraction precision of the trap state density of the dielectric layer is ensured to the maximum extent.
3. The method has high feasibility, gives consideration to the simplicity and the precision of extraction, and can be used as an important evaluation basis in the deposition production process of the dielectric layer.
Drawings
FIG. 1 is a diagram of the structure and Cs-fitting equivalent circuit of a HEMT device in accordance with the present invention;
FIG. 2 is a diagram of the structure and Cb-fitting equivalent circuit of a HEMT device in accordance with the present invention;
FIG. 3 is a structural diagram of a HEMT device adopting MIS structure and a Ce-fitted equivalent circuit diagram according to the present invention;
FIG. 4 is a C-V plot of a MIS-HEMT device and a HEMT device;
FIG. 5a is a characteristic curve of conductance-frequency (Gm-f) variation obtained by testing a conventional device using a frequency conversion test method in the present invention;
FIG. 5b is a capacitance-frequency (Cm-f) variation characteristic curve obtained by testing a conventional device by using a frequency conversion test method in the present invention;
FIG. 6a is a graph showing conductance-frequency (Gm-f) variation characteristics of MIS-type device tested by a frequency conversion test method according to the present invention;
FIG. 6b is a graph showing capacitance-frequency (Cm-f) variation characteristics of MIS device tested by a frequency conversion test method according to the present invention;
FIG. 7a is a graph of the fit of a conventional HEMT spacer capacitance Cs (test gate voltage-4.0V) in accordance with the present invention;
FIG. 7b is a graph of the fit of the spacer capacitance Cs of a conventional HEMT of the present invention (test gate voltage-4.1V);
FIG. 7c is a graph of the fit of the spacer capacitance Cs of a conventional HEMT of the present invention (test gate voltage-4.2V);
FIG. 7d is a graph of the fit of the spacer capacitance Cs of a conventional HEMT of the present invention (test gate voltage-4.3V);
FIG. 8 is a graph of the fit of the MIS-HEMT spacer capacitance Cs in the present invention;
FIG. 9a is a graph of the total defect state density of dielectric and barrier layers in an MIS device using a capacitance-frequency (Cm-f) fit (gate voltage 9.1V) in the present invention;
FIG. 9b is a graph of the total defect state density of the dielectric layer and barrier layer in the MIS device using a capacitance-frequency (Cm-f) fit (gate voltage 9.2V) in the present invention;
FIG. 9c is a graph of the total defect state density of the dielectric layer and barrier layer in the MIS device using a capacitance-frequency (Cm-f) fit (gate voltage 9.3V) in the present invention;
FIG. 9d is a graph of the total defect state density of the dielectric and barrier layers in the MIS device using a capacitance-to-frequency (Cm-f) fit in the present invention (gate voltage 9.4V);
in the drawings: 1-substrate, 2-transition layer, 3-dielectric layer, 4-barrier layer, 5-protective layer and 6-insulating layer.
Detailed Description
The specific embodiment is described by taking an AlGaN/GaN heterojunction MIS-HEMT as an example.
Referring to fig. 1 and 2, a conventional HEMT structure used in the present invention is a HEMT structure having, from bottom to top: substrate 1, transition 2 layer, dielectric layer 3, barrier layer 4 and protective layer 5. Referring to fig. 3, the MIS-HEMT structure used in the present invention is, from bottom to top: the substrate 1, the transition layer 2, the dielectric layer 3, the barrier layer 4, the insulating layer 6 and the protective layer 5.
The method for extracting the trap state in the gate dielectric layer comprises the following steps:
step 1, performing C-V characteristic test on the MIS-HEMT device and the HEMT device to obtain a corresponding C-V curve chart, and determining the depletion voltage of the corresponding device according to the curve chart; the MIS-HEMT device and the HEMT device C-V characteristic test curve are shown in FIG. 4.
Step 2, determining the test gate voltage of the HEMT device, wherein the method comprises the following steps: and selecting 2-4 gate voltages as test voltages near the depletion voltage, wherein the 2-4 selected gate voltages are uniformly distributed between the fully depleted voltage and the just-turned-on voltage. For the HEMT device, four gate voltages of-4.0V, -4.1V, -4.2V and-4.3V are selected in the embodiment, the test curves are shown in fig. 5a and 5b, and the frequency test range is 10KHz to 10 MHz. The voltage near the depletion voltage is chosen to eliminate the effect of channel layer body traps.
And 3, determining the test gate voltage of the MIS-HEMT device, wherein the method is the same as the step 2, and four gate voltages of-9.1V, -9.2V, -9.3V and-9.4V are selected for the MIS-HEMT device.
Step 4, using a semiconductor parameter analyzer to perform C on the HEMT device and the MIS-HEMT device under different grid voltagesmF and GmF, testing the characteristic, wherein the testing frequency is 10 k-10 MHz, the HEMT device testing curve is shown in figure 5, the MIS-HEMT device testing curve is shown in figures 6a and 6b, and the frequency testing range is 10 KHz-10 MHz; for the capacitance C of the test resultmAnd conductance GmAnd storing for later treatment.
Step 5, FIG. 1 is an equivalent circuit for fitting the spacer layer capacitance Cs of the HEMT device, wherein Rs is the series resistance of the drain, CbIs a barrier layer capacitance, CitIs the spacer layer interface trap capacitance. According to the equivalent model in FIG. 1, for the test value capacitance CmAnd conductance GmAnd a capacitance fitting value CpAnd conductance fitted value GpThe relationship between the angular frequency ω and the test frequency f is derived to obtain equations (1) and (2), and the conversion relationship between the angular frequency ω and the test frequency f is shown in equation (3).
Figure GDA0002802498470000091
Figure GDA0002802498470000092
ω＝2πf (3)
Using the formulas (1), (2) and (3) to CmF and GmF, processing the test result to obtain CpAnd GpDistribution of/ω.
Step 6, using the formula (4) to obtain CpAnd GpFitting the distribution of/omega to obtain the trap state density D of the spacing layeritAnd trap time constant τ, will DitAnd the results of τ are substituted into equations (5) and (6) to obtain the value of the spacer layer capacitance Cs. In the formula (6), q is the single electron electric quantity.
Figure GDA0002802498470000093
Figure GDA0002802498470000094
Dit＝Cit·q (6)
After fitting, a fitting graph of the common type HEMT spacer layer capacitance Cs is shown in fig. 7a to 7d, and a fitting graph of the MIS-HEMT spacer layer capacitance Cs is shown in fig. 8.
Step 7, FIG. 2 is an equivalent circuit for fitting the trap state density of the barrier layer of the HEMT device, wherein CsIs already a known quantity. According to the equivalent circuit diagram, traps in the fitted barrier layer can be obtainedAt density of state, test value Cm1And Gm1And fitting value Cp1And Gp1The relationship between them is shown in formula (7) and formula (8):
Figure GDA0002802498470000095
Figure GDA0002802498470000096
Figure GDA0002802498470000097
Ditb＝Citbq (10) fitting the formula (7) and the formula (8) with the formula (9) and the formula (10) to obtain the trap state density D of the barrier layer of the HEMT deviceitb。
Step 8, FIG. 3 is an equivalent circuit for fitting the trap state density of the dielectric layer of the MIS-HEMT device, wherein Ce＝Cb+Cox，CeIs the equivalent capacitance of the dielectric layer and the barrier layer, CoxThe dielectric layer capacitance can be determined after the type and thickness of the dielectric layer capacitance are determined, and the spacer layer capacitance CsHas been obtained from step 6. According to the equivalent circuit diagram, the test value C can be obtained when the trap state density of the barrier layer is fittedmAnd GmAnd fitting value CpAnd GpThe relationship between them is shown in formula (11) and formula (12):
Figure GDA0002802498470000101
Figure GDA0002802498470000102
Figure GDA0002802498470000103
Dit(b+i)＝Cit(b+i)q (14) Using equation (5)
And (6) after fitting treatment, obtaining the total trap state density D of the barrier layer and the dielectric layer of the MIS-HEMT deviceit(b+i)The fitting results are shown in fig. 9a to 9 d.
Step 9, using formula Diti＝Dit(b+i)-DitbAnd calculating to obtain the trap state density D of the dielectric layeriti。
The device structure applicable to the invention is a heterojunction structure formed by adopting any compound semiconductor material, and the structure comprises the following components from bottom to top: the device comprises a substrate, a transition layer, a barrier layer, a gate dielectric layer (composite gate dielectric layer), a source electrode, a drain electrode, a grid electrode, a passivation layer and a protective layer. The dielectric layer may be a single layer or a plurality of layers.
The coverage area of each dielectric layer is the same, but the thickness and the composition of each layer can be different.
In the manufacturing process of the device, a part of a common HEMT is manufactured on the same substrate by adopting a masking method, and the common HEMT is different from an MIS or MOS structure HEMT in that the common HEMT structure does not contain a dielectric layer. The purpose of manufacturing the common HEMT is to accurately extract the spacer layer capacitor and the barrier layer capacitor, so that the extraction precision of the trap in the dielectric layer is improved.
It should be noted that, for a device with a small gate length, which is usually less than 1um, the capacitor ring must be fabricated on both the fabricated HEMT device and the MIS HEMT device, and the trap state density is extracted by using the capacitor ring, otherwise the extraction accuracy may be affected.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and are not limited thereto, and although the detailed description of the specific implementation of the present invention is made with reference to the foregoing, those skilled in the art should understand the following contents: the technical solutions mentioned above can be modified or some technical features can be equivalently replaced by technical personnel, so that the invention can be reasonably applied to practical engineering; meanwhile, the technical proposal of the invention is not to depart from the spirit and scope of the technical proposal of the invention by the modification or the replacement of the technical proposal by the technical personnel.

Claims (10)

1. A method for determining the trap state of a gate dielectric layer of an insulated gate HEMT is characterized by comprising the following steps:
s1, establishing a cross section model of the HEMT device and a cross section model of the MIS-HEMT device, and establishing an equivalent circuit for the cross section model of the HEMT device and the cross section model of the MIS-HEMT device; the substrate structure of the MIS-HEMT device is consistent with that of the HEMT device;
s2, selecting a plurality of test voltage points in the depletion voltage region for the HEMT device and the MIS-HEMT device;
s3, testing the variation characteristic curves of the conductance-frequency and the capacitance-frequency of the test voltage point selected in the step S2 respectively for the HEMT device and the MIS-HEMT device to obtain the relation between the conductance Gm and the test frequency f and the relation between the capacitance Cm and the test frequency f;
s4, measuring the barrier layer capacitance C of the HEMT devicebFitting to obtain the capacitance Cs of the spacer layer according to the equivalent circuit of the cross section model of the HEMT device established in the step S1, and obtaining the capacitance C of the barrier layer of the HEMT device according to the capacitance C of the barrier layerbCalculating the trap state density D of the barrier layer by the capacitance Cs of the spacing layeritb；
S5, for the MIS-HEMT device, according to the equivalent circuit of the cross section model of the MIS-HEMT device established in the S1, the sum D of the trap state densities of the barrier layer and the dielectric layer is obtained through fittingit(b+i)(ii) a According to formula Diti＝Dit(b+i)-DitbAnd calculating the density D of trap states in the dielectric layers under different test pointsitiAnd calculating the average trap state density of the MIS-HEMT device.
2. The method according to claim 1, wherein in step S1, a cross-sectional model of the HEMT device structure and a cross-sectional model of the MIS-HEMT device are created in the order from bottom to top; and the HEMT device and the MIS-HEMT device are manufactured on the same substrate by adopting a masking method.
3. The method of claim 1, wherein in step S1, when the MIS-HEMT device is a multilayer composite gate dielectric, the composite gate dielectric is equivalent to a gate dielectric by: and solving the equivalent dielectric constant of the multilayer composite gate dielectric, and establishing a corresponding equivalent circuit model for the obtained equivalent dielectric layer.
4. The method for determining the trap state of the gate dielectric layer of the insulated gate HEMT of claim 1, wherein in step S2, said test voltage point is selected by: determining the depletion voltage of the corresponding device according to the capacitance-voltage characteristic of the selected device; and selecting a plurality of gate voltage values for testing between the depletion voltage and the starting voltage, wherein the gate voltage values are the testing voltage points.
5. The method for determining the trap state of the gate dielectric layer of the insulated gate HEMT of claim 1 or 4, wherein in step S2, the number of the selected test voltage points is 2 to 4.
6. The method according to claim 1, wherein in step S3, the conductance-frequency and capacitance-frequency variation characteristic curves of the test voltage points are tested at a test frequency of 10KHz to 10 MHz.
7. The method for determining the trap state of the gate dielectric layer for the insulated gate HEMT of claim 1, wherein in said step S4, the capacitance Cs of said spacer layer is calculated as shown in equations (1) to (6):
Figure FDA0002802498460000021
Figure FDA0002802498460000022
ω＝2πf (3)
Figure FDA0002802498460000023
Figure FDA0002802498460000024
Dit＝Cit·q (6)
wherein Rs is a series resistor of a drain electrode, Cb is a barrier layer capacitor, Cit is a spacer interface trap capacitor, q is single electron electric quantity, tau is a trap state time constant, and omega is angular frequency;
Figure FDA0002802498460000025
and CpFor calculating the intermediate quantity, the measured value conductance-frequency and capacitance-frequency are obtained by the formulas (1) and (2); fitting by using the formulas (4) to (6) to obtain the capacitance Cs of the spacer layer, the series resistance Rs of the drain electrode and the trap state density D of the spacer layerit。
8. The method for determining the trap state of the gate dielectric layer of the insulated gate HEMT of claim 7, wherein said barrier layer capacitance C is determined according to the capacitance-voltage characteristics of said HEMT device in step S4b(ii) a Density of trap states of the barrier layer DitbThe calculation method of (2) is shown in equations (7), (8), (9) and (10):
Figure FDA0002802498460000031
Figure FDA0002802498460000032
Figure FDA0002802498460000033
Ditb＝Citb·q (10)
wherein the content of the first and second substances,
Figure FDA0002802498460000034
and CpFor calculating the intermediate quantity, the measured value conductance-frequency and capacitance-frequency are obtained by the formulas (7) and (8); the capacitance Cs of the spacer layer is already a known quantity.
9. The method for determining the trap state of the gate dielectric layer of the insulated gate HEMT of claim 7, wherein the sum D of the trap state densities of the barrier layer and the dielectric layer in step S5it(b+i)Determined according to equations (11), (12), (13), and (14):
Figure FDA0002802498460000035
Figure FDA0002802498460000036
Figure FDA0002802498460000037
Dit(b+i)＝Cit(b+i)·q (14)
wherein the content of the first and second substances,
Figure FDA0002802498460000041
and CpFor calculating the intermediate quantity, the conductance-frequency and the capacitance-frequency are obtained by the formulas (11) to (14); the capacitance Cs of the spacing layer is already a known quantity, and the sum D of trap state densities of the barrier layer and the dielectric layer can be obtained through calculationit(b+i)。
10. The method according to claim 1, wherein when the gate lengths of the HEMT device and the MIS-HEMT device are less than 1um, a capacitance ring is formed for the HEMT device and the MIS-HEMT device, and the trap state density is extracted using the capacitance ring.
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