CN102262206B - Method for predicting negative bias temperature instability (NBTI) service life of pMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) device - Google Patents
Method for predicting negative bias temperature instability (NBTI) service life of pMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title abstract description 4
- 230000005669 field effect Effects 0.000 title abstract 2
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 238000012360 testing method Methods 0.000 claims abstract description 23
- 238000013213 extrapolation Methods 0.000 claims description 6
- 230000029087 digestion Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000007796 conventional method Methods 0.000 abstract description 5
- 230000035882 stress Effects 0.000 abstract 7
- 230000032683 aging Effects 0.000 abstract 2
- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 5
- 238000006731 degradation reaction Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 230000007850 degeneration Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Abstract
The invention discloses a method for predicting a negative bias temperature instability (NBTI) service life of a pMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) device. The method comprises the following steps of: S1, before applying negative bias stress, measuring initial characteristics of the pMOSFET device to obtain initial parameters of the device; S2, applying a stress condition to a grid of the device, wherein drain voltage is normal working voltage; performing stress aging test to the device within a pre-set time interval; S3, testing the parameters of the device to obtain device parameters related to the aging time until the total stress time is ended; S4, when the drain voltage is the normal working voltage, repeating the steps S2 and S3; testing different stress conditions; referencing to the device parameters retrograded to a critical point; obtaining failure times of the pMOSFET device under the relative stress conditions; and S5, using the failure times of the pMOSFET device under the different stress conditions, predicting the reliability service life of the device when the gate voltage is the normal working voltage. Because the failure time of the device obtained by the method in the invention is shorter than that obtained by the conventional method, the NBTI service life of the pMOSFET device can be well reflected.
Description
Technical field
The present invention relates to MOS device reliability technical field, particularly a kind of pMOSFET device negative bias thermal instability life-span prediction method.
Background technology
Along with the develop rapidly of semiconductor technology and the significantly raising of microelectronic chip integrated level, integrated circuit (IC) design and level of processing have entered the nanoscale MOS epoch, the appearance of surface channel device, the Ultra Thin Gate Oxide of the attenuate of device oxidated layer thickness and the high nitrogen-containing that adopts for suppressor leakage current and boron penetration effects, caused the electric field across oxide increase, make negative bias thermal instability (Negative Bias Temperature Instability, NBTI), reliability degradation failure becomes the main integrity problem of current limiting device scaled down, particularly outstanding in the pMOSFET device.Conventional method of testing is carried out under long channel device, high temperature and homogeneous state of stress condition, by the acceleration electric stress test prediction of carrying out on reliability testing structure, draws the pMOSFET device reliability life-span.
When the pMOSFET device under NBTI reliability effect of stress, the drift that the degeneration main manifestations of device is the Primary Component parameters such as threshold voltage, drain saturation current, mutual conductance, once the key parameter of device floats to a certain degree, the normal operating conditions of pMOSFET device will not exist, and finally can cause the inefficacy of integrated circuit.In normal operation, the degeneration of NBTI is an accumulative process slowly in the life cycle of whole integrated circuit, therefore, the sign of degenerating for the NBTI of silicon chip level pMOSFET device must be by means of the acceleration stress of short time, test structure schematic diagram commonly used as shown in Figure 1, test structure is a four-terminal device that comprises source electrode, grid, drain electrode and substrate, and wherein W and L mean respectively channel width and the channel length of device.Typical drain saturation current with the variation of stress time as shown in Figure 2, can be found out the growth along with stress time, and the drift of device is degenerated and increased.Existing NBTI measuring technology test structure commonly used is long raceway groove pMOSFET device, by at grid, applying negative bias, the mode of source leakage and the equal ground connection of substrate realizes the constant voltage homogeneous state of stress, the key parameter of device, as threshold voltage, drain saturation currents etc. change with stress time, after the some time, device parameters degradation failure is to certain critical value, as: 10%, now be defined as the out-of-service time of device under corresponding stress condition, as shown in figure as left as Fig. 3, V1, V2, V3 (V1>V2>V3) is the different stress condition of correspondence respectively, the corresponding component failure time is t1, t2, t3, meet t1<t2<t3.Can obtain the corresponding life-span of device under normal working voltage Vdd according to accelerating the stress model extrapolation, as shown in figure as right as Fig. 3.
Under the bias state of device in real work,, for simulation and radio frequency (RadioFrequency) application, be not particularly only to apply voltage on grid, often at drain terminal, applied voltage yet, therefore, only at grid, apply the duty that voltage stress can not fully reflect device.Prior art is not considered grid and drains to execute alive situation simultaneously, can not fully reflect the device actual working state.In addition, as shown in Figure 5, under identical grid voltage, when drain voltage is supply voltage, the degeneration of device, than large in existing homogeneous state of stress situation, therefore, has limited the life-span of device.Drain voltage is taken as supply voltage, has reflected the duty of pMOSFET device, and has not introduced extra stress.
Summary of the invention
(1) technical matters that will solve
The technical problem to be solved in the present invention is: the problem of pMOSFET device negative bias thermal instability life prediction under the NBTI stress condition.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of pMOSFET device negative bias thermal instability life-span prediction method, adopt the minimum channel length device under fabrication process condition to be tested, comprise the following steps:
S1: before the grid to described pMOSFET device applies negative bias stress, measure the initial characteristic of described pMOSFET device, obtain the initial device parameter;
S2: to the grid stress application condition of described pMOSFET device, drain voltage, for the normal operation supply voltage, carries out the stress burn-in test to this pMOSFET device within the default time interval simultaneously;
S3: described pMOSFET device is carried out to parameter testing, obtain the device parameters relevant to digestion time, until the overall stress time finishes;
S4: drain voltage is under the normal operation supply voltage, and repeating step S2 and S3, carry out the test of a plurality of different stress conditions, and the device parameters of take degenerates to critical point as benchmark, obtains the out-of-service time of pMOSFET device under corresponding stress condition;
S5: utilize the out-of-service time of the pMOSFET device under different stress conditions, the method by Data Extrapolation obtains grid voltage for the device reliability life-span under normal operation supply voltage condition.
Wherein, the described default time interval is less than 100000 seconds.
Wherein, described critical point is 90% of initial device parameter value.
(3) beneficial effect
The present invention is the bias state real work from device, has proposed a kind ofly in drain electrode, to apply normal power voltage, accelerates by the grid negative bias method that stress carries out pMOSFET prediction device lifetime simultaneously.This Forecasting Methodology is the bias state real work situation of proximity device more not only, and in the situation that identical grid stress, the component failure time is shorter than conventional method, the NBTI life-span that therefore more can reflect the pMOSFET device.In addition, reliability testing structure of the present invention is four end structures, is different from existing long ditch test component structure, and the test structure that the present invention adopts is the minimum channel length device under fabrication process condition, can on conventional semiconductor parametric tester, complete, save the testing apparatus cost.
The accompanying drawing explanation
Fig. 1 is the test component structural representation that method of the present invention adopts;
Fig. 2 is that the pMOSFET device is under NBTI stress, typical drain saturation current is with the variation diagram of stress time, wherein transverse axis is stress time, the variable quantity that the longitudinal axis is drain saturation current, with number percent, mean, article three, curve corresponds respectively to the result under different grid stress voltage conditions, and the grid stress voltage is higher, and the device degradation amount is larger;
Fig. 3 be the pMOSFET device under typical Constant Pressure Stress, device lifetime the Forecasting Methodology schematic diagram;
Fig. 4 is a kind of pMOSFET device negative bias thermal instability Reliabiltty Life Prediction method flow diagram of the embodiment of the present invention;
Fig. 5 is the short channel device Degenerate Graphs under grid and drain stress condition of the present invention, wherein transverse axis is stress time, the variable quantity that the longitudinal axis is drain saturation current, with number percent, mean, article two, curve corresponds respectively to the result under prior art and condition of the present invention, under identical grid voltage, when drain voltage is supply voltage, the amount of degradation of device is large;
Fig. 6 is the figure that predicts the outcome that utilizes the pMOSFET device reliability life-span of method in Fig. 4, wherein transverse axis is gate voltage, the longitudinal axis is the component failure time, square point is corresponding to the component failure time recorded under different stress conditions, in step S4, complete on stream, by Data Extrapolation, can obtain at gate voltage is the life-span in supply voltage 1V situation, is expressed as the intersection point of dotted line and the longitudinal axis, with round dot, means.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for the present invention is described, but are not used for limiting the scope of the invention.
This patent is the bias state real work from device, in conjunction with the short channel device structure, has proposed a kind ofly in drain electrode, to apply normal power voltage, accelerates by the grid negative bias method that stress carries out pMOSFET prediction device lifetime simultaneously.This Forecasting Methodology more real work situation of proximity device of not only setovering, and in the situation that identical grid stress, the component failure time is shorter than conventional method, the NBTI life-span that therefore more can reflect the pMOSFET device.This method adopts the short channel device structure, and as shown in Figure 1, wherein L, for short channel length, applies normal power voltage in drain electrode, the method for simultaneously by grid negative bias acceleration stress, carrying out pMOSFET prediction device lifetime.Idiographic flow as shown in Figure 4, comprising:
Step S1, before the grid to the pMOSFET device applies negative bias stress, measure the initial characteristic of pMOSFET device, obtains the initial device parameter, as leakage current Id0, threshold voltage vt h0 etc.
Step S2, to the grid stress application condition of pMOSFET device, drain voltage, for the normal operation supply voltage, carries out the stress burn-in test to this pMOSFET device within the default time interval simultaneously.
Step S3, carry out parameter testing to the pMOSFET device, obtains the device parameters relevant to digestion time, as: leakage current Id, threshold voltage vt h, until the end of overall stress time.
Step S4, drain voltage is under the normal operation supply voltage, and repeating step S2 and S3, carry out the test of a plurality of different stress conditions, and the device parameters of take degenerates to critical point as benchmark, obtains the out-of-service time of pMOSFET device under corresponding stress condition.
Step S5, utilize the out-of-service time of the pMOSFET device under different stress conditions, the prediction grid voltage is the device reliability life-span under normal operation supply voltage condition, and the method by Data Extrapolation obtains grid voltage for the device reliability life-span under normal operation supply voltage condition.
Experimental studies results also shows, under same gate stress condition, when drain terminal voltage is supply voltage Vdd, under identical stress time, the amount of degradation of device is large, as shown in Figure 5, drain voltage=0 (not making alive) is corresponding to traditional stress, drain voltage=-1V is the situation of supply voltage-1V corresponding to drain electrode, can find out that the component failure time obtained is shorter than conventional method, the NBTI life-span that therefore more can reflect the pMOSFET device.
Fig. 6 has provided and has utilized the inventive method experimental result in prediction pMOSFET device reliability life-span.Wherein transverse axis is gate voltage, the longitudinal axis is time device lifetime, square point is corresponding to the component failure time recorded under different stress conditions (with the corresponding result of the present invention of lines of closed square), in step S4, complete on stream, by Data Extrapolation, can obtain at gate voltage is the out-of-service time in the supply voltage situation, be expressed as the intersection point of dotted line and the longitudinal axis, with round dot, mean, the device that adopts Forecasting Methodology of the present invention to obtain is shorter than prior art normal working hours, becomes the life-span of limiting device normal operation.
Above embodiment is only for illustrating the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (3)
1. a pMOSFET device negative bias thermal instability life-span prediction method, is characterized in that, adopts the minimum channel length device under fabrication process condition to be tested, and comprises the following steps:
S1: before the grid to described pMOSFET device applies negative bias stress, measure the initial characteristic of described pMOSFET device, obtain the initial device parameter;
S2: to the grid stress application condition of described pMOSFET device, drain voltage, for the normal operation supply voltage, carries out the stress burn-in test to this pMOSFET device within the default time interval simultaneously;
S3: described pMOSFET device is carried out to parameter testing, obtain the device parameters relevant to digestion time, until the overall stress time finishes;
S4: drain voltage is under the normal operation supply voltage, and repeating step S2 and S3, carry out the test of a plurality of different stress conditions, and the device parameters of take degenerates to critical point as benchmark, obtains the out-of-service time of pMOSFET device under corresponding stress condition;
S5: utilize the out-of-service time of the pMOSFET device under different stress conditions, the method by Data Extrapolation obtains grid voltage for the device reliability life-span under normal operation supply voltage condition.
2. pMOSFET device negative bias thermal instability life-span prediction method as claimed in claim 1, is characterized in that, the described default time interval is less than 100000 seconds.
3. pMOSFET device negative bias thermal instability life-span prediction method as claimed in claim 1 or 2, is characterized in that, described critical point is 90% of initial device parameter value.
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| CN102680875B (en) * | 2012-03-14 | 2014-06-04 | 北京大学 | Method for isolating two reliability effects from SOI (silicon-on-insulator) PMOSFET (P-type metal-oxide-semiconductor field effect transistor) causing threshold value voltage shift |
| CN103424684B (en) * | 2012-05-24 | 2015-12-09 | 中芯国际集成电路制造(上海)有限公司 | The instable testing circuit of Bias Temperature and detection method |
| CN103792475B (en) * | 2012-11-02 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Negative Bias Temperature Instability testing circuit and detection method thereof |
| CN104142461B (en) * | 2013-05-09 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device aging test method |
| CN104122492B (en) * | 2014-07-24 | 2016-10-05 | 北京大学 | A kind of method predicting 10 year life-span of semiconductor devices corresponding operating voltage |
| CN107293501B (en) * | 2016-03-31 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Method and device for predicting high-temperature operation life of chip |
| CN106295009A (en) * | 2016-08-12 | 2017-01-04 | 江苏商贸职业学院 | A kind of circuit aging modeling method of PBTI based on electric charge capture releasing mechanism |
| CN108037438B (en) * | 2017-12-13 | 2020-10-09 | 中国科学院新疆理化技术研究所 | Method for testing influence of total dose irradiation on negative bias temperature instability of PMOSFET |
| CN111381139B (en) * | 2018-12-29 | 2022-04-26 | 长鑫存储技术有限公司 | Semiconductor device testing method and semiconductor device testing system |
| CN110045258A (en) * | 2019-03-26 | 2019-07-23 | 电子科技大学 | A kind of test method of the using pseudo-random sequence signal NBTI effect as voltage stress |
| CN110672943B (en) * | 2019-09-26 | 2022-11-08 | 宁波大学 | Aging detection sensor based on voltage comparator |
| CN110703066B (en) * | 2019-11-12 | 2021-11-12 | 云南电网有限责任公司电力科学研究院 | Method and system for predicting transistor failure |
| CN114019249B (en) * | 2021-10-15 | 2024-06-18 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | NBTI test method and device under ionizing radiation coupling |
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