CN103424684B - The instable testing circuit of Bias Temperature and detection method - Google Patents
The instable testing circuit of Bias Temperature and detection method Download PDFInfo
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- CN103424684B CN103424684B CN201210164995.6A CN201210164995A CN103424684B CN 103424684 B CN103424684 B CN 103424684B CN 201210164995 A CN201210164995 A CN 201210164995A CN 103424684 B CN103424684 B CN 103424684B
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Abstract
A kind of instable testing circuit of Bias Temperature and detection method, the instable testing circuit of described Bias Temperature comprises: odd number fundamental oscillation unit, and described fundamental oscillation unit comprises the first transistor, transistor seconds and first controls transistor, second and controls transistor, input end, output terminal; Third transistor between described adjacent fundamental oscillation unit, described fundamental oscillation unit and third transistor series connection form ring oscillator.Utilize the instable testing circuit of the Bias Temperature of the embodiment of the present invention, PMOS transistor can be detected respectively because the degree of threshold voltage degradation that causes of Negative Bias Temperature Instability and nmos pass transistor are because the degree of threshold voltage degradation that causes of positive bias temperature instability, and utilize third transistor, can amplifying mos transistor because the degree of threshold voltage degradation that causes of Bias Temperature instability, make final testing result sensitiveer, the precision of detection is higher.
Description
Technical field
The present invention relates to semiconductor detection technique, particularly the instable testing circuit of a kind of Bias Temperature and detection method.
Background technology
Along with the integrated level of SIC (semiconductor integrated circuit) is more and more higher, also day by day increase the requirement of transistor performance, therefore, the requirement for transistor reliability improves thereupon.The Bias Temperature instability of MOS transistor is the key factor affecting MOS transistor reliability, and described Bias Temperature instability comprises Negative Bias Temperature Instability and positive bias temperature instability.In existing CMOS technology, when the reliability for PMOS transistor is evaluated, Negative Bias Temperature Instability is a main factor of evaluation.Negative Bias Temperature Instability refers to that PMOS transistor is under the effect of negative bias grid voltage and high temperature, the hydrogen silicon bond rupture of the interface between the gate oxide of PMOS transistor and substrate, form boundary defect electric charge, thus cause the threshold voltage of PMOS transistor and saturated drain current that the phenomenon of drift occurs.
Along with the continuous reduction of the design node of integrated circuit, utilize metal gates to replace the Main way that traditional polysilicon gate has become microelectric technique development.The performance of metal gates can be subject to the impact of multiple charge defects, and wherein the oxygen vacancies of interstitial oxygen concentration atom and positively charged is very large on the instable impact of threshold voltage, and they easily catch the electronics in high-K gate dielectric layer and Si thus produce fast charging and discharging phenomenon.Adopt HfO
2easily cause threshold voltage to offset with the contour K dielectric material of HfSiO as gate dielectric layer material, utilize the nmos pass transistor of metal gates to be easily subject to the impact of positive bias temperature instability.Therefore, the positive bias temperature instability of pair nmos transistor is needed to carry out testing and analysis.
The patent No. is that the american documentation literature of US7504847B2 discloses the instable method of testing of a kind of negative temperature bias voltage, specifically comprise: to be applied to there is voltage stress stress device and parametric device on voltage be configured, and the gate source voltage of described parametric device is 0V, measure the source-drain current of described stress device and parametric device, judge that whether described stress device is because negative temperature bias voltage instability causes threshold voltage degradation.But utilize described negative temperature bias voltage instable method of testing precision lower.
In other prior aries, ring oscillator is also utilized to test the negative temperature bias voltage instability of PMOS transistor, please refer to Fig. 1, for the structural representation of the ring oscillator test circuit of prior art, described ring oscillator test circuit comprises the phase inverter 10,11,12 of three series connection, each phase inverter comprises a nmos pass transistor and a PMOS transistor, one end of described PMOS transistor connects operating voltage Vdd, one end ground connection of described nmos pass transistor, described nmos pass transistor is connected with the output terminal of phase inverter with the other end of PMOS transistor.Concrete method of testing comprises: disconnect the input end A1 of phase inverter 10 in test circuit and the output terminals A 2 of phase inverter 12, low level is applied to the input end A1 of phase inverter 10, the grid of the PMOS transistor of described phase inverter 10, phase inverter 12 is subject to low level, and the PMOS transistor of described phase inverter 10, phase inverter 12 can produce because negative temperature bias voltage instability causes threshold voltage degradation; The input end A1 of the phase inverter 10 in test circuit is connected with the output terminals A 2 of phase inverter 12, the phase inverter 10,11,12 of three series connection forms ring oscillator, by detecting the oscillation frequency before input end A1 applying low level with to the ring oscillator after input end A1 applying low level, the oscillation frequency rate variance of both utilizations judges that whether the PMOS transistor of described phase inverter 10, phase inverter 12 is because negative temperature bias voltage instability causes threshold voltage degradation.But along with the nmos pass transistor with metal gates is more and more general, when the grid structure of the nmos pass transistor in described phase inverter and PMOS transistor is metal gates, low level is applied to the input end A1 of phase inverter 10, the grid of the nmos pass transistor of described phase inverter 11 can be subject to high level, the nmos pass transistor of described phase inverter 11 also can cause threshold voltage degradation because of positive temperature bias instability, both can final oscillation frequency be impacted, make to judge described phase inverter 10 according to final oscillation frequency rate variance, the PMOS transistor of phase inverter 12 is because negative temperature bias voltage instability causes the degree of threshold voltage degradation.
Summary of the invention
The problem that the present invention solves is to provide a kind of high precision and can the instable testing circuit of Bias Temperature of independent detection and detection method.
For solving the problem, technical solution of the present invention provides the instable testing circuit of a kind of Bias Temperature, comprising:
Odd number fundamental oscillation unit, described fundamental oscillation unit comprises the first transistor, transistor seconds and first controls transistor, second and controls transistor, input end, output terminal, and the type that described the first transistor, first controls the channel region of transistor is contrary with the type that transistor seconds, second controls the channel region of transistor;
Described the first transistor is connected with input end with the grid of transistor seconds, and described first controls transistor is connected with control voltage end electricity with the second grid controlling transistor,
First end, first first end controlling transistor of described the first transistor are connected with the first voltage end electricity, and the second end, first second end controlling transistor of described the first transistor are connected with output terminal electricity,
The first end of described transistor seconds is connected with the second voltage end electricity, and the first end electricity that second end and second of described transistor seconds controls transistor is connected, and the described second the second end controlling transistor is connected with output terminal electricity;
Third transistor between described adjacent fundamental oscillation unit, the grid of described third transistor is connected with tertiary voltage end electricity, the first end of described third transistor is connected with the output terminal electricity of one of them fundamental oscillation unit, second end of described third transistor is connected with the input end electricity of another fundamental oscillation unit, and described fundamental oscillation unit and third transistor series connection form ring oscillator.
Optionally, the type of the channel region of described third transistor is identical with the type of the channel region of transistor seconds.
Optionally, utilize described tertiary voltage end that the channel region of third transistor is opened.
Optionally, it is PMOS transistor that described the first transistor, first controls transistor, it is nmos pass transistor that described transistor seconds, second controls transistor, and the voltage of described first voltage end is operating voltage, and the voltage of described second voltage end is no-voltage or negative bias.
Optionally, the grid of described transistor seconds is metal gates.
Optionally, it is nmos pass transistor that described the first transistor, first controls transistor, it is PMOS transistor that described transistor seconds, second controls transistor, and the voltage of described second voltage end is operating voltage, and the voltage of described first voltage end is no-voltage or negative bias.
Optionally, the grid of described transistor seconds is metal gates or polysilicon gate.
Optionally, described PMOS transistor is enhancement mode PMOS transistor or depletion type PMOS transistor, and described nmos pass transistor is enhancement mode nmos pass transistor or depletion type nmos transistor.
Optionally, utilize described control voltage end to control the first channel region and second controlling transistor control the channel region unlatching of transistor or close.
Technical solution of the present invention additionally provides a kind of detection method adopting the instable testing circuit of described Bias Temperature, comprising:
Applying the first control voltage at described control voltage end makes the channel region of the first control transistor open, second channel region controlling transistor is closed, make the grid of transistor seconds be applied with bias voltage, transistor seconds is because Bias Temperature instability causes threshold voltage degradation;
Applying the second control voltage at described control voltage end makes the channel region of the second control transistor open, and the first channel region controlling transistor is closed, and described ring oscillator normally works, and detects the detection frequency of ring oscillator;
According to the difference between the detection frequency of described ring oscillator and standard frequency, judge transistor seconds because Bias Temperature instability causes the degree of threshold voltage degradation.
Optionally, the difference DELTA f=k between the detection frequency of described ring oscillator and standard frequency
pΔ V
tHP+ k
nΔ V
tHN+ k
lΔ L, wherein said Δ V
tHPfor the changing value of the threshold voltage of PMOS transistor in the first transistor and transistor seconds, described Δ V
tHNfor the changing value of the threshold voltage of nmos pass transistor in the first transistor and transistor seconds, Δ L is the changing value of the length of channel region in MOS transistor, described k
p, k
n, k
lfor constant.
Optionally, when described the first transistor, first control transistor is PMOS transistor, described transistor seconds, second control transistor is nmos pass transistor, the voltage of described first voltage end is operating voltage, the voltage of described second voltage end is no-voltage or negative bias, described first control voltage is no-voltage or negative voltage, when described second control voltage is operating voltage, when described control voltage end applies the first control voltage, the output terminal of fundamental oscillation unit and the voltage of input end equal operating voltage, the grid of the first transistor and transistor seconds is made to be applied with operating voltage, make transistor seconds because positive bias temperature instability causes threshold voltage degradation, and according to the difference between the detection frequency of described ring oscillator and standard frequency, judge transistor seconds because positive bias temperature instability causes the degree of threshold voltage degradation.
Optionally, when described the first transistor, first control transistor is nmos pass transistor, described transistor seconds, second control transistor is PMOS transistor, the voltage of described second voltage end is operating voltage, the voltage of described first voltage end is no-voltage or negative bias, described first control voltage is operating voltage, described second control voltage be no-voltage or negative voltage time, when described control voltage end applies the first control voltage, the output terminal of fundamental oscillation unit and the voltage of input end equal zero voltage or negative bias, the grid of the first transistor and transistor seconds is made to be applied with no-voltage or negative bias, make transistor seconds because Negative Bias Temperature Instability causes threshold voltage degradation, and according to the difference between the detection frequency of described ring oscillator and standard frequency, judge transistor seconds because Negative Bias Temperature Instability causes the degree of threshold voltage degradation.
Compared with prior art, the present invention has the following advantages:
The instable testing circuit of Bias Temperature of the embodiment of the present invention comprises odd number fundamental oscillation unit and the third transistor between described adjacent fundamental oscillation unit, and described fundamental oscillation unit comprises the first transistor, transistor seconds and first controls transistor, second and controls transistor, input end, output terminal, described the first transistor is connected with input end with the grid of transistor seconds, described first controls transistor is connected with control voltage end electricity with the second grid controlling transistor, the first end of described the first transistor, first first end controlling transistor is connected with the first voltage end electricity, second end of described the first transistor, first the second end controlling transistor is connected with output terminal electricity, the first end of described transistor seconds is connected with the second voltage end electricity, the first end electricity that second end and second of described transistor seconds controls transistor is connected, described second the second end controlling transistor is connected with output terminal electricity, the ring oscillator formed owing to utilizing described fundamental oscillation unit can detect separately PMOS transistor or nmos pass transistor causes threshold voltage that the degree of degenerating occurs because of Bias Temperature instability, can not interfere with each other, and utilize described third transistor, energy amplifying mos transistor is because temperature bias instability causes the degree of threshold voltage degradation, make testing result sensitiveer, the precision detected is higher.
Further, when the type of the channel region of described third transistor is identical with the type of the channel region of transistor seconds, be all PMOS transistor or be all nmos pass transistor, can amplification detection result by a larger margin, the precision of detection is higher.
Accompanying drawing explanation
Fig. 1 is the structural representation of the ring oscillator test circuit of prior art;
Fig. 2 is the structural representation of the instable testing circuit of Bias Temperature of first embodiment of the invention;
Fig. 3 is the schematic flow sheet of the detection method of the instable testing circuit of Bias Temperature adopting first embodiment of the invention;
Fig. 4 is the structural representation of the instable testing circuit of Bias Temperature of second embodiment of the invention;
Fig. 5 is the schematic flow sheet of the detection method of the instable testing circuit of Bias Temperature adopting second embodiment of the invention.
Embodiment
Due to prior art to the instable method of testing of negative temperature bias voltage or precision lower, or when the grid of MOS transistor to be tested is metal gates, can not effectively test because negative temperature bias voltage instability causes the degree of threshold voltage degradation, inventor is through research, propose the instable testing circuit of a kind of Bias Temperature and detection method, the instable testing circuit of described Bias Temperature comprises: odd number fundamental oscillation unit, described fundamental oscillation unit comprises the first transistor, transistor seconds and first controls transistor, second controls transistor, input end, output terminal, described the first transistor is connected with input end with the grid of transistor seconds, described first controls transistor is connected with control voltage end electricity with the second grid controlling transistor, the first end of described the first transistor, first first end controlling transistor is connected with the first voltage end electricity, second end of described the first transistor, first the second end controlling transistor is connected with output terminal electricity, the first end of described transistor seconds is connected with the second voltage end electricity, the first end electricity that second end and second of described transistor seconds controls transistor is connected, described second the second end controlling transistor is connected with output terminal electricity, third transistor between described adjacent fundamental oscillation unit, the grid of described third transistor is connected with tertiary voltage end electricity, the first end of described third transistor is connected with the output terminal electricity of one of them fundamental oscillation unit, second end of described third transistor is connected with the input end electricity of another fundamental oscillation unit, and described fundamental oscillation unit and third transistor series connection form ring oscillator.
Utilize the instable testing circuit of the Bias Temperature of the embodiment of the present invention, when described the first transistor, the first control transistor are PMOS transistor, it is nmos pass transistor that described transistor seconds, second controls transistor, can detect the degree of the threshold voltage degradation that nmos pass transistor causes because of positive bias temperature instability; When described the first transistor, the first control transistor are nmos pass transistor, it is PMOS transistor that described transistor seconds, second controls transistor, the degree of the threshold voltage degradation that PMOS transistor causes because of Negative Bias Temperature Instability can be detected, and utilize third transistor, can amplifying mos transistor because the degree of threshold voltage degradation that causes of Bias Temperature instability, make final testing result sensitiveer, the precision of detection is higher.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
First embodiment
First embodiment of the invention provide firstly a kind of testing circuit of the positive bias temperature instability for detecting nmos pass transistor, please refer to Fig. 2, and the structural representation of the instable testing circuit of the Bias Temperature for the embodiment of the present invention, specifically comprises:
The fundamental oscillation unit 210 that odd number circuit structure is identical, wherein fundamental oscillation unit 210 comprises the first transistor 211, transistor seconds 212 and first controls transistor 213, second control transistor 214, input end 215, output terminal 216, it is PMOS transistor that described the first transistor 211, first controls transistor 213, and it is nmos pass transistor that described transistor seconds 212, second controls transistor 214;
Described the first transistor 211 is connected with input end 215 with the grid of transistor seconds 212, and described first controls transistor 213 is connected with control voltage end 240 electricity with the second grid controlling transistor 214,
First end, first first end controlling transistor 213 of described the first transistor 211 are connected with the first voltage end 250 electricity, and the second end, first second end controlling transistor 213 of described the first transistor 211 are connected with output terminal 216 electricity,
The first end of described transistor seconds 212 is connected with the second voltage end 260 electricity, the first end electricity that second end and second of described transistor seconds 212 controls transistor 214 is connected, and the described second the second end controlling transistor 214 is connected with output terminal 216 electricity;
Third transistor 220 between described adjacent fundamental oscillation unit 210, described third transistor 220 is nmos pass transistor, the grid of described third transistor 220 is connected with tertiary voltage end 230 electricity, the first end of described third transistor 220 is connected with output terminal 216 electricity of one of them fundamental oscillation unit, second end of described third transistor 220 is connected with input end 215 electricity of another fundamental oscillation unit, and described fundamental oscillation unit 210 and third transistor 220 are connected and formed ring oscillator.
Concrete, in fig. 2, the instable testing circuit of described Bias Temperature comprises the identical fundamental oscillation unit of 3 circuit structures 210 and is positioned at the third transistor 220 of adjacent two fundamental oscillation unit 210, and described fundamental oscillation unit 210, third transistor 220 are connected and end to end.In other embodiments, the instable testing circuit of described Bias Temperature comprises the identical fundamental oscillation unit of odd number circuit structure being greater than 3 and the third transistor being positioned at adjacent two fundamental oscillation unit, described fundamental oscillation unit, third transistor series connection and end to end.
Described the first transistor 211, transistor seconds 212 and first control transistor 213, second first end controlled in transistor 214, third transistor 220 to be source electrode in MOS transistor or to drain one of them, and it is source electrode in MOS transistor or drain electrode wherein another that described the first transistor 211, transistor seconds 212 and first control transistor 213, second the second end controlled in transistor 214, third transistor 220.
In the present embodiment, it is depletion type PMOS transistor that described the first transistor 211, first controls transistor 213, and it is enhancement mode nmos pass transistor that described transistor seconds 212, second controls transistor 214.The voltage that described first voltage end 250 applies is operating voltage, and described operating voltage is 1V, 1.2V, 1.5V or 1.8V etc.The voltage that described first voltage end applies corresponds to the noble potential of ring oscillator.Described second voltage end 260 ground connection, the voltage of described second voltage end 260 is no-voltage.In other embodiments, the voltage of described second voltage end 260 can also be negative voltage.The voltage of described second voltage end corresponds to the electronegative potential of ring oscillator.The voltage that described control voltage end 240 applies comprises operating voltage or no-voltage, when the voltage that control voltage end 240 applies is operating voltage, first channel region controlling transistor 213 is closed, second channel region controlling transistor 214 is opened, the voltage applied when described control voltage end 240 is no-voltage, first channel region controlling transistor 213 is opened, and the second channel region controlling transistor 214 is closed.Described third transistor 220 is nmos pass transistor, can be enhancement mode nmos pass transistor or depletion type nmos transistor, the voltage that described tertiary voltage end 230 applies is operating voltage, described operating voltage is 1V, 1.2V, 1.5V or 1.8V etc., makes the channel region of described third transistor 220 be in opening.
In other embodiments, it can also be enhancement mode PMOS transistor that described the first transistor 211, first controls transistor 213, and it can also be depletion type nmos transistor that described transistor seconds 212, second controls transistor 214.By configuring the first voltage end, second voltage end, tertiary voltage end, the voltage of control voltage end, the voltage of described first voltage end is made to correspond to the high level of ring oscillator, the voltage of described second voltage end corresponds to the low level of ring oscillator, the channel region that described tertiary voltage end can control the first control transistor is simultaneously closed, second channel region controlling transistor is opened, or control the channel region closedown that first controls transistor simultaneously, second channel region controlling transistor is opened, the voltage of described tertiary voltage end makes the channel region of third transistor be in opening.
The instable testing circuit of Bias Temperature of the present embodiment is for detecting the positive bias temperature instability of described transistor seconds 212, and the grid of described transistor seconds 212 is metal gates.Because the nmos pass transistor with metal gates is easily subject to the impact of positive bias temperature instability, therefore, the grid of the transistor seconds 212 of the embodiment of the present invention is metal gates.
In embodiments of the present invention, described third transistor 220 is nmos pass transistor, and in other embodiments, described third transistor also can be PMOS transistor.
First embodiment of the invention additionally provides a kind of detection method adopting the instable testing circuit of described Bias Temperature, please refer to Fig. 3, for adopting the schematic flow sheet of the testing process of the instable testing circuit of described Bias Temperature, specifically comprises:
Step S101, applying the first control voltage at described control voltage end makes the channel region of the first control transistor open, second channel region controlling transistor is closed, the output terminal of fundamental oscillation unit and the voltage of input end is made to equal operating voltage, make the grid of the first transistor and transistor seconds be applied with operating voltage, make transistor seconds because positive bias temperature instability causes threshold voltage degradation;
Step S102, applies the second control voltage at described control voltage end and the channel region of the second control transistor is opened, and the first channel region controlling transistor is closed, and described ring oscillator normally works, and detects the detection frequency of ring oscillator;
Step S103, according to the difference between the detection frequency of described ring oscillator and standard frequency, judges transistor seconds because positive bias temperature instability causes the degree of threshold voltage degradation.
Concrete, please refer to Fig. 2, the first control voltage is applied at described control voltage end 240, described first control voltage is no-voltage, i.e. described control voltage end 240 ground connection, the channel region of the first control transistor 213 is opened, second channel region controlling transistor 214 is closed, the voltage of output terminal 216 is approximately equal to the operating voltage on the first voltage end 250, and be in opening due to the channel region of third transistor 220, the voltage of the input end 215 of next fundamental oscillation unit is made also to be approximately operating voltage, the grid of the first transistor 211 in each fundamental oscillation unit and transistor seconds 212 is made to be applied with operating voltage.Because described the first transistor 211 is PMOS transistor, described transistor seconds 212 is nmos pass transistor, the grid of nmos pass transistor is subject to positive voltage for a long time can because positive bias temperature instability causes threshold voltage to be degenerated, threshold voltage and saturated drain current is caused to be drifted about, and along with grid, to be subject to the time absolute value that is longer, positive voltage of positive voltage larger, easier because positive bias temperature instability causes threshold voltage to be degenerated.Therefore, pair nmos transistor is needed because the degree that positive bias temperature instability causes threshold voltage to occur to degenerate detects.
Please refer to Fig. 2, the second control voltage is applied at described control voltage end 240, described second control voltage is operating voltage, such as 1V, 1.2V, 1.5V or 1.8V etc., the channel region of the first control transistor 213 is closed, second channel region controlling transistor 214 is opened, and the second end of described transistor seconds 212 is connected with output terminal 216 electricity, and described the first transistor 211, transistor seconds 212 form the phase inverter of a ring oscillator as shown in Figure 1.When the input end input high level of one of them fundamental oscillation unit 210, such as operating voltage, the input end of next fundamental oscillation unit 210 inputs a low level, such as no-voltage, quantity due to the fundamental oscillation unit 210 of ring oscillator is odd number, thus cause vibration, and detect the detection frequency of ring oscillator when vibrational stabilization.Owing to forming the first transistor 211 of phase inverter in the present embodiment, transistor seconds 212 is only had to be subject to Bias Temperature instability in transistor seconds 212, therefore the oscillation frequency of ring oscillator changes mainly by transistor seconds 212(NMOS transistor) be subject to threshold voltage that positive bias temperature instability causes and source-drain current and change and cause, other factors are not had to disturb, thus the degree that can be changed by the oscillation frequency of ring oscillator judges nmos pass transistor because positive bias temperature instability causes threshold voltage that the degree of degenerating occurs.
Because the described detection frequency recorded occurs to record when degenerating at the threshold voltage of transistor seconds 212, described detection frequency and the threshold voltage of transistor seconds 212 do not occur to have certain difference compared with the standard frequency that records when degenerating, inventor finds through research, the difference DELTA f=k between the detection frequency of described ring oscillator and standard frequency
pΔ V
tHP+ k
nΔ V
tHN+ k
lΔ L, wherein said Δ V
tHPfor the changing value of the threshold voltage of PMOS transistor in the first transistor and transistor seconds, described Δ V
tHNfor the changing value of the threshold voltage of nmos pass transistor in the first transistor and transistor seconds, Δ L is the changing value of the length of channel region in MOS transistor, described k
p, k
n, k
lfor constant, relevant to the circuit structure of ring oscillator, and along with the increase of fundamental oscillation element number, described k
p, k
n, k
lalso can increase thereupon.
Inventor also finds through research, a MOS transistor is added between every two fundamental oscillation circuit of ring oscillator, wherein one end in the source-drain electrode of described MOS transistor is connected with the output terminal of a fundamental oscillation circuit, wherein the other end is connected with the input end of another fundamental oscillation circuit, utilize described MOS transistor, can k be made
p, k
n, k
lthe absolute value of three constants increases, the difference between the detection frequency of described ring oscillator and standard frequency can be made to increase, the degree of the threshold voltage degradation that nmos pass transistor causes because of positive bias temperature instability can be amplified, make final testing result sensitiveer, the precision of detection is higher.Please refer to table 1, is the k that the ring oscillator with third transistor of the embodiment of the present invention is corresponding with not having the ring oscillator of third transistor
p, k
n, k
lthe comparison sheet of three constants.
| Ring oscillator type | k P | k N | k L |
| There is no third transistor | -0.038 | -0.035 | -0.026 |
| Third transistor is PMOS transistor | -0.24 | -0.052 | -0.085 |
| Third transistor is nmos pass transistor | -0.054 | -0.34 | -0.029 |
Table 1
As seen from the table, between every two fundamental oscillation circuit of ring oscillator, add a MOS transistor and can significantly improve k
p, k
nthe absolute value of these two constants, and the difference DELTA f between the detection frequency of described ring oscillator and standard frequency can be made to increase, can amplifying mos transistor because the degree of threshold voltage degradation that causes of Bias Temperature instability, make final testing result sensitiveer, the precision of detection is higher.
Owing to working as described k
p, k
n, k
lwhen three constants are determined, in the changing value of threshold voltage of the detection frequency of described ring oscillator and PMOS transistor main to the difference between standard frequency, the changing value of the threshold voltage of nmos pass transistor, MOS transistor, the length of grid is relevant, transistor seconds 212(NMOS transistor in the embodiment of the present invention) the threshold voltage impact that is easily subject to positive bias temperature instability change, and the length of channel region can not change in the threshold voltage of PMOS transistor, MOS transistor, therefore in the present embodiment, Δ f ≈ k
nΔ V
tHN.K corresponding during owing to not having a third transistor
nfor-0.035, and there is third transistor and third transistor is nmos pass transistor time corresponding k
nfor-0.34, the difference DELTA f between the detection frequency of described ring oscillator and standard frequency can be improved greatly, the degree of the threshold voltage degradation that nmos pass transistor causes because of positive bias temperature instability can be amplified.In other embodiments, due to k corresponding when third transistor is PMOS transistor
nfor-0.052, be k corresponding when not having third transistor
nbe worth 1.5 times, also can amplify the degree of the threshold voltage degradation that nmos pass transistor causes because of positive bias temperature instability.
By recording the difference between the detection frequency of described ring oscillator and standard frequency, just can obtain the changing value of the threshold voltage of nmos pass transistor, thus the degree of the threshold voltage degradation that the nmos pass transistor of described transistor seconds causes because of positive bias temperature instability can be judged.
Second embodiment
Second embodiment of the invention provides a kind of testing circuit of the Negative Bias Temperature Instability for detecting PMOS transistor, please refer to Fig. 4, and the structural representation of the instable testing circuit of the Bias Temperature for the embodiment of the present invention, specifically comprises:
The fundamental oscillation unit 310 that odd number circuit structure is identical, wherein fundamental oscillation unit 310 comprises the first transistor 311, transistor seconds 312 and first controls transistor 313, second control transistor 314, input end 315, output terminal 316, it is nmos pass transistor that described the first transistor 311, first controls transistor 313, and it is PMOS transistor that described transistor seconds 312, second controls transistor 314;
Described the first transistor 311 is connected with input end 315 with the grid of transistor seconds 312, and described first controls transistor 313 is connected with control voltage end 340 electricity with the second grid controlling transistor 314,
First end, first first end controlling transistor 313 of described the first transistor 311 are connected with the first voltage end 350 electricity, and the second end, first second end controlling transistor 313 of described the first transistor 311 are connected with output terminal 316 electricity,
The first end of described transistor seconds 312 is connected with the second voltage end 360 electricity, the first end electricity that second end and second of described transistor seconds 312 controls transistor 314 is connected, and the described second the second end controlling transistor 314 is connected with output terminal 316 electricity;
Third transistor 320 between described adjacent fundamental oscillation unit 310, described third transistor 320 is PMOS transistor, the grid of described third transistor 320 is connected with tertiary voltage end 330 electricity, the first end of described third transistor 320 is connected with output terminal 316 electricity of one of them fundamental oscillation unit, second end of described third transistor 320 is connected with input end 315 electricity of another fundamental oscillation unit, and described fundamental oscillation unit 310 and third transistor 320 are connected and formed ring oscillator.
Concrete, in the diagram, the instable testing circuit of described Bias Temperature comprises the identical fundamental oscillation unit of 3 circuit structures 310 and is positioned at the third transistor 320 of adjacent two fundamental oscillation unit 310, and described fundamental oscillation unit 310, third transistor 320 are connected and end to end.In other embodiments, the instable testing circuit of described Bias Temperature comprises the identical fundamental oscillation unit of odd number circuit structure being greater than 3 and the third transistor being positioned at adjacent two fundamental oscillation unit, described fundamental oscillation unit, third transistor series connection and end to end.
Described the first transistor 311, transistor seconds 312 and first control transistor 313, second first end controlled in transistor 314, third transistor 320 to be source electrode in MOS transistor or to drain one of them, and it is source electrode in MOS transistor or drain electrode wherein another that described the first transistor 311, transistor seconds 312 and first control transistor 313, second the second end controlled in transistor 314, third transistor 320.
In the present embodiment, it is enhancement mode nmos pass transistor that described the first transistor 311, first controls transistor 313, and it is depletion type PMOS transistor that described transistor seconds 312, second controls transistor 314.The voltage that described second voltage end 360 applies is operating voltage, and described operating voltage is 1V, 1.2V, 1.5V or 1.8V etc.The voltage that described second voltage end applies corresponds to the noble potential of ring oscillator.Described first voltage end 350 ground connection, the voltage of described first voltage end 350 is no-voltage.In other embodiments, the voltage of described first voltage end 350 can also be negative voltage.The voltage of described first voltage end corresponds to the electronegative potential of ring oscillator.The voltage that described control voltage end 340 applies comprises operating voltage or no-voltage, when the voltage that control voltage end 340 applies is operating voltage, first channel region controlling transistor 313 is opened, second channel region controlling transistor 314 is closed, the voltage applied when described control voltage end 340 is no-voltage, first channel region controlling transistor 313 is closed, and the second channel region controlling transistor 314 is opened.Described third transistor 320 is PMOS transistor, can be enhancement mode PMOS transistor or depletion type PMOS transistor, and the voltage that described tertiary voltage end 330 applies is no-voltage or negative voltage, makes the channel region of described third transistor 320 be in opening.
In other embodiments, it can also be depletion type nmos transistor that described the first transistor 311, first controls transistor 313, and it can also be enhancement mode PMOS transistor that described transistor seconds 312, second controls transistor 314.By configuring the first voltage end, second voltage end, tertiary voltage end, the voltage of control voltage end, the voltage of described first voltage end is made to correspond to the low level of ring oscillator, the voltage of described second voltage end corresponds to the high level of ring oscillator, the channel region that described tertiary voltage end can control the first control transistor is simultaneously closed, second channel region controlling transistor is opened, or control the channel region closedown that first controls transistor simultaneously, second channel region controlling transistor is opened, the voltage of described tertiary voltage end makes the channel region of third transistor be in opening.
The instable testing circuit of Bias Temperature of the present embodiment is for detecting the Negative Bias Temperature Instability of described transistor seconds 312, and the grid of described transistor seconds 312 is metal gates or polysilicon gate.Because the PMOS transistor with metal gates or polysilicon gate is easily subject to the impact of Negative Bias Temperature Instability, therefore, the grid of the transistor seconds 312 of the embodiment of the present invention is metal gates or polysilicon gate.
In embodiments of the present invention, described third transistor 320 is PMOS transistor, and in other embodiments, described third transistor also can be nmos pass transistor.
Second embodiment of the invention additionally provides a kind of detection method adopting the instable testing circuit of described Bias Temperature, please refer to Fig. 5, for adopting the schematic flow sheet of the testing process of the instable testing circuit of described Bias Temperature, specifically comprises:
Step S201, applying the first control voltage at described control voltage end makes the channel region of the first control transistor open, second channel region controlling transistor is closed, the output terminal of fundamental oscillation unit and the voltage of input end are equalled zero voltage, make the grid of the first transistor and transistor seconds be applied with no-voltage, make transistor seconds because Negative Bias Temperature Instability causes threshold voltage degradation;
Step S202, applies the second control voltage at described control voltage end and the channel region of the second control transistor is opened, and the first channel region controlling transistor is closed, and described ring oscillator normally works, and detects the detection frequency of ring oscillator;
Step S203, according to the difference between the detection frequency of described ring oscillator and standard frequency, judges transistor seconds because Negative Bias Temperature Instability causes the degree of threshold voltage degradation.
Concrete, please refer to Fig. 4, the first control voltage is applied at described control voltage end 340, described first control voltage is operating voltage, such as 1V, 1.2V, 1.5V or 1.8V etc., the channel region of the first control transistor 313 is opened, second channel region controlling transistor 314 is closed, the voltage of output terminal 316 is approximately equal to the no-voltage on the first voltage end 350, and be in opening due to the channel region of third transistor 320, the voltage of the input end 315 of next fundamental oscillation unit is made also to be approximately no-voltage, the grid of the first transistor 311 in each fundamental oscillation unit and transistor seconds 312 is made to be applied with operating voltage.Because described the first transistor 311 is nmos pass transistor, described transistor seconds 312 is PMOS transistor, the grid of PMOS transistor is subject to negative bias for a long time can because Negative Bias Temperature Instability causes threshold voltage to be degenerated, threshold voltage and saturated drain current is caused to be drifted about, and along with grid, to be subject to the time absolute value that is longer, negative bias of negative bias larger, easier because positive bias temperature instability causes threshold voltage to be degenerated.Therefore, pair pmos transistor is needed because the degree that Negative Bias Temperature Instability causes threshold voltage to occur to degenerate detects.
In other embodiments, when the voltage on described first voltage end 350 is negative voltage, the output terminal 316 of fundamental oscillation unit and the voltage of input end 315 is made to equal negative voltage, the grid of the first transistor 311 and transistor seconds 312 is made to be applied with negative voltage, make grid be subject to larger negative bias, more easily make transistor seconds 312 because Negative Bias Temperature Instability causes threshold voltage degradation.
Please refer to Fig. 4, the second control voltage is applied at described control voltage end 340, described second control voltage is no-voltage or negative voltage, the channel region of the first control transistor 313 is closed, second channel region controlling transistor 314 is opened, second end of described transistor seconds 312 is connected with output terminal 316 electricity, and described the first transistor 311, transistor seconds 312 form the phase inverter of a ring oscillator as shown in Figure 1.When the input end input high level of one of them fundamental oscillation unit 310, such as operating voltage, the input end of next fundamental oscillation unit 310 inputs a low level, such as no-voltage, quantity due to the fundamental oscillation unit 210 of ring oscillator is odd number, thus cause vibration, and detect the detection frequency of ring oscillator when vibrational stabilization.Owing to forming the first transistor 311 of phase inverter in the present embodiment, transistor seconds 312 is only had to be subject to Bias Temperature instability in transistor seconds 312, therefore the oscillation frequency of ring oscillator changes mainly by transistor seconds 312(PMOS transistor) be subject to threshold voltage that Negative Bias Temperature Instability causes and source-drain current and change and cause, other factors are not had to disturb, thus the degree that can be changed by the oscillation frequency of ring oscillator judges PMOS transistor because Negative Bias Temperature Instability causes threshold voltage that the degree of degenerating occurs.
Because the described detection frequency recorded occurs to record when degenerating at the threshold voltage of transistor seconds 312, described detection frequency and the threshold voltage of transistor seconds 312 do not occur compared with the standard frequency that records when degenerating, can because the threshold voltage of PMOS transistor occurs degenerate thus have certain difference.Due to the difference DELTA f=k between the detection frequency of described ring oscillator and standard frequency
pΔ V
tHP+ k
nΔ V
tHN+ k
lΔ L.Owing to working as described k
p, k
n, k
lwhen three constants are determined, in the changing value of threshold voltage of the detection frequency of described ring oscillator and PMOS transistor main to the difference between standard frequency, the changing value of the threshold voltage of nmos pass transistor, MOS transistor, the length of grid is relevant, transistor seconds 312(PMOS transistor in the embodiment of the present invention) the threshold voltage impact that is easily subject to Negative Bias Temperature Instability change, and the length of channel region can not change in the threshold voltage of nmos pass transistor, MOS transistor, therefore in the present embodiment, Δ f ≈ k
pΔ V
tHP.
Please refer to table 1, k corresponding during owing to not having a third transistor
pfor-0.038, and there is third transistor and third transistor is PMOS transistor time corresponding k
pfor-0.24, the difference DELTA f between the detection frequency of described ring oscillator and standard frequency can be improved greatly, can amplify the degree of the threshold voltage degradation that PMOS transistor causes because of Negative Bias Temperature Instability, make final testing result sensitiveer, the precision of detection is higher.In other embodiments, due to k corresponding when third transistor is nmos pass transistor
nfor-0.054, be approximately k corresponding when not having third transistor
n1.5 times that are worth, also can amplify the degree of the threshold voltage degradation that PMOS transistor causes because of Negative Bias Temperature Instability.
By recording the difference between the detection frequency of described ring oscillator and standard frequency, just can obtain the changing value of the threshold voltage of PMOS transistor, thus the degree of the threshold voltage degradation that the PMOS transistor of described transistor seconds causes because of Negative Bias Temperature Instability can be judged.
To sum up, the instable testing circuit of Bias Temperature of the embodiment of the present invention comprises odd number fundamental oscillation unit and the third transistor between described adjacent fundamental oscillation unit, and described fundamental oscillation unit comprises the first transistor, transistor seconds and first controls transistor, second and controls transistor, input end, output terminal, described the first transistor is connected with input end with the grid of transistor seconds, described first controls transistor is connected with control voltage end electricity with the second grid controlling transistor, the first end of described the first transistor, first first end controlling transistor is connected with the first voltage end electricity, second end of described the first transistor, first the second end controlling transistor is connected with output terminal electricity, the first end of described transistor seconds is connected with the second voltage end electricity, the first end electricity that second end and second of described transistor seconds controls transistor is connected, described second the second end controlling transistor is connected with output terminal electricity, the ring oscillator formed owing to utilizing described fundamental oscillation unit can detect separately PMOS transistor or nmos pass transistor causes threshold voltage that the degree of degenerating occurs because of Bias Temperature instability, can not interfere with each other, and utilize described third transistor, energy amplifying mos transistor is because temperature bias instability causes the degree of threshold voltage degradation, make testing result sensitiveer, the precision detected is higher.
Further, when the type of the channel region of described third transistor is identical with the type of the channel region of transistor seconds, be all PMOS transistor or be all nmos pass transistor, can amplification detection result by a larger margin, the precision of detection is higher.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (4)
1. adopt a detection method for the instable testing circuit of Bias Temperature, it is characterized in that,
The instable testing circuit of described Bias Temperature comprises:
Odd number fundamental oscillation unit, described fundamental oscillation unit comprises the first transistor, transistor seconds and first controls transistor, second and controls transistor, input end, output terminal, and the type that described the first transistor, first controls the channel region of transistor is contrary with the type that transistor seconds, second controls the channel region of transistor;
Described the first transistor is connected with input end with the grid of transistor seconds, and described first controls transistor is connected with control voltage end electricity with the second grid controlling transistor,
First end, first first end controlling transistor of described the first transistor are connected with the first voltage end electricity, and the second end, first second end controlling transistor of described the first transistor are connected with output terminal electricity,
The first end of described transistor seconds is connected with the second voltage end electricity, and the first end electricity that second end and second of described transistor seconds controls transistor is connected, and the described second the second end controlling transistor is connected with output terminal electricity;
Third transistor between adjacent fundamental oscillation unit, the grid of described third transistor is connected with tertiary voltage end electricity, the first end of described third transistor is connected with the output terminal electricity of one of them fundamental oscillation unit, second end of described third transistor is connected with the input end electricity of another fundamental oscillation unit, and described fundamental oscillation unit and third transistor series connection form ring oscillator and also comprise:
Applying the first control voltage at described control voltage end makes the channel region of the first control transistor open, second channel region controlling transistor is closed, make the grid of transistor seconds be applied with bias voltage, transistor seconds is because Bias Temperature instability causes threshold voltage degradation;
Applying the second control voltage at described control voltage end makes the channel region of the second control transistor open, and the first channel region controlling transistor is closed, and described ring oscillator normally works, and detects the detection frequency of ring oscillator;
According to the difference between the detection frequency of described ring oscillator and standard frequency, judge transistor seconds because Bias Temperature instability causes the degree of threshold voltage degradation.
2. detection method as claimed in claim 1, is characterized in that, the difference DELTA f=k between the detection frequency of described ring oscillator and standard frequency
pΔ V
tHP+ k
nΔ V
tHN+ k
lΔ L, wherein said Δ V
tHPfor the changing value of the threshold voltage of PMOS transistor in the first transistor and transistor seconds, described Δ V
tHNfor the changing value of the threshold voltage of nmos pass transistor in the first transistor and transistor seconds, Δ L is the changing value of the length of channel region in MOS transistor, described k
p, k
n, k
lfor constant.
3. detection method as claimed in claim 1, it is characterized in that, when described the first transistor, first control transistor is PMOS transistor, described transistor seconds, second control transistor is nmos pass transistor, the voltage of described first voltage end is operating voltage, the voltage of described second voltage end is no-voltage or negative bias, described first control voltage is no-voltage or negative voltage, when described second control voltage is operating voltage, when described control voltage end applies the first control voltage, the output terminal of fundamental oscillation unit and the voltage of input end equal operating voltage, the grid of the first transistor and transistor seconds is made to be applied with operating voltage, make transistor seconds because positive bias temperature instability causes threshold voltage degradation, and according to the difference between the detection frequency of described ring oscillator and standard frequency, judge transistor seconds because positive bias temperature instability causes the degree of threshold voltage degradation.
4. detection method as claimed in claim 1, it is characterized in that, when described the first transistor, first control transistor is nmos pass transistor, described transistor seconds, second control transistor is PMOS transistor, the voltage of described second voltage end is operating voltage, the voltage of described first voltage end is no-voltage or negative bias, described first control voltage is operating voltage, described second control voltage be no-voltage or negative voltage time, when described control voltage end applies the first control voltage, the output terminal of fundamental oscillation unit and the voltage of input end equal zero voltage or negative bias, the grid of the first transistor and transistor seconds is made to be applied with no-voltage or negative bias, make transistor seconds because Negative Bias Temperature Instability causes threshold voltage degradation, and according to the difference between the detection frequency of described ring oscillator and standard frequency, judge transistor seconds because Negative Bias Temperature Instability causes the degree of threshold voltage degradation.
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| CN106597246A (en) * | 2016-11-30 | 2017-04-26 | 上海华力微电子有限公司 | Bias temperature instability testing structure and bias temperature instability testing method |
| CN109975679B (en) * | 2017-12-14 | 2021-06-08 | 中芯国际集成电路制造(上海)有限公司 | BTI performance test circuit of MOSFET and test method based on BTI performance test circuit |
| US10715115B2 (en) * | 2018-09-28 | 2020-07-14 | Qualcomm Incorporated | Circuits and methods for preventing bias temperature instability |
| CN110610871B (en) * | 2019-08-21 | 2021-09-14 | 中国科学院微电子研究所 | Metal gate temperature measuring method |
| CN111812485A (en) * | 2020-06-10 | 2020-10-23 | 西安电子科技大学 | Early warning method and circuit for aging failure of integrated circuit |
| CN114639610B (en) * | 2020-12-15 | 2024-06-07 | 长鑫存储技术有限公司 | Process corner detection circuit and process corner detection method |
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