CN102262206A - Method for predicting negative bias temperature instability (NBTI) service life of pMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) device - Google Patents
Method for predicting negative bias temperature instability (NBTI) service life of pMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) device Download PDFInfo
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Abstract
The invention discloses a method for predicting a negative bias temperature instability (NBTI) service life of a pMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) device. The method comprises the following steps of: S1, before applying negative bias stress, measuring initial characteristics of the pMOSFET device to obtain initial parameters of the device; S2, applying a stress condition to a grid of the device, wherein drain voltage is normal working voltage; performing stress aging test to the device within a pre-set time interval; S3, testing the parameters of the device to obtain device parameters related to the aging time until the total stress time is ended; S4, when the drain voltage is the normal working voltage, repeating the steps S2 and S3; testing different stress conditions; referencing to the device parameters retrograded to a critical point; obtaining failure times of the pMOSFET device under the relative stress conditions; and S5, using the failure times of the pMOSFET device under the different stress conditions, predicting the reliability service life of the device when the gate voltage is the normal working voltage. Because the failure time of the device obtained by the method in the invention is shorter than that obtained by the conventional method, the NBTI service life of the pMOSFET device can be well reflected.
Description
Technical field
The present invention relates to MOS device reliability technical field, particularly a kind of pMOSFET device negative bias thermal instability life-span prediction method.
Background technology
Along with the develop rapidly of semiconductor technology and the significantly raising of microelectronic chip integrated level, integrated circuit (IC) design and level of processing have entered the nanometer MOS epoch, the appearance of surface channel device, the superthin grid oxide layer of the attenuate of device oxidated layer thickness and the high nitrogen-containing that adopted for suppressor leakage current and boron penetration effects, caused the oxide layer electric field to increase, make negative bias thermal instability (Negative Bias Temperature Instability, NBTI), reliability degradation failure becomes the main integrity problem of current limiting device scaled down, and is particularly outstanding in the pMOSFET device.Conventional method of testing is carried out under long channel device, high temperature and homogeneous state of stress condition, draws the pMOSFET device reliability life-span by the acceleration electric stress test prediction of carrying out on reliability testing structure.
When the pMOSFET device under NBTI reliability stress, the degeneration of device mainly shows as the drift of Primary Component parameters such as threshold voltage, drain saturation current, mutual conductance, in case the key parameter of device floats to a certain degree, the normal operating conditions of pMOSFET device will not exist, and finally can cause the inefficacy of integrated circuit.In normal operation, the degeneration of NBTI is an accumulative process slowly in the life cycle of whole integrated circuit, therefore, must be for the sign that the NBTI of silicon chip level pMOSFET device degenerates by means of the acceleration stress of short time, test structure synoptic diagram commonly used as shown in Figure 1, test structure is a four-terminal device that comprises source electrode, grid, drain electrode and substrate, and wherein W and L represent the channel width and the channel length of device respectively.Typical drain saturation current with the variation of stress time as shown in Figure 2, along with the growth of stress time, the drift of device is degenerated and is increased as can be seen.Existing NBTI measuring technology test structure commonly used is long raceway groove pMOSFET device, the mode of source leakage and the equal ground connection of substrate realizes the constant voltage homogeneous state of stress by applying negative bias at grid, the key parameter of device, as threshold voltage, drain saturation currents etc. change with stress time, through after the some time, device parameters degradation failure is to certain critical value, as: 10%, be defined as the out-of-service time of device under the corresponding stress condition this moment, shown in the left figure of Fig. 3, V1, V2, V3 (V1＞V2＞V3) distinguish corresponding different stress conditions, the corresponding component failure time is t1, t2, t3 satisfies t1＜t2＜t3.Can obtain the pairing life-span of device under the normal working voltage Vdd according to quickening the stress model extrapolation, shown in the right figure of Fig. 3.
Under the bias state of device in real work, particularly using for simulation and radio frequency (RadioFrequency), is not only to apply voltage on grid, has often applied voltage at drain terminal yet, therefore, only apply the duty that voltage stress can not fully reflect device at grid.Prior art does not consider that grid and drain electrode apply voltage condition simultaneously, can not fully reflect the device actual working state.In addition, as shown in Figure 5, under identical grid voltage, when drain voltage was supply voltage, therefore the degeneration of device, had limited the life-span of device than big under the existing homogeneous state of stress situation.Drain voltage is taken as supply voltage, has reflected the duty of pMOSFET device, and has not introduced extra stress.
Summary of the invention
(1) technical matters that will solve
The technical problem to be solved in the present invention is: the problem of pMOSFET device negative bias thermal instability life prediction under the NBTI stress condition.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of pMOSFET device negative bias thermal instability life-span prediction method, adopt the minimum channel length device under the fabrication process condition to test, may further comprise the steps:
S1: before the grid to described pMOSFET device applies negative bias stress, measure the initial characteristic of described pMOSFET device, obtain the initial device parameter;
S2: to the grid stress application condition of described pMOSFET device, drain voltage is the operate as normal supply voltage simultaneously, in the default time interval this pMOSFET device is carried out the stress burn-in test;
S3: described pMOSFET device is carried out parameter testing, obtain the device parameters relevant, finish until the overall stress time with digestion time;
S4: drain voltage is under the operate as normal supply voltage, and repeating step S2 and S3 carry out the test of a plurality of different stress conditions, and degenerating to critical point with device parameters is benchmark, obtains the out-of-service time of pMOSFET device under the corresponding stress condition;
S5: utilize the out-of-service time of the pMOSFET device under the different stress conditions, it is device reliability life-span under the operate as normal supply voltage condition that the method by data extrapolations obtains grid voltage.
Wherein, the described default time interval was less than 100000 seconds.
Wherein, described critical point is 90% of an initial device parameter value.
(3) beneficial effect
The present invention is from the bias state of device real work, proposed a kind ofly to apply normal power voltage in drain electrode, quickens stress by the grid negative bias simultaneously and carries out pMOSFET forecast method device lifetime.Not only bias state is more near the real work situation of device for this Forecasting Methodology, and under the situation of identical grid stress, component failure time ratio conventional method is shorter, therefore the NBTI life-span that more can reflect the pMOSFET device.In addition, reliability testing structure of the present invention is four end structures, is different from existing long ditch test component structure, and the test structure that the present invention adopts is the minimum channel length device under the fabrication process condition, can on conventional semiconductor parametric tester, finish, save the testing apparatus cost.
Description of drawings
Fig. 1 is the test component structural representation that method of the present invention adopts;
Fig. 2 is that the pMOSFET device is under NBTI stress, typical drain saturation current is with the variation diagram of stress time, wherein transverse axis is a stress time, the longitudinal axis is the variable quantity of drain saturation current, represent with number percent, article three, curve corresponds respectively to the result under the different grid stress voltage conditions, and the grid stress voltage is high more, and the device degradation amount is big more;
Fig. 3 be the pMOSFET device under typical Constant Pressure Stress, device lifetime the Forecasting Methodology synoptic diagram;
Fig. 4 is a kind of pMOSFET device negative bias thermal instability reliable life Forecasting Methodology process flow diagram of the embodiment of the invention;
Fig. 5 is the short channel device degeneration figure under grid and drain stress condition of the present invention, wherein transverse axis is a stress time, the longitudinal axis is the variable quantity of drain saturation current, represent with number percent, article two, curve corresponds respectively to the result under prior art and the condition of the present invention, under identical grid voltage, when drain voltage was supply voltage, the amount of degradation of device was big;
Fig. 6 is the pMOSFET device reliability Life Prediction figure as a result that utilizes method among Fig. 4, wherein transverse axis is a gate voltage, the longitudinal axis is the component failure time, square point is corresponding to the component failure time that records under the different stress conditions, in step S4, finish on stream, can obtain at gate voltage by data extrapolations is life-span under the supply voltage 1V situation, is expressed as the intersection point of the dotted line and the longitudinal axis, represents with round dot.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used to illustrate the present invention, but are not used for limiting the scope of the invention.
This patent is from the bias state of device real work, in conjunction with the short channel device structure, proposed a kind ofly to apply normal power voltage in drain electrode, quickens stress by the grid negative bias simultaneously and carries out pMOSFET forecast method device lifetime.This Forecasting Methodology is not only setovered more near the real work situation of device, and under the situation of identical grid stress, component failure time ratio conventional method is shorter, therefore the NBTI life-span that more can reflect the pMOSFET device.This method adopts the short channel device structure, and as shown in Figure 1, wherein L applies normal power voltage for short channel length in drain electrode, carries out pMOSFET forecast method device lifetime by grid negative bias acceleration stress simultaneously.Idiographic flow comprises as shown in Figure 4:
Step S1 before the grid to the pMOSFET device applies negative bias stress, measures the initial characteristic of pMOSFET device, obtains the initial device parameter, as leakage current Id0, threshold voltage vt h0 etc.
Step S2, to the grid stress application condition of pMOSFET device, drain voltage is the operate as normal supply voltage simultaneously, in the default time interval this pMOSFET device is carried out the stress burn-in test.
Step S3 carries out parameter testing to the pMOSFET device, obtains the device parameters relevant with digestion time, as: leakage current Id, threshold voltage vt h, finished until the overall stress time.
Step S4, drain voltage are under the operate as normal supply voltage, and repeating step S2 and S3 carry out the test of a plurality of different stress conditions, and degenerating to critical point with device parameters is benchmark, obtains the out-of-service time of pMOSFET device under the corresponding stress condition.
Step S5, utilize the out-of-service time of the pMOSFET device under the different stress conditions, the prediction grid voltage is device reliability life-span under the operate as normal supply voltage condition, and promptly to obtain grid voltage be device reliability life-span under the operate as normal supply voltage condition to the method by the data extrapolation.
Experimental studies results also shows, under same gate stress condition, when drain terminal voltage is supply voltage Vdd, under the identical stress time, the amount of degradation of device is big, as shown in Figure 5, drain voltage=0 (not making alive) is corresponding to traditional stress, drain voltage=-1V be the situation of supply voltage-1V corresponding to drain electrode, can find out that the component failure time ratio conventional method that obtains is shorter, so the NBTI life-span that more can reflect the pMOSFET device.
Fig. 6 has provided and has utilized the inventive method experimental result in prediction pMOSFET device reliability life-span.Wherein transverse axis is a gate voltage, the longitudinal axis is time device lifetime, square point is corresponding to the component failure time that records under the different stress conditions (the corresponding result of the present invention of the lines of band closed square), in step S4, finish on stream, can obtain at gate voltage by data extrapolations is out-of-service time under the supply voltage situation, be expressed as the intersection point of the dotted line and the longitudinal axis, represent with round dot, the device that adopts Forecasting Methodology of the present invention to obtain is shorter than prior art normal working hours, becomes the life-span of limiting device operate as normal.
Above embodiment only is used to illustrate the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; under the situation that does not break away from the spirit and scope of the present invention; can also make various variations and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (3)
1. a pMOSFET device negative bias thermal instability life-span prediction method is characterized in that, adopts the minimum channel length device under the fabrication process condition to test, and may further comprise the steps:
S1: before the grid to described pMOSFET device applies negative bias stress, measure the initial characteristic of described pMOSFET device, obtain the initial device parameter;
S2: to the grid stress application condition of described pMOSFET device, drain voltage is the operate as normal supply voltage simultaneously, in the default time interval this pMOSFET device is carried out the stress burn-in test;
S3: described pMOSFET device is carried out parameter testing, obtain the device parameters relevant, finish until the overall stress time with digestion time;
S4: drain voltage is under the operate as normal supply voltage, and repeating step S2 and S3 carry out the test of a plurality of different stress conditions, and degenerating to critical point with device parameters is benchmark, obtains the out-of-service time of pMOSFET device under the corresponding stress condition;
S5: utilize the out-of-service time of the pMOSFET device under the different stress conditions, it is device reliability life-span under the operate as normal supply voltage condition that the method by data extrapolations obtains grid voltage.
2. pMOSFET device negative bias thermal instability life-span prediction method as claimed in claim 1 is characterized in that the described default time interval was less than 100000 seconds.
3. pMOSFET device negative bias thermal instability life-span prediction method as claimed in claim 1 or 2 is characterized in that described critical point is 90% of an initial device parameter value.
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Cited By (13)
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|---|---|---|---|---|
| CN102680875A (en) * | 2012-03-14 | 2012-09-19 | 北京大学 | Method for isolating two reliability effects from SOI (silicon-on-insulator) PMOSFET (P-type metal-oxide-semiconductor field effect transistor) causing threshold value voltage shift |
| CN103424684A (en) * | 2012-05-24 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Bias voltage temperature instability detection circuit and detection method |
| CN103792475A (en) * | 2012-11-02 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Negative-bias-temperature-instability detection circuit and detection method thereof |
| CN104122492A (en) * | 2014-07-24 | 2014-10-29 | 北京大学 | Method for predicting work voltage of service life of semiconductor device |
| CN104142461A (en) * | 2013-05-09 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device aging test method |
| CN106295009A (en) * | 2016-08-12 | 2017-01-04 | 江苏商贸职业学院 | A kind of circuit aging modeling method of PBTI based on electric charge capture releasing mechanism |
| CN107293501A (en) * | 2016-03-31 | 2017-10-24 | 中芯国际集成电路制造(上海)有限公司 | Method and device for predicting the chip high-temperature operation life-span |
| CN108037438A (en) * | 2017-12-13 | 2018-05-15 | 中国科学院新疆理化技术研究所 | The test method that a kind of total dose irradiation influences PMOSFET Negative Bias Temperature Instabilities |
| CN110045258A (en) * | 2019-03-26 | 2019-07-23 | 电子科技大学 | A kind of test method of the using pseudo-random sequence signal NBTI effect as voltage stress |
| CN110672943A (en) * | 2019-09-26 | 2020-01-10 | 宁波大学 | Aging detection sensor based on voltage comparison |
| CN110703066A (en) * | 2019-11-12 | 2020-01-17 | 云南电网有限责任公司电力科学研究院 | Method and system for predicting transistor failure |
| CN111381139A (en) * | 2018-12-29 | 2020-07-07 | 长鑫存储技术有限公司 | Semiconductor device testing method and semiconductor device testing system |
| CN114019249A (en) * | 2021-10-15 | 2022-02-08 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | NBTI test method and device under coupling of ionizing radiation |
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Cited By (20)
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| CN102680875A (en) * | 2012-03-14 | 2012-09-19 | 北京大学 | Method for isolating two reliability effects from SOI (silicon-on-insulator) PMOSFET (P-type metal-oxide-semiconductor field effect transistor) causing threshold value voltage shift |
| CN102680875B (en) * | 2012-03-14 | 2014-06-04 | 北京大学 | Method for isolating two reliability effects from SOI (silicon-on-insulator) PMOSFET (P-type metal-oxide-semiconductor field effect transistor) causing threshold value voltage shift |
| CN103424684A (en) * | 2012-05-24 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Bias voltage temperature instability detection circuit and detection method |
| CN103424684B (en) * | 2012-05-24 | 2015-12-09 | 中芯国际集成电路制造(上海)有限公司 | The instable testing circuit of Bias Temperature and detection method |
| CN103792475A (en) * | 2012-11-02 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Negative-bias-temperature-instability detection circuit and detection method thereof |
| CN103792475B (en) * | 2012-11-02 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Negative Bias Temperature Instability testing circuit and detection method thereof |
| CN104142461A (en) * | 2013-05-09 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device aging test method |
| CN104122492A (en) * | 2014-07-24 | 2014-10-29 | 北京大学 | Method for predicting work voltage of service life of semiconductor device |
| CN104122492B (en) * | 2014-07-24 | 2016-10-05 | 北京大学 | A kind of method predicting 10 year life-span of semiconductor devices corresponding operating voltage |
| CN107293501A (en) * | 2016-03-31 | 2017-10-24 | 中芯国际集成电路制造(上海)有限公司 | Method and device for predicting the chip high-temperature operation life-span |
| CN107293501B (en) * | 2016-03-31 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Method and device for predicting high-temperature operation life of chip |
| CN106295009A (en) * | 2016-08-12 | 2017-01-04 | 江苏商贸职业学院 | A kind of circuit aging modeling method of PBTI based on electric charge capture releasing mechanism |
| CN108037438A (en) * | 2017-12-13 | 2018-05-15 | 中国科学院新疆理化技术研究所 | The test method that a kind of total dose irradiation influences PMOSFET Negative Bias Temperature Instabilities |
| CN111381139A (en) * | 2018-12-29 | 2020-07-07 | 长鑫存储技术有限公司 | Semiconductor device testing method and semiconductor device testing system |
| CN111381139B (en) * | 2018-12-29 | 2022-04-26 | 长鑫存储技术有限公司 | Semiconductor device testing method and semiconductor device testing system |
| CN110045258A (en) * | 2019-03-26 | 2019-07-23 | 电子科技大学 | A kind of test method of the using pseudo-random sequence signal NBTI effect as voltage stress |
| CN110672943A (en) * | 2019-09-26 | 2020-01-10 | 宁波大学 | Aging detection sensor based on voltage comparison |
| CN110703066A (en) * | 2019-11-12 | 2020-01-17 | 云南电网有限责任公司电力科学研究院 | Method and system for predicting transistor failure |
| CN110703066B (en) * | 2019-11-12 | 2021-11-12 | 云南电网有限责任公司电力科学研究院 | Method and system for predicting transistor failure |
| CN114019249A (en) * | 2021-10-15 | 2022-02-08 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | NBTI test method and device under coupling of ionizing radiation |
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