CN102194650B - Method for evaluating efficiency of processes for improving negative bias temperature instability effect - Google Patents
Method for evaluating efficiency of processes for improving negative bias temperature instability effect Download PDFInfo
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Abstract
The invention provides a method for evaluating the efficiency of processes for improving the negative bias temperature instability effect, which comprises the following steps of: (1) respectively implementing a plurality of different processes for improving the negative bias temperature instability effect on a plurality of first semiconductor devices with the same parameters; (2) applying same stress to the first semiconductor devices for a period of time; (3) judging whether the first semiconductor devices reach a rejection value, and returning to the step (2) if the first semiconductor devices do not reach the rejection value, stopping applying stress to the first semiconductor devices if the semiconductor devices reach the rejection value, and going to the step (4); and (4) selecting the process for improving the negative bias temperature instability effect, applied to the first semiconductor device which last reaches the rejection value, as the optimal process from the multiple processes.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly for estimating the method for improving temperature instability under minus bias pressure effect technological effect.
Background technology
In recent ten years, semi-conductor industry, with unusual speed development, is obtaining huge achievement aspect integrated circuit production.At present, can produce high performance SOC(system level chip) product.Along with semiconductor technology enters into the sub-micro level, some key issues have influence on the production of semiconductor circuit, comprising the NBTI(temperature instability under minus bias pressure) effect, device is applied to a series of phenomenons that occur under negative grid voltage and temperature stress condition
The NBTI effect is the key factor that affects the cmos device reliability.The PMOSFET caused by the NBTI effect degenerates becomes the principal element that affects device lifetime gradually.It degenerates more serious than the NMOSFET life-span of being caused by hot carrier (HC) effect.The NBTI effect is to cause by (usually being greater than 100 degrees centigrade) under high temperature the PMOSFET grid being applied to certain back bias voltage.All may run in device aging and the course of work in this case, show as saturation current I
dsatwith constantly reducing of mutual conductance Gm, threshold voltage shift △ V
thconstantly increase, sub-threshold slope such as constantly reduces at the variation of device parameters.It may increase the signal delay in sequence circuit, thereby causes timing drift.In analog integrated circuit, particularly, in the application of some parameter matching, the circuit working condition can apply asymmetrical bias pressure to the transistor of coupling, thereby causes obvious parameter mismatch.This will cause degenerating of performance of semiconductor device under the reduction of rate of finished products in ageing process and condition of work.
In recent years, semi-conductor industry bound pair NBTI effect problem has given the concern of height, and the NBTI effect has become one of integrity problem that current CMOS technology is the most serious.Because being is interrupted the increase of the electric charge at the interface caused because of the Si-H key, cause the generation of NBTI effect, therefore can manage to introduce other and can usually replace H with the unit of the higher bond energy of Si formation, as deuterium, the Si-D bond energy formed is high, interrupted than the Si-H key is more difficult, thereby can be reduced the increase of interface charge under bias voltage.The element that also has other same function, such as fluorine.In addition, also can the NBTI effect be improved by the state of controlling oxide layer.The defect of oxide layer is directly related with the NBTI effect.Mainly can obtain silicon/oxide layer interface state and oxide layer performance preferably by the technique of carrying out preliminary treatment and control growth oxide layer before the growth oxide layer on technique.These techniques of improving the NBTI effect are widely used in industry.
Judge that any technological effect that improves the NBTI effect is more better, need to be detected corresponding sample.Therefore, carry out the test of device accelerated aging significant to cmos device.Accelerated test device lifetime refers under HTHP the test to the device properties, with the assessment device method in useful life at normal temperatures and pressures.
At first to some, there is the sample of same parameter to adopt different technique to improve the NBTI effect, then carry out the life test of sample, the sample of longest-lived is best sample, and the corresponding process conditions of this sample are the process conditions of improving NBTI effect the best.Take the PMOS device as example, adopt three samples, existing improved detect the semiconductor device life-span after NBTI effect technique method as shown in Figure 1.
As shown in Figure 1, the method for existing test NBTI effect is chosen the sample that some have same parameter, for example sample 1, sample 2 and sample 3, and these samples all have identical reference parameter, and for example each sample all has identical I
dsat(saturation current).These samples are implemented to different technique to improve its NBTI effect.Sample 1, sample 2 and sample 3 are applied to a period of time t
1stress.What the stress here should refer to that the external world applies can accelerate the means that sample is aging, for example, by the grid voltage V of PMOS device
gbe adjusted into-2V.Then three samples are tested observation Δ I separately
dsatvalue, wherein Δ I
dsatrefer to I
dsatdrift value, calculate Δ I now
dsat/ I
dsatwhether reach rejection value, the value that the rejection value is here scrapped for the artificial semiconductor device of setting.The sample that will not reach afterwards rejection value applies a period of time t
2stress, then immediately sample is carried out to same test, test Δ I
dsat, calculate Δ I now
dsat/ I
dsatwhether reach rejection value; The sample that will not reach rejection value applies an end time t
3stress, then immediately to sample test Δ I
dsatso circulation is t up to the stress application time
sthe time, then immediately sample is tested, until all samples are all scrapped.Now, observe the longest-lived of which sample, the process conditions that can judge the corresponding NBTI of improvement of respective sample are optimum condition.
This existing detection method, draw formula P(t)=A * t
-nin A and the value of n, A representative be the factor relevant to technique, the n representative be the accelerated factor that the NBTI effect is degenerated, t is the time of stress application, is P(t) the drift degree of reference parameter, for example Δ I described above
dsat/ I
dsat, can know by calculating the life-span t ' of semiconductor device after the technique of implementing to improve the NBTI effect after like this.For example, judge in the time of, known P(t ')=10% that this semiconductor device scraps, can pass through
learn the size of t ', change the life-span of semiconductor device after can obtaining implementing improving the technique of NBTI effect, and needn't again be measured it.
But this existing to be improved the method that detects the semiconductor device life-span after NBTI effect technique accurate not, it is wrong likely causing last testing result, correspondingly causes P(t)=A * t
-nthere is certain problem in formula, and the t ' value calculated is accurate not.If used the testing result of this mistake, used the technique of the corresponding NBTI of the improvement effect of wrong testing result, it is best can not really effectively finding out which kind of process conditions, be unfavorable for like this improvement of semiconductor device technology, and adopt technique corresponding to error result can reduce the overall performance of semiconductor device, reduce yields, make product not there is competitiveness.Therefore, need a kind of new method, can accurately estimate the effect of improving NBTI effect technique, in order to improve the performance of device integral body, improve the yields of semiconductor device.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order accurately to estimate the effect of improving NBTI effect technique, the present invention proposes a kind ofly for estimating the method for improving temperature instability under minus bias pressure effect technological effect, comprise the following steps: a: a plurality of the first semiconductor device with identical parameters are implemented respectively to described a plurality of different technique of improving the temperature instability under minus bias pressure effect; B: the identical stress of size that described the first semiconductor device is applied to a period of time t; C: judge whether described the first semiconductor device arrives rejection value P(t), when described the first semiconductor device does not arrive described rejection value P(t) time, return to step b; When described the first semiconductor device arrives described rejection value P(t) time stops, to described the first semiconductor device stress application, entering steps d; D: choose for arriving the latest described rejection value P(t) technique of improving the temperature instability under minus bias pressure effect that the first semiconductor device applies is the optimum process in described a plurality of technique; Wherein, described rejection value P(t)=Δ T(t)/T, the value that T is the reference parameter described step a after, described the first semiconductor device measured immediately, Δ T(t) be to the value T ' of the reference parameter of described the first semiconductor device measurement and the difference of T after described step b.
Preferably, also comprise,
E: the time that described the first semiconductor device of choosing in steps d is arrived to described rejection value was set as for the first life-span, described the first life-span is compared with the first preset value, if described the first life-span is less than the first preset value, reselect the technique of improving the temperature instability under minus bias pressure effect, and return to step a.
Preferably, also comprise,
E: be set as for the first life-span by choosing the time that described the first semiconductor device arrives described rejection value in steps d, described the first life-span is compared with the first preset value, if described the first life-span is not less than the first preset value, enter step f; F: provide with steps d in described the first semiconductor device of choosing there is identical parameters and implemented the second semiconductor device of described optimum process; G: the parameter that described the second semiconductor device has been drifted about after described optimum process adjusts back to without the parameter before optimum process; H: described the second semiconductor device stress application, to detect the life-span, is obtained to the second life-span; I: described the second life-span and the second preset value are compared, if described the second life-span is less than the second preset value, reselect the technique of improving the temperature instability under minus bias pressure effect, and return to step a; If described the second life-span is not less than described the second preset value, described the second semiconductor device is qualified.
The method employing ion implantation technology of preferably, recalling to described parameter in wherein said step g is carried out.
Preferably, the saturation current I that wherein said reference parameter is semiconductor device
dsat.
Preferably, the threshold voltage V that wherein said reference parameter is semiconductor device
th.
Preferably, wherein said rejection value is set as 10%.
The invention allows for a kind of life detecting method for having applied the semiconductor device that improves temperature instability under minus bias pressure effect technique, it is characterized in that, adopt following formula to calculate the life-span t of semiconductor device:
t=10
D，
Wherein
α=(1-P wherein
0/ P
tar)
-m, described P(t) and be rejection value, described A is the factor relevant to technique, and described n is the accelerated factor that the temperature instability under minus bias pressure effect is degenerated, and described t is the time of stress application, and m is the factor relevant to concrete technology, 0≤m≤1; P
0to implement the described numerical value that improves the parameter of semiconductor device after temperature instability under minus bias pressure effect technique, P
tarrepresentative implement described improve semiconductor device before temperature instability under minus bias pressure effect technique the numerical value of parameter.
Preferably, it is characterized in that, work as P
0=P
tarthe time, described m=0.
Preferably, the saturation current I that wherein said parameter is semiconductor device
dsat.
Preferably, the threshold voltage V that wherein said parameter is semiconductor device
th.
Preferably, wherein said rejection value is set as 10%.
The present invention is Promethean considers the drift value of the reference parameter after the technique of implementing to improve the NBTI effect, make when evaluation improves effect, can judge more exactly which kind of process conditions is as the technique optimum condition of improving the NBTI effect, avoid the impact of drift value on estimating of reference parameter; In like manner, during the life-span, also more accurate at calculating device.
The accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 detects the method schematic diagram in semiconductor device life-span after the existing NBTI of being improved effect technique;
Fig. 2 is that the embodiment according to one aspect of the invention is improved after NBTI effect technique the method schematic diagram that detects the semiconductor device life-span;
The method new according to the employing of the embodiment of the present invention that show Fig. 3 detects the schematic diagram that improves the semiconductor device life-span after the NBTI effect.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, detailed step will be proposed in following description, in order to illustrate how the present invention adopts new method to detect to carry out semiconductor device life-span after NBTI effect improving technique.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet, except these are described in detail, the present invention can also have other execution modes.
Improve after the technique of NBTI effect the coarse problem that detects the semiconductor device life-span in order to overcome existing enforcement, the drift value that the present invention proposes will improve other parameter that NBTI effect technique causes by enforcement at initial detection-phase takes into account.
As described below according to an embodiment of one aspect of the invention.
At first to three various parameter same sample, sample 4, sample 5, sample 6 are implemented different technique to improve the NBTI effect, such as ion injection method etc., then carry out the life test of sample.It is pointed out that in the actual industrial production application, must only to three samples, be detected, during detection, the quantity of sample is unrestricted, according to industrial requirements, determine, and be only three samples here by way of example.
As shown in Figure 2, implement to improve after the technique of NBTI effect for the embodiment according to one aspect of the invention the method that detects the semiconductor device life-span.To having implemented to improve three samples that various parameters are identical of NBTI effect technique, for example sample 4, sample 5 and sample 6 carry out the test of device accelerated aging.For example, sample 4, sample 5 and sample 6 are applied to a period of time t
1identical stress, these samples all have identical reference parameter, for example each sample all has identical I
dsat.Detect I separately
after dsat(t
1), and calculate P(t
1)=Δ I (t
1)/I
after dsat, i.e. the first comparison value P(t
1) whether arriving rejection value, rejection value is the parameter value that the semiconductor device of artificial setting is scrapped.It is to be noted the I here
after dsatfor sample being implemented to improve the I measured immediately after NBTI effect technique
dsatvalue, but not the original I improved before NBTI effect technique
before dsatvalue.Wherein, Δ I (t
1) for applying a period of time t
1identical stress after current I
after dsat(t
1) value and I
after dsatdifference, i.e. Δ I (t
1)
after=I
after dsat-I
after dsat(t
1); The sample that does not arrive rejection value is continued to apply a period of time t
2identical stress, then immediately to sample test I
after dsat(t
2), calculate P(t
2)=Δ I (t
2)/I
after dsat, i.e. the second comparison value P(t
2) whether arrive rejection value, the Δ I (t here
2) for applying a period of time t
2identical stress after current I
after dsat(t
2) value and I
after dsatdifference, i.e. Δ I (t
2)=I
after dsat-I
after dsat(t
2); The sample that does not arrive rejection value is continued to apply an end time t
3identical stress, then immediately sample is tested to Δ I (t
3) ... so circulation is t up to the stress application time
sthe time, s is integer and s>=1 herein, then immediately to sample test I
after dsat(t
s), calculate P(t
s)=Δ I (t
s)/I
after dsat, i.e. s comparison value P(t
s) whether arrive rejection value, wherein Δ I (t
s) for applying a period of time t
sidentical stress after current I
dsat after(t
s) value and I
after dsatdifference, i.e. Δ I (t
s)=I
after dsat-I
after dsat(t
s).When all samples all arrive rejection value, i.e. the P(t of all samples
s) all reaching rejection value, in the present embodiment, rejection value is set as 10%, observes this three sample t separately
svalue, choose the sample of last arrival rejection value, i.e. the sample of s maximum, this sample has the optimum process condition that improves the NBTI effect.This be in example for sample 4, i.e. the longest-lived of sample 4, the process conditions of sample 4 are to improve the optimum process condition of NBTI effect.
If adopt existing means to be detected these three samples, as shown in Figure 1, first adopt existing means of testing to be tested, do not consider the drift value of other parameter, for example, by after sample (sample 1, sample 2 and the sample 3) stress application that utilizes different process to be improved the NBTI effect and make, here sample 1 adopts identical technique with sample 4, and sample 2 adopts identical technique with sample 5, and sample 3 adopts identical technique with sample 6.Test result in this example shows the longest-lived of sample 3, can assert that the technique that sample 3 adopts is to improve the optimum process condition of NBTI effect.Clearly, the detected result of this existing means is inaccurate.
According to the result of the present embodiment, show, adopting method of the present invention can more accurately judge which kind of process conditions is to improve the technique optimum condition of NBTI effect.This be due to, after implementing to improve the technique of NBTI effect, can impact other parameter, cause these parameters that drift in various degree, for example reference parameter I occur
dsatthe value of departing from objectives, desired value herein is the value of reference parameter while not implementing to improve the technique of NBTI effect.And traditional handicraft is not taken into account the drift of these reference parameters when detecting, cause the result of detection inaccurate.The present invention all takes into account the drift value of these reference parameters, so just can judge more exactly which kind of process conditions is as the technique optimum condition of improving the NBTI effect, thereby can be applied to better in actual industrial, be conducive to the progress of semiconductor technology, improve the overall performance of semiconductor device, improve yields.
According to the present invention, adopt new formula to calculate to implement the life-span improve the semiconductor device after NBTI effect technique, i.e. formula P(t)=A ' * t
-n=(α * A) * t
-n, α=(1-P wherein
0/ P
tar)
-m, P
0representative implements to improve I after NBTI effect technique
after dsatnumerical value, P
tarrepresentative implements to improve the front I of NBTI effect technique
dsatnumerical value, the I reached in actual industrial
dsatnumerical value.Through the too much measurement of group sample, can obtain empirical A, n that different process is corresponding and the value of m.What A represented is the factor relevant to technique, and what n represented is the accelerated factor that the NBTI effect is degenerated, and t is the time of stress application, and m is the factor relevant to concrete technology, and P especially, is worked as in 0≤m≤1
0=P
tarthe time, m=0.After, just can calculate according to this formula the life value of the corresponding sample of corresponding technique, and not need equally being tested described in above-described embodiment for another example.It is pointed out that the P(t here) do not refer in particular to as Δ I
dsat/ I
after dsat, in the same way, i.e. P(t)=Δ T(t)/T, wherein, T is for sample being implemented to improve the value of the reference parameter of measuring immediately after NBTI effect technique, but not the original value of being improved the reference parameter before NBTI effect technique; Δ T(t) be the value T ' that applies current reference parameter after the identical stress of a period of time t difference with T, i.e. Δ I
dsat=T-T '.For example, P(t) can also be V
ththe drift degree of (threshold voltage), i.e. Δ V
th(t)/V
after thnumerical value, P correspondingly
0representative be to implement to improve V after NBTI effect technique
after thnumerical value, P
tarrepresentative implements to improve the front V of NBTI effect technique
thnumerical value, the V reached in actual industrial
thnumerical value.Utilize the method adopted in embodiment, can calculate formula P(t)=A ' * t
-n=(α * A) * t
-nin the value of all parameters except t, like this as the people for setting rejection value P(t ') value the time, can calculate the life-span t ' of corresponding semiconductor device, i.e. t '=10
d, wherein
α=(1-P wherein
0/ P
tar)
-m.
The life value that the life value calculated like this is realistic, can more accurately react the life-span of being improved the semiconductor device after the NBTI effect.
The method new according to the employing of the embodiment of the present invention that show the flow chart of Fig. 3 detects the schematic diagram that improves the semiconductor device life-span after the NBTI effect.In step 301, a plurality of the first samples with identical parameters are implemented respectively to a plurality of different technique of improving the temperature instability under minus bias pressure effect.In step 302, the identical stress of size that these first samples are applied to a period of time t, what this stress should refer to that the external world applies can accelerate the means that sample is aging.In step 303, the first sample and rejection value are compared, judge whether the first sample reaches rejection value.When the first sample does not arrive rejection value, return to step 302; When arriving rejection value, the first sample stops, to the first sample device stress application, entering step 304.In step 304, to choose for the first sample that arrives the latest rejection value, its life-span is the first life-span t
1, by the first life-span t
1compare value when the first preset value is herein scrapped for the artificial sample of setting with the first preset value.If the first life-span t
1be less than the first preset value, return to step 301, the first sample first step is defective, reselects the technique of improving the temperature instability under minus bias pressure effect; If the first life-span t
1be not less than the first preset value, the first sample first step is qualified, proceeds to step 305.In step 305, provide and there is the first life-span t
1the first sample there is identical parameters and implemented the second sample of described optimum process, the reference parameter that the second sample has been drifted about after described optimum process, as I
dsator V
thdeng, adjusting back to not the parameter of implementing to improve before NBTI technique, this process can adopt carries out as techniques such as Implantations.In step 306, the second sample is applied to the life-span that identical stress detects sample.Now the life-span of the second sample is the second life-span t in setting
2, by the second life-span t
2compare the value that the second preset value herein reaches while scrapping for the artificial sample of setting with the second preset value.If the second life-span t
2be less than the second preset value, the second sample second step is defective, returns to step 301, reselects the technique of improving the temperature instability under minus bias pressure effect; If the second life-span t
2be not less than the second preset value, the second sample second step is qualified, proceeds to step 307.In step 307, the second sample is qualified.Can select identical with the second sample parameters in actual industrial and implement the semiconductor device of the identical technique of improving the NBTI effect.
It is to be noted, the first sample of choosing or the second sample can be a plurality of, at this time can be in step 304 and step 306 time used and preset value be relatively when detecting the first sample in a group or the second sample and scrap the sample of certain percentage, if be less than the first preset value or the second preset value, continue to implement to improve the technique of NBTI effect, otherwise, proceed to next step.This is due in actual industrial, even have the semiconductor device of identical parameters, has implemented the identical NBTI technique of improving and does not also have the identical life-span.For example, choose 100 the first samples in step 304, simultaneously these 100 the first sample stress applications, can choose wherein 50 times that the first sample is scrapped, with the first preset value, compare, if be less than the first preset value, the first sample first step is defective; Otherwise, proceed to next step.
Showing the method new according to the employing of the embodiment of the present invention according to the employing of embodiment manufacture as above detects and improves the semiconductor device of semiconductor device life-span method after the NBTI effect and can be applicable in multiple integrated circuit (IC).According to IC of the present invention, be for example memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.According to IC of the present invention, can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the purpose for giving an example and illustrating just, but not is intended to the present invention is limited in described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. one kind for estimating the method for improving temperature instability under minus bias pressure effect technological effect, comprises the following steps:
A: a plurality of the first semiconductor device with identical parameters are implemented respectively to a plurality of different technique of improving the temperature instability under minus bias pressure effect;
B: the identical stress of size that described the first semiconductor device is applied to a period of time t;
C: the drift degree P(t that judges the reference parameter of described the first semiconductor device) whether arrive rejection value, as the drift degree P(t of the reference parameter of described the first semiconductor device) while not arriving described rejection value, return to step b; Drift degree P(t when the reference parameter of described the first semiconductor device) while arriving described rejection value, stop, to described the first semiconductor device stress application, entering steps d;
D: choose for described P(t) arriving the latest the technique of improving the temperature instability under minus bias pressure effect that the first semiconductor device of described rejection value applies is the optimum process in a plurality of described technique; Wherein, described P(t)=Δ T(t)/T, the value that T is the described reference parameter described step a after, described the first semiconductor device measured immediately, Δ T(t) be to the value T ' of the described reference parameter of described the first semiconductor device measurement and the difference of described T after described step b;
E: by the described P(t of described the first semiconductor device of choosing in steps d) time that arrives described rejection value is set as the first life-span t
1, by described the first life-span t
1with the first preset value, compare, if described the first life-span t
1be less than described the first preset value, reselect the technique of improving the temperature instability under minus bias pressure effect, and return to step a, if described the first life-span t
1be not less than described the first preset value, enter step f;
F: provide with steps d in described the first semiconductor device of choosing there is identical parameters and implemented the second semiconductor device of described optimum process;
G: the parameter that described the second semiconductor device has been drifted about after described optimum process adjusts back to without the parameter before optimum process;
H: described the second semiconductor device stress application, to detect the life-span, is obtained to the second life-span t
2; And
I: by described the second life-span t
2with the second preset value, compare, if described the second life-span t
2be less than described the second preset value, reselect the technique of improving the temperature instability under minus bias pressure effect, and return to step a; If described the second life-span t
2be not less than described the second preset value, described the second semiconductor device is qualified.
2. the method for claim 1, recall to the method employing ion implantation technology of described parameter and carry out in wherein said step g.
3. as arbitrary described method in claim 1-2, the saturation current I that wherein said reference parameter is semiconductor device
dsat.
4. as arbitrary described method in claim 1-2, the threshold voltage V that wherein said reference parameter is semiconductor device
th.
5. the method for claim 1, wherein said rejection value is set as 10%.
6. the method for claim 1, wherein adopt following formula to calculate the life-span t ' of described semiconductor device, and described life-span t ' comprises described the first life-span t
1with described the second life-span t
2:
t’=10
D，
Wherein
α=(1-P wherein
0/ P
tar)
-m, described P(t ') and be rejection value, described A is the factor relevant to technique, and described n is the accelerated factor that the temperature instability under minus bias pressure effect is degenerated, and described t is the time of stress application, and m is the factor relevant to concrete technology, 0≤m≤1; P
0to implement the described numerical value that improves the parameter of semiconductor device after temperature instability under minus bias pressure effect technique, P
tarthe described numerical value that improves the parameter of the front semiconductor device of temperature instability under minus bias pressure effect technique is implemented in representative.
7. method according to claim 6, is characterized in that, works as P
0=P
tarthe time, described m=0.
8. method as claimed in claim 6, the saturation current I that wherein said parameter is semiconductor device
dsat.
9. method as claimed in claim 6, the threshold voltage V that wherein said parameter is semiconductor device
th.
10. method as claimed in claim 6, wherein said rejection value is set as 10%.
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| CN104091770B (en) * | 2014-07-25 | 2017-06-23 | 上海华力微电子有限公司 | Negative Bias Temperature Instability appraisal procedure |
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