CN104851876A - Semiconductor device reliability testing structure protection circuit and protection method - Google Patents
Semiconductor device reliability testing structure protection circuit and protection method Download PDFInfo
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- CN104851876A CN104851876A CN201410053565.6A CN201410053565A CN104851876A CN 104851876 A CN104851876 A CN 104851876A CN 201410053565 A CN201410053565 A CN 201410053565A CN 104851876 A CN104851876 A CN 104851876A
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Abstract
The invention relates to a semiconductor device reliability testing structure protection circuit and a protection method; the circuit comprises the following elements: a to-be tested MOS device; a protection diode and a fuse structure connected in series. A cathode of the protection diode is connected with a grid electrode of the MOS device; an anode of the protection diode is connected with one end of the fuse structure, and the other end of the fuse structure is grounded. The protection circuit can remove influences of plasma damages generated in a production process, and can prevent the reliability test from being affected by the protection circuit in a following device test period. In the MOS device production process, the fuse structure equals to a fuse wire, so the protection diode can remove plasma damages in the process period; in the following MOS device testing period after production, pulse stress can be applied to break the fuse structure, so a reliability testing result cannot be affected.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of protective circuit and guard method of semiconductor device reliability test structure.
Background technology
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly realized with the speed improving it by the size constantly reducing integrated circuit (IC)-components.At present, in order to improve device density, high-performance and reduce costs, the size of semiconductor device constantly reduces, and brings very large challenge to all many-sides such as manufacture and design.
With very lagre scale integrated circuit (VLSIC) (Ultra Large Scale Integrated circuit, ULSI) constantly the reducing of size, gate dielectric size in semiconductor device CMOS also constantly reduces, to obtain higher performance, semiconductor device reliability test becomes the important indicator weighing yield of devices.
Wherein, when adding constant voltage on grid, device is made to be in accumulated state through after a period of time, gate dielectric will puncture, the time experienced during this is exactly the life-span under this condition, namely generally said with time correlation dielectric breakdown (time dependent dielectric breakdown, TDDB), described TDDB is one of key factor weighing described gate dielectric reliability, and device such as 28nm or 20nm little for size is even following particularly like this.
In device fabrication process, often comprise the processing step of plasma treatment, described processing step can cause bad charging damage to device.Protection diode (Protection diodes, PDs) is widely used as a kind of mode avoiding plasma to charge.
The set-up mode of described protection diode circuit as shown in Figure 1a; its domain structure as shown in Figure 2; described diode is parallel is connected to grid; provide another leakage approach of a kind of electric current of plasma-induced generation in described processing step, such protective circuit must ensure that described diode can not affect the normal function of device or circuit.
The reliability testing structure of semiconductor device often carries out at a higher temperature, such as 120-150 DEG C, the Leakage Current of described diode is far longer than the Leakage Current under room temperature at such a temperature, thus affects the accuracy of described reliability testing structure test TDDB performance.
Such as select in constant current TDDB method of testing, the grid of described MOS transistor applies a constant current bias stress (constant-current bias stress), under described MOS transistor is in inverted status, described transistor is biased in described reverse turn operation region equally, as shown in Figure 1 b, under normal circumstances, when room temperature, by the Leakage Current Ileak of described diode well below the electric current I g through described grid, because now described diode has very little reverse current, described diode at room temperature can not affect normal electrical testing.
But described TDDB test is often carried out at a higher temperature, even higher than 150 DEG C, at such a temperature, that is greater than the Leakage Current under room temperature far away for the Leakage Current Ileak of described diode, even similar with described grid current Ig, when the electric current that applying one on described grid is constant, part can through described diode leakage, and the life-span of the TDDB obtained greatly by described method of testing is inaccurate.
Therefore; in order to the electric current formed in described plasma process is discharged in prior art; need to add described protection diode; but described protection diode is owing to having height Leakage Current at relatively high temperatures; can impact reliability testing structure in reliability testing process; making test result not accurate enough, is the problem needing solution at present badly.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of protective circuit of reliability testing structure, comprising:
MOS device to be measured;
The protection diode be arranged in series and fuse-wires structure;
The negative pole of wherein said protection diode is connected with the grid of MOS device to be measured, and the positive pole of described protection diode is connected with one end of described fuse-wires structure, the other end ground connection of described fuse-wires structure.
As preferably, the source electrode of described MOS device to be measured and grounded drain.
As preferably, described protection diode is the PN junction that N-type doping and P trap are formed, or the PN junction of the doping of P type and the formation of N trap.
As preferably, described fuse-wires structure is polysilicon fuse or metal fuse.
As preferably, described MOS device to be measured is nmos pass transistor or PMOS transistor.
As preferably, in MOS device preparation process, described protection diode and described fuse-wires structure are in path;
In reliability testing process, described fuse-wires structure fusing, makes described protection diode and described fuse-wires structure be in open circuit.
Present invention also offers a kind of guard method of protective circuit, comprising:
In MOS device preparation process, control described protection diode and described fuse-wires structure is in path, for the charging current produced in described preparation process provides leakage path;
In reliability testing process, described fuse-wires structure is fused, make described protection diode and described fuse-wires structure be in open circuit, to avoid impacting reliability test result.
As preferably, between the described grid and tagma of described MOS device, apply pulse stress, to be disconnected by described fuse-wires structure.
As preferably, described reliability testing comprises the test with time correlation dielectric breakdown.
The present invention is in order to solve problems of the prior art; provide a kind of protective circuit of new reliability detection architecture; described protective circuit adds an electric fuse structure relative to prior art; described electric fuse structure is in series with protection diode; after series connection, one end is electrically connected the grid of described MOS device; one end ground connection, wherein said diode reverse biased is arranged.
Protective circuit of the present invention can eliminate the impact of the plasma damage produced in the manufacturing process stage, can ensure again to eliminate the impact of described protective circuit on reliability testing in the follow-up device detection stage.During the manufacturing process of MOS device; described fuse-wires structure is equivalent to a resistance wire; the grid of MOS device is directly connected on protection diode and on described fuse-wires structure, thus makes to protect diode to play the effect of the plasma damage eliminated during technique.When manufacture complete enter follow-up MOS device test phase time; by applying pulse stress, described fuse-wires structure is disconnected; thus make MOS device and protect the separated of diode; avoid the Leakage Current at high temperature due to described protection diode excessive, described reliability test result is impacted.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
The protective circuit schematic diagram that Fig. 1 a-1b is detection architecture described in prior art;
The domain structure schematic diagram that Fig. 2 is the protective circuit of detection architecture described in prior art;
The protective circuit schematic diagram that Fig. 3 is detection architecture described in the embodiment of the invention;
The domain structure schematic diagram that Fig. 4 a-4c is the protective circuit of detection architecture described in the embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, protective circuit of the present invention and described guard method to be described.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
The present invention is in order to solve problems of the prior art; provide a kind of protective circuit of new reliability detection architecture; described protective circuit adds an electric fuse structure relative to prior art; described electric fuse structure is in series with protection diode; after series connection, one end is electrically connected the grid of described MOS device; one end ground connection, wherein said diode reverse biased is arranged.
Protective circuit of the present invention can eliminate the impact of the plasma damage produced in the manufacturing process stage, can ensure again to eliminate the impact of described protective circuit on reliability testing in the follow-up device detection stage.During the manufacturing process of MOS device; described fuse-wires structure is equivalent to a resistance wire; the grid of MOS device is directly connected on protection diode and on described fuse-wires structure, thus makes to protect diode to play the effect of the plasma damage eliminated during technique.When manufacture complete enter follow-up MOS device test phase time; by applying pulse stress, described fuse-wires structure is disconnected; thus make MOS device and protect the separated of diode; avoid the Leakage Current at high temperature due to described protection diode excessive, described reliability test result is impacted.
Embodiment 1
Below in conjunction with accompanying drawing to of the present invention one particularly execution mode be described further.
Wherein, described Fig. 3 is the protective circuit schematic diagram according to improvement circuit of the present invention.As shown in the figure; MOS device described in this figure is nmos pass transistor; described nmos pass transistor comprises grid and is positioned at grid both sides source and drain; wherein said protective circuit comprises diode and the fuse-wires structure of series connection; the positive pole of wherein said protection diode is connected with described fuse-wires structure one end; the negative pole of described protection diode is connected with the grid of MOS device to be measured, the other end ground connection of described fuse-wires structure.
As preferably; described protection diode is PN junction; in described nmos pass transistor; described protection diode is the PN junction that N-type doping and P trap are formed; the wherein 4a-4c domain structure schematic diagram that is the protective circuit of detection architecture described in the embodiment of the invention; can find out in described domain structure, described protective circuit 10 comprises diode in circle and fuse-wires structure.
As preferably, the source electrode of described nmos pass transistor to be measured and grounded drain, described fuse-wires structure is polysilicon fuse or metal fuse.
In MOS device preparation process, described protection diode and described fuse-wires structure are in path; In reliability testing process, described fuse-wires structure fusing, makes described protection diode and described fuse-wires structure be in open circuit.
The operation principle of described protective circuit is: ground connection after the positive pole series connection fuse-wires structure of described protection diode, is connected between the negative pole (protection diode N+ end) of this protection diode and the grid of NMOS tube.When in the manufacture process in NMOS tube; described fuse-wires structure is in connected state; the grid of NMOS tube and the protection negative pole of diode, fuse-wires structure are linked together; like this when the gate oxide of NMOS tube assembles a large amount of electric charge owing to being subject to action of plasma; these electric charges just can be discharged into ground by protection diode and described fuse-wires structure; thus protection NMOS tube is not subject to plasma damage, ensures that device has higher yield.
After NMOS tube completes; by applying pulse stress, described fuse-wires structure is disconnected; namely the grid of NMOS tube and protection diode, connection between fuse-wires structure is disconnected; NMOS tube is worked alone; avoid the Leakage Current at high temperature due to described protection diode excessive, described reliability test result is impacted.
In described structure domain 4a-4c; comprise grid G, source region S, drain region D and tagma B; wherein said grid is connected with described protective circuit 10; described protective circuit comprises the PN junction that the N-type doping that is arranged in fuse-wires structure and described P trap and is positioned at P trap is formed; wherein said grid G, source region S, drain region D and tagma B are all formed with metal level; to form electrical connection, for stress application.Described grid G, source region S, drain region D and be electrically connected by metal throuth hole between tagma B and the metal level of top.
Described structure domain 4a-4c is all corresponding to the circuit diagram in described Fig. 3, and when in the manufacture process in NMOS tube, the fuse-wires structure in described protective circuit 10 is in connected state, is equivalent to resistance wire; In reliability testing process between described grid G and tagma B stress application, described fuse-wires structure is fused, formed open circuit.
Embodiment 2
Below to of the present invention one particularly execution mode be described further.
Wherein, described MOS device is PMOS transistor in this embodiment; described PMOS transistor comprises grid and is positioned at grid both sides source and drain; wherein said protective circuit comprises diode and the fuse-wires structure of series connection; the positive pole of wherein said protection diode is connected with described fuse-wires structure one end; the negative pole of described protection diode is connected with the grid of MOS device to be measured, the other end ground connection of described fuse-wires structure.
As preferably; described protection diode is PN junction; in described PMOS transistor, described protection diode is the PN junction of the doping of P type and the formation of N trap, and the domain structure schematic diagram of the protective circuit of the detection architecture shown in 4a-4c in its domain structure and embodiment 1 is similar.
As preferably, the source electrode of described PMOS transistor to be measured and grounded drain, described fuse-wires structure is polysilicon fuse or metal fuse.
In MOS device preparation process, described protection diode and described fuse-wires structure are in path; In reliability testing process, described fuse-wires structure fusing, makes described protection diode and described fuse-wires structure be in open circuit.
The operation principle of described protective circuit is: ground connection after the positive pole series connection fuse-wires structure of described protection diode, this protection diode P+ holds and is connected between the grid of PMOS transistor.When in the manufacture process in PMOS transistor; described fuse-wires structure is in connected state; the grid of PMOS transistor and the protection negative pole of diode, fuse-wires structure are linked together; like this when the gate oxide of PMOS transistor assembles a large amount of electric charge owing to being subject to action of plasma; these electric charges just can be discharged into ground by protection diode and described fuse-wires structure; thus protection PMOS transistor is not subject to plasma damage, ensures that device has higher yield.
After PMOS transistor completes; by applying pulse stress, described fuse-wires structure is disconnected; namely the grid of PMOS transistor and protection diode, connection between fuse-wires structure is disconnected; PMOS transistor is worked alone; avoid the Leakage Current at high temperature due to described protection diode excessive, described reliability test result is impacted.
Grid G, source region S, drain region D and tagma B is comprised at described structure domain; wherein said grid is connected with described protective circuit; described protective circuit comprises the PN junction that the N-type doping that is arranged in fuse-wires structure and described P trap and is positioned at P trap is formed; wherein said grid G, source region S, drain region D and tagma B are all formed with metal level; to form electrical connection, for stress application.Described grid G, source region S, drain region D and be electrically connected by metal throuth hole between tagma B and the metal level of top.
When in the manufacture process in PMOS transistor, the fuse-wires structure in described protective circuit is in connected state, is equivalent to resistance wire; In reliability testing process between described grid G and tagma B stress application, described fuse-wires structure is fused, formed open circuit, particularly, pulse stress can be applied between described grid G and tagma B.
Can be applicable in multiple integrated circuit (IC) according to the semiconductor device with protective circuit that embodiment as above manufactures.Such as memory circuitry according to IC of the present invention, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM), read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio frequency (RF) circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for such as consumer electronic products, as in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (9)
1. a protective circuit for reliability testing structure, comprising:
MOS device to be measured;
The protection diode be arranged in series and fuse-wires structure;
The negative pole of wherein said protection diode is connected with the grid of MOS device to be measured, and the positive pole of described protection diode is connected with one end of described fuse-wires structure, the other end ground connection of described fuse-wires structure.
2. protective circuit according to claim 1, is characterized in that, the source electrode of described MOS device to be measured and grounded drain.
3. protective circuit according to claim 1, is characterized in that, described protection diode is the PN junction that N-type doping and P trap are formed, or the PN junction of the doping of P type and the formation of N trap.
4. protective circuit according to claim 1, is characterized in that, described fuse-wires structure is polysilicon fuse or metal fuse.
5. protective circuit according to claim 1, is characterized in that, described MOS device to be measured is nmos pass transistor or PMOS transistor.
6. protective circuit according to claim 1, is characterized in that, in MOS device preparation process, described protection diode and described fuse-wires structure are in path;
In reliability testing process, described fuse-wires structure fusing, makes described protection diode and described fuse-wires structure be in open circuit.
7., based on a guard method for the described protective circuit of one of claim 1 to 6, comprising:
In MOS device preparation process, control described protection diode and described fuse-wires structure is in path, for the charging current produced in described preparation process provides leakage path;
In reliability testing process, described fuse-wires structure is fused, make described protection diode and described fuse-wires structure be in open circuit, to avoid impacting reliability test result.
8. method according to claim 7, is characterized in that, applies pulse stress, to be disconnected by described fuse-wires structure between the described grid and tagma of described MOS device.
9. method according to claim 7, is characterized in that, described reliability testing comprises the test with time correlation dielectric breakdown.
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| CN201410053565.6A CN104851876B (en) | 2014-02-17 | 2014-02-17 | A kind of protection circuit of semiconductor device reliability test structure and guard method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106782659A (en) * | 2016-12-05 | 2017-05-31 | 中国电子科技集团公司第四十七研究所 | A kind of utilization antifuse realizes the circuit of encipherment protection |
| CN107393908A (en) * | 2017-08-31 | 2017-11-24 | 长江存储科技有限责任公司 | Mos gate oxygen applied to chip device test cell protects system and method |
| CN110364511A (en) * | 2019-07-24 | 2019-10-22 | 德淮半导体有限公司 | Semiconductor device |
| CN111562476A (en) * | 2019-01-28 | 2020-08-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure and test method of semiconductor device |
| WO2023279530A1 (en) * | 2021-07-05 | 2023-01-12 | 长鑫存储技术有限公司 | Detection circuit and detection method |
| US11621261B2 (en) | 2021-07-05 | 2023-04-04 | Changxin Memory Technologies, Inc. | Detection circuit and detection method |
| CN119147932A (en) * | 2024-11-20 | 2024-12-17 | 成都电科星拓科技有限公司 | A structure and method for testing MOS field effect transistor GIDL |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06295948A (en) * | 1993-04-08 | 1994-10-21 | Seiko Epson Corp | Method and circuit for evaluating semiconductor characteristics |
| US6611040B2 (en) * | 2000-06-08 | 2003-08-26 | Tito Gelsomini | Anti-fuse structure of writing and reading in integrated circuits |
| CN101252119A (en) * | 2008-03-25 | 2008-08-27 | 上海宏力半导体制造有限公司 | Characteristic measuring structure of MOS device |
| CN101393913A (en) * | 2007-09-21 | 2009-03-25 | 松下电器产业株式会社 | Semiconductor device and method for manufacturing the same |
| CN102024807A (en) * | 2009-09-09 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Protection device and method for semiconductor apparatus |
-
2014
- 2014-02-17 CN CN201410053565.6A patent/CN104851876B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06295948A (en) * | 1993-04-08 | 1994-10-21 | Seiko Epson Corp | Method and circuit for evaluating semiconductor characteristics |
| US6611040B2 (en) * | 2000-06-08 | 2003-08-26 | Tito Gelsomini | Anti-fuse structure of writing and reading in integrated circuits |
| CN101393913A (en) * | 2007-09-21 | 2009-03-25 | 松下电器产业株式会社 | Semiconductor device and method for manufacturing the same |
| CN101252119A (en) * | 2008-03-25 | 2008-08-27 | 上海宏力半导体制造有限公司 | Characteristic measuring structure of MOS device |
| CN102024807A (en) * | 2009-09-09 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Protection device and method for semiconductor apparatus |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106782659A (en) * | 2016-12-05 | 2017-05-31 | 中国电子科技集团公司第四十七研究所 | A kind of utilization antifuse realizes the circuit of encipherment protection |
| CN107393908A (en) * | 2017-08-31 | 2017-11-24 | 长江存储科技有限责任公司 | Mos gate oxygen applied to chip device test cell protects system and method |
| CN111562476A (en) * | 2019-01-28 | 2020-08-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure and test method of semiconductor device |
| CN110364511A (en) * | 2019-07-24 | 2019-10-22 | 德淮半导体有限公司 | Semiconductor device |
| WO2023279530A1 (en) * | 2021-07-05 | 2023-01-12 | 长鑫存储技术有限公司 | Detection circuit and detection method |
| US11621261B2 (en) | 2021-07-05 | 2023-04-04 | Changxin Memory Technologies, Inc. | Detection circuit and detection method |
| CN119147932A (en) * | 2024-11-20 | 2024-12-17 | 成都电科星拓科技有限公司 | A structure and method for testing MOS field effect transistor GIDL |
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