CN102024807A - Protection device and method for semiconductor apparatus - Google Patents
Protection device and method for semiconductor apparatus Download PDFInfo
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- CN102024807A CN102024807A CN2009101954976A CN200910195497A CN102024807A CN 102024807 A CN102024807 A CN 102024807A CN 2009101954976 A CN2009101954976 A CN 2009101954976A CN 200910195497 A CN200910195497 A CN 200910195497A CN 102024807 A CN102024807 A CN 102024807A
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Abstract
The invention provides a protection device for a semiconductor apparatus, which comprises a transistor, a first pad connected to the grid of the transistor, and a switch element and a diode in turn connected between the ground and the join point of the first pad and the grid of the transistor. The protection device of the invention can be used for protecting the semiconductor apparatus, particularly for preventing MOS transistor from being damaged by plasma in the manufacturing process and for testing the MOS elements under reverse mode and accumulating mode.
Description
Technical field
The present invention relates to semiconductor device, relate in particular to the circuit protection device that a kind of protection semiconductor device prevents to be subjected to plasma damage (PID).
Background technology
Along with semiconductor fabrication process enters the deep-submicron stage, plasma process has become the technology of more and more widely using.Plasma process is mainly used in ultraviolet photolithographic field, plasma etching field and field ion implantation etc.Yet, owing to have the operation of plasma in the manufacture process of semiconductor device, thereby the plasma damage phenomenon inevitably appears.Plasma damage can damage semiconductor device, and particularly the gate oxide of MOS device and device property cause the performance of device to reduce.For example, cause the threshold voltage of MOS device to drift about, gate oxidation films punctures electric weight and puncture voltage changes, and causes minority carrier generation transition in the MOS device conducting channel, finally causes the MOS device creepage excessive.Particularly, in the MOS device fabrication, adopt reactive ion etching (RIE), plasma enhanced chemical vapor deposition (PECVD) and in plasma sputtering equipment the plasma of depositing metal mix or etching.In the process that produces plasma and etching MOS device, can cause the different nodes or the zone of MOS device to have different current potentials, cause that current discharge causes damage, cause device reliability to reduce, make the gate oxide leakage current obviously increase, promptly produce so-called plasma damage.
The mechanism of plasma damage mainly comprises: the cumulative effect of electric charge, the ionisation effect of UV ray and the antenna effect of design layout etc.Described charge accumulation effects mainly is that electric charge accumulates in silicon wafer surface and produces to back to a certain degree and wear electric current then in technical process, thereby forms the damage of dielectric layer electric stress.In antenna effect, a conductor that is isolated on the gate oxide and is not connected to silicon substrate is called antenna.Because the area of gate oxide is littler, and thinner, so gate oxide is easy to be subjected to the influence of plasma damage.Antenna area influences the variation of the amount of electromotive force and electric current.Antenna ratio is high more, and the electric charge that gate oxide region is collected is many more, and is just severe more to the plasma damage of device.Along with further dwindling of antenna live width, plasma damage can be more and more serious.Thereby avoid the inhomogeneous electromotive force of plasma damage or leakage current generating in test with when using the MOS device, and can measure the performance of MOS device accurately, change particularly important.
Eliminate the influence of plasma damage by in circuit, increasing the protection diode in the prior art to the MOS device.Fig. 1 a and 1b show and have the NMOS pipe of protecting diode and the schematic circuit diagram of PMOS pipe in the prior art.In order to protect the MOS device; the gate oxide of MOS device particularly; between input pad and MOS device, increase by a protection diode; discharge owing to the unnecessary electric charge of antenna effect, so that the damage that the MOS device avoids high voltage and current and electrostatic interaction to cause by the protection diode that increases in the gate oxide region accumulation.
Particularly; as shown in Figure 1a, the grid of NMOS pipe 101 is connected to pad (PAD) 103, and increase by has the diode 102 of protective effect between the junction of the grid of NMOS pipe 101 and pad 103 and ground; the plus earth of diode 102, negative pole are connected to the grid of NMOS pipe 101.Because the grid of NMOS pipe can be assembled a large amount of electric charges in plasma treatment procedure.These unnecessary electric charges can be discharged into ground by protection diode 102, thereby avoid producing plasma damage.The protection mechanism of PMOS pipe is similar to the NMOS pipe, shown in Fig. 1 b.
Yet the plasma damage that plasma process produced although above-mentioned protection diode can be eliminated can bring new problem simultaneously.When after the device manufacturing is finished, entering test phase, usually need at reverse mode and accumulation pattern the MOS device to be tested respectively, with the NMOS pipe is example, and reverse mode is meant that the grid with the NMOS pipe adds positive voltage, and accumulation pattern is meant that the grid with the NMOS pipe adds negative voltage.Because the existence of protection diode, when the grid of NMOS pipe added negative voltage (being accumulation pattern), the negative voltage that is applied can be discharged into ground by protection diode 102, therefore can't measure the NMOS pipe under the accumulation pattern.
Therefore, need improve, can eliminate the influence of the plasma damage that produces in the manufacturing process stage, can guarantee again to be implemented in reverse mode and accumulation pattern can be tested the MOS device at the subsequent device test phase to existing protected mode.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
For addressing the above problem, promptly, make semiconductor device, particularly MOS transistor can prevent to be subjected to plasma damage by the protection diode during fabrication, can under reverse mode and accumulation pattern, all can test again the MOS device, the invention provides a kind of protective device of semiconductor device, it is characterized in that, described protective device comprises: transistor; Be connected in first pad of described transistor gate; And, the switch element and the diode that between the tie point of described transistor gate and first pad and ground, are connected successively.
According to an aspect of the present invention, described transistor is nmos pass transistor or PMOS transistor.When described transistor is nmos pass transistor, the plus earth of described diode; When described transistor is the PMOS transistor, the minus earth of described diode.
According to another aspect of the present invention, described switch element is transistor, diode or the fuse with switching function.The blowout current density of wherein said fuse is 10MA/cm
2To 50MA/cm
2
The present invention also provides a kind of method that is used to protect semiconductor device, described protective device comprises transistor, be connected in first pad of described transistor gate, and the switch element and the diode that between the tie point of described transistor gate and first pad and ground, are connected successively, it is characterized in that method comprises the following steps: during the manufacturing of described semiconductor device to make described transistorized grid be connected with described diode described switch element closure; Test period at described semiconductor device disconnects described switch element, makes described transistorized grid disconnect with described diode and is connected.
The plasma damage that utilizes protective circuit of the present invention to eliminate to produce in the manufacturing process stage is to the influence of MOS device, can guarantee again to be implemented in reverse mode and accumulation pattern can be tested the MOS device at the subsequent device test phase.The switch element that is adopted is simple in structure, is convenient on the technology realize, can not increase extra processing step.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 a shows the existing nmos device circuit of protecting diode that has;
Fig. 1 b shows the existing PMOS device circuitry of protecting diode that has;
Fig. 2 a shows first embodiment according to improvement nmos device circuit of the present invention;
Fig. 2 b shows first embodiment according to improvement PMOS device circuitry of the present invention;
Fig. 3 a shows second embodiment according to improvement nmos device circuit of the present invention;
Fig. 3 b shows second embodiment according to improvement PMOS device circuitry of the present invention;
Fig. 4 shows the local domain according to the fuse-wires structure that uses in the second embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
Fig. 2 a and Fig. 2 b show the protective circuit according to improvement nmos device circuit of the present invention and PMOS device circuitry respectively.Can eliminate the influence of the plasma damage that produces in the manufacturing process stage according to protective circuit of the present invention, can guarantee again to be implemented in reverse mode and accumulation pattern can be tested the MOS device at the subsequent device test phase.As shown in the figure; the present invention connects a switch element between the grid of protection diode and MOS device; during the manufacturing process of MOS device; switch closure; the grid of MOS device is directly connected on the protection diode, thereby makes the protection diode play to eliminate the effect of the plasma damage during the technology.Enter follow-up MOS device detection during the stage when manufacturing finishes, this switch element is disconnected, disconnect thereby make between MOS device and the protection diode.At test phase,, therefore need not to connect again the protection diode owing to no longer have the influence of plasma damage.And disconnecting MOS device afterwards with the protection diode can work alone, and therefore can carry out the test of normal reverse mode and accumulation pattern.
Fig. 2 a is depicted as the protective circuit schematic diagram according to improvement nmos circuit of the present invention.As shown in the figure, the grid of NMOS pipe 201 is connected to first pad (PAD-1) 204, the plus earth of protection diode 202, and the negative pole of this protection diode 202 and NMOS manage between 201 the grid and are connected a switch element 205.When in the manufacture process of NMOS pipe 201; switch element 205 closures; with the negative pole short circuit of the grid of NMOS pipe 201 and protection diode 202 together; like this when the gate oxide of NMOS pipe 201 owing to being subjected to action of plasma and assembling a large amount of electric charge; these electric charges just can be discharged into ground by protection diode 202, thereby protection NMOS pipe 201 is not subjected to plasma damage.After the making of NMOS pipe is finished; cut-off switch element 205; being connected between the grid that has promptly disconnected NMOS pipe 201 and the protection diode 202 makes NMOS pipe 201 work alone, so just can realize the while under reverse mode and accumulation pattern to NMOS 201 the work of managing test.
Fig. 2 b is depicted as the protective circuit schematic diagram according to improved PMOS circuit of the present invention.PMOS pipe 201 ' is similar with the operation principle of NMOS pipe 201, and difference only is to protect the conducting direction of diode 202 ' opposite.Shown in Fig. 2 b, the minus earth of protection diode 202 ', and anodal and PMOS manage between 201 ' the grid and are connected a switch element 205 '.When making PMOS pipe 201 ', can accumulate a large amount of electric charges because of action of plasma on the gate oxide of PMOS pipe 201 ', these electric charges when switch element 205 ' is closed by protecting diode 202 ' to be discharged into ground.
The switch element here can realize with device or the element that has on-off action arbitrarily well known to those skilled in the art, for example transistor, diode or the like.Yet in practice, production process of semiconductor device is preceding, and test step after, and this process is that order is carried out and irreversible, therefore switch element does not need to carry out switch repeatedly in real work, and only needs closure during manufacture, disconnects at test period afterwards getting final product.Consider this fact, preferred only be to use can switch fuse element once as the switch element among the present invention.
Fig. 3 a and 3b show second embodiment according to nmos device 301 of the present invention and PMOS device 301 ' protective circuit.Wherein Fig. 3 a shows the circuit diagram according to nmos device 301 protective circuits of the present invention, and Fig. 3 b shows the circuit diagram according to PMOS device 301 ' protective circuit of the present invention.Shown in Fig. 3 a and 3b, the switch element has here adopted the form of fuse.One end of this fuse element 305 is connected in the grid of MOS device and the tie point of first pad 304, and the other end of fuse element 305 is connected in the tie point of the protection diode 302 and second pad 303.During the MOS device was made, fuse 305 kept connecting, thereby the grid of MOS device is shorted on the protection diode 302.Finish when entering test phase in manufacturing; by between first pad 304 and second pad 303, applying enough voltage; thereby make the fuse element 305 of the electric current of fuse element 305 fusing can being flowed through make fuse element 305 fuse; thereby the grid of MOS device is disconnected with protection diode 302; realize working alone of MOS device, so that under reverse mode and accumulation pattern, all can test to the MOS device.The size of blowout current can be selected arbitrarily according to actual needs, and under the 65nm process conditions, the blowout current density that is adopted here is 10MA/cm
2To 50MA/cm
2
Fuse element is more simpler than the structure of other switch elements (for example transistor, diode etc.), and polysilicon that is deposited in the time of can utilizing making MOS device gate electrode or metal level carry out photoetching to be realized.Fig. 4 shows the schematic domain of the fuse element of the embodiment shown in Fig. 3 a and the 3b.Represented in Fig. 4 is fuse-wires structure under the 65nm semiconductor technology.As shown in Figure 4, the shape of fuse element 401 can be dumbbell shape, first width D of fuse element 401
1For greater than 5um, second width D
2Minimum is 0.09um, and its length L is 10um.When applying current density is 10MA/cm
2To 50MA/cm
2Blowout current the time, be the part fusing of L with the length of fuse element 401.Be understandable that for those skilled in the art the 65nm process conditions here only are examples, the invention is not restricted to concrete process and fuse element structure, also be applicable to the semiconductor technology of other sizes according to protective circuit of the present invention.
The plasma damage that utilizes protective circuit of the present invention to eliminate to produce in the manufacturing process stage is to the influence of MOS device, can guarantee again to be implemented in reverse mode and accumulation pattern can be tested the MOS device at the subsequent device test phase.The switch element that is adopted is simple in structure, is convenient on the technology realize, can not increase extra processing step.
The semiconductor device with protective circuit according to aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM), read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio frequency (RF) circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (13)
1. the protective device of a semiconductor device is characterized in that, described protective device comprises:
Transistor;
Be connected in first pad of described transistor gate; And,
The switch element and the diode that between the tie point of described transistor gate and first pad and ground, are connected successively.
2. protective device as claimed in claim 1 is characterized in that, described transistor is nmos pass transistor or PMOS transistor.
3. protective device as claimed in claim 2 is characterized in that, when described transistor is nmos pass transistor, and the plus earth of described diode.
4. protective device as claimed in claim 2 is characterized in that, when described transistor is the PMOS transistor, and the minus earth of described diode.
5. protective device as claimed in claim 1 is characterized in that, described switch element is transistor, diode or the fuse with switching function.
6. protective device as claimed in claim 4 is characterized in that, the blowout current density of described fuse is 10MA/cm
2To 50MA/cm
2
7. protective device as claimed in claim 1; it is characterized in that; described switch element is closed during the manufacturing of described semiconductor device; make described transistorized grid be connected with described diode; and the test period at described semiconductor device disconnects, and makes described transistorized grid disconnect with described diode and is connected.
8. integrated circuit that comprises the protective device of semiconductor device as claimed in claim 1, described integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC) and buried type DRAM, radio-frequency devices.
9. electronic equipment that comprises the protective device of semiconductor device as claimed in claim 1, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
10. method that is used to protect semiconductor device; described protective device comprises transistor; be connected in first pad of described transistor gate; and the switch element and the diode that between the tie point of described transistor gate and first pad and ground, are connected successively, it is characterized in that method comprises the following steps:
During the manufacturing of described semiconductor device,, make described transistorized grid be connected with described diode with described switch element closure;
Test period at described semiconductor device disconnects described switch element, makes described transistorized grid disconnect with described diode and is connected.
11. the method for protection semiconductor device as claimed in claim 9 is characterized in that, described transistor is nmos pass transistor or PMOS transistor.
12. the method for protection semiconductor device as claimed in claim 9 is characterized in that, described switch element is transistor, diode or the fuse with switching function.
13. the method for protection semiconductor device as claimed in claim 11 is characterized in that, the blowout current density of described fuse is 10MA/cm
2To 50MA/cm
2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101954976A CN102024807A (en) | 2009-09-09 | 2009-09-09 | Protection device and method for semiconductor apparatus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101954976A CN102024807A (en) | 2009-09-09 | 2009-09-09 | Protection device and method for semiconductor apparatus |
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| CN102024807A true CN102024807A (en) | 2011-04-20 |
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| CN2009101954976A Pending CN102024807A (en) | 2009-09-09 | 2009-09-09 | Protection device and method for semiconductor apparatus |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165602A (en) * | 2011-12-12 | 2013-06-19 | 台湾积体电路制造股份有限公司 | Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits |
| CN103199093A (en) * | 2012-01-09 | 2013-07-10 | 三星电子株式会社 | Semiconductor device, semiconductor system and fabricating method of the semiconductor device |
| CN103378095A (en) * | 2012-04-18 | 2013-10-30 | 北大方正集团有限公司 | Metal oxide semiconductor electrical parameter testing device and method of manufacture |
| CN104282662A (en) * | 2013-07-08 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Plasma damage testing structure and plasma damage testing method |
| CN104851876A (en) * | 2014-02-17 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device reliability testing structure protection circuit and protection method |
| CN109860150A (en) * | 2019-02-28 | 2019-06-07 | 德淮半导体有限公司 | The test circuit and test method of semiconductor devices |
| CN111354723A (en) * | 2018-12-24 | 2020-06-30 | 爱思开海力士有限公司 | Semiconductor device with a plurality of transistors |
| CN112466772A (en) * | 2020-11-27 | 2021-03-09 | 长江存储科技有限责任公司 | Test assembly and test method |
| WO2024000626A1 (en) * | 2022-06-30 | 2024-01-04 | 长鑫存储技术有限公司 | Semiconductor test key and method for forming same |
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2009
- 2009-09-09 CN CN2009101954976A patent/CN102024807A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165602A (en) * | 2011-12-12 | 2013-06-19 | 台湾积体电路制造股份有限公司 | Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits |
| CN103165602B (en) * | 2011-12-12 | 2016-07-20 | 台湾积体电路制造股份有限公司 | Prevent the antenna cell design of the gate dielectric damage that semiconductor integrated circuit plasma causes |
| CN103199093A (en) * | 2012-01-09 | 2013-07-10 | 三星电子株式会社 | Semiconductor device, semiconductor system and fabricating method of the semiconductor device |
| CN103378095A (en) * | 2012-04-18 | 2013-10-30 | 北大方正集团有限公司 | Metal oxide semiconductor electrical parameter testing device and method of manufacture |
| CN103378095B (en) * | 2012-04-18 | 2015-12-16 | 北大方正集团有限公司 | A kind of metal-oxide semiconductor (MOS) electrical parameter test component and manufacture method |
| CN104282662A (en) * | 2013-07-08 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Plasma damage testing structure and plasma damage testing method |
| CN104851876A (en) * | 2014-02-17 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device reliability testing structure protection circuit and protection method |
| CN111354723A (en) * | 2018-12-24 | 2020-06-30 | 爱思开海力士有限公司 | Semiconductor device with a plurality of transistors |
| CN111354723B (en) * | 2018-12-24 | 2024-02-27 | 爱思开海力士有限公司 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
| CN109860150A (en) * | 2019-02-28 | 2019-06-07 | 德淮半导体有限公司 | The test circuit and test method of semiconductor devices |
| CN112466772A (en) * | 2020-11-27 | 2021-03-09 | 长江存储科技有限责任公司 | Test assembly and test method |
| WO2024000626A1 (en) * | 2022-06-30 | 2024-01-04 | 长鑫存储技术有限公司 | Semiconductor test key and method for forming same |
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Application publication date: 20110420 |