CN106782659A - A kind of utilization antifuse realizes the circuit of encipherment protection - Google Patents
A kind of utilization antifuse realizes the circuit of encipherment protection Download PDFInfo
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- CN106782659A CN106782659A CN201611101218.1A CN201611101218A CN106782659A CN 106782659 A CN106782659 A CN 106782659A CN 201611101218 A CN201611101218 A CN 201611101218A CN 106782659 A CN106782659 A CN 106782659A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The circuit of encipherment protection is realized the present invention relates to a kind of utilization antifuse, including antifuse, enable control circuit and the state machine input port logic circuit being linked in sequence；Enable control circuit：For after antifuse is programmed, changing the enable control signal state of a control machine input port logic circuit of output；State machine input port logic circuit, for according to the data inversion position of control signal output TMS test ports is enabled to state machine circuit, realizing encryption.The present invention can realize the test to internal state, and after circuit design sizing, function solidification, by burning, the antifuse programs point so that by state machine to the test failure of internal logic circuit.
Description
Technical field
The present invention relates to the encipherment protection circuit that a kind of utilization antifuse realizes circuit.In particular, it is that one kind is used
Antifuse programs the state of point control circuit internal state machine, realizes the circuit to the encipherment protection effect of internal circuit logic.
Background technology
The developing direction of present integrated circuit is less and less device feature size, integrated level more and more higher, circuit design
Difficulty is increasing, increases in circuit design from the aspect of measurability, may so reduce the ability of circuit autoprotection.Circuit
Need to leave sufficient means of testing in design process, in order to the fault location in design process, meanwhile, after design typification also
Need to take circuit the means of being effectively protected, this respect has become the problem that IC design must take into consideration.
At present, for some large scale integrated circuits, especially programmable gate array circuit, more using software platform and firmly
The method of operation of part chip cooperation, has certain circuit protection to act on, but operating cost is larger.Antifuse device due to it once
Property programming characteristic, be more and more applied to the encipherment protection of circuit design in.
The content of the invention
It is above-mentioned to overcome the invention provides the effect that a kind of utilization antifuse programming point realizes circuit design encipherment protection
Defect.
The technical scheme that is used to achieve the above object of the present invention is：A kind of utilization antifuse realizes the electricity of encipherment protection
Road, including antifuse, enable control circuit and the state machine input port logic circuit being linked in sequence；
Enable control circuit：Enable control signal state of a control machine input for after antifuse is programmed, changing output
Port logic circuit；
State machine input port logic circuit, for according to the data inversion for enabling control signal output TMS test ports
Encryption is realized to state machine circuit in position.
It is described enable control circuit include upper pull-up structure, PMOS P20, NMOS tube N11, phase inverter INV20, INV21,
INV22, INV23, INV24, INV25, INV27, INV28, NAND gate NAND10, nor gate NOR20 and reverse output latch
LAT；
The source electrode of N11 is used to be input into program voltage, is also grounded by antifuse, and is connected with pull-up structure, grid and power supply
Connection, drain electrode is connected with the drain electrode of P20, INV20 inputs；The source electrode of P20 is connected with power supply, and grid connects with INV20 output ends
Connect；The data input pin connection of INV21, INV22, INV23 and the LAT of INV20 output ends through being sequentially connected；
Two inputs of NAND10 are respectively used to be input into reset signal and state machine control signals, in output end and LAT
The PMOS gate control signals end CN connections of cmos transmission gate circuit, also through the NMOS grid-control of cmos transmission gate circuit in INV24 and LAT
Signal end C is connected；The output end of LAT is connected through INV25 with the first input end of NOR20, second input end grounding of NOR20,
Output end enables control signal to state machine input port logic circuit through INV27, INV28 output successively.
The upper pull-up structure includes PMOS P10 and NMOS tube N10；The grounded-grid of P10, source electrode is connected with power supply, leakage
Pole is connected with the drain electrode of N10；The grid of N10 is connected with power supply, and source electrode is connected with the source electrode of N11.
The state machine input port logic circuit includes voltage conversion circuit, PMOS P11, P12, P13, NMOS tube
N12, phase inverter INV29, INV31, INV32, INV33, INV34, transmission gate GATE1, GATE2；
The input of INV29 is used to be input into the enable control signal for enabling control circuit, output end and voltage conversion circuit
Input connection；The output end of voltage conversion circuit is connected with the grid of P13；
INV31 input end groundings, output end is connected with the grid of N12, the grid of P11；The source ground of N12, drain electrode with
The drain electrode of P11, the grid connection of P12；The source electrode of P11 is connected with power supply, and the drain electrode of substrate and P12, substrate are connected；The source of P12
Pole is connected with power supply, and drain electrode is connected with the source electrode of P13, substrate, and the drain electrode of P13 is connected by resistance with TMS test ports；
TMS test ports are connected by IOB input modules circuit with the input of INV32, the output end of INV32 with
The input connection of GATE1, the output end of GATE1 successively after INV33, INV34 output data antiphase to state machine circuit；
The input of GATE2 is connected with the input of INV32, and GATE2 output ends are connected with the output end of GATE1；
GATE1 and GATE2 are the cmos transmission gates being made up of PMOS and NMOS；The PMOS grid ends of GATE1 are with GATE2's
The input connection of NMOS grid ends, INV29, the NMOS grid ends of GATE1 connect with the PMOS grid ends of GATE2, the output end of INV29
Connect, an alternative circuit is made up of GATE1 and GATE2.
The IOB input modules circuit includes PMOS P16, P17, P18, P19, NMOS tube N15, N16；The grid of P17,
The grid of P19 and the grid of N16 are connected with TMS test ports；The drain electrode of P17 and the drain electrode of N15, the drain electrode of P19, N16
Drain electrode, the input connection of INV32；The source electrode of P17 is connected with the drain electrode of P16；The source electrode of P16 is connected with power supply, grounded-grid；
The grid of N15, source ground；The source electrode of P19 is connected with the drain electrode of P18, and the source electrode of P18 is connected with power supply, grounded-grid；N16
Source ground.
The invention has the advantages that and advantage：
1. the present invention can realize the test to internal state, and after circuit design sizing, function solidification, by burning, this is anti-
Fuse programming point so that by state machine to the test failure of internal logic circuit.
2. the structure can be with flexible Application, in the case of coming easily to IC design, calibration tape, to circuit itself
Protection play great role.
3. this circuit programs point using antifuse, is applied to reinforcing, the application of secure circuit.This circuit structure is equally fitted
For the encipherment protection of the device circuitries with switching characteristic such as fuse circuit, flash circuits.
Brief description of the drawings
Fig. 1 is the encipherment protection structured flowchart that the present invention realizes circuit using antifuse；
Fig. 2 is antifuse programming point and enables control circuit theory diagrams；
Fig. 3 is state machine input port logic circuit schematic diagram.
Specific embodiment
Below in conjunction with the accompanying drawings and embodiment the present invention is described in further detail.
As shown in figure 1, the present invention programs point, state machine input port circuit logic IOB_TMS and control by antifuse
The part of enable control logic three composition of IOB_TMS outputs.In the case of the antifuse programming non-burn through of point, control logic portion is enabled
Divide the signal of output, the signal for controlling state machine input port to provide directly is entered into inside circuit in the same direction by gate circuit,
Connection status machine logic.In the case of antifuse programming point burn through, the signal that state machine input port is provided then is redirected back into
Inside circuit, cause state machine to occur abnormal, test function of circuit is limited under the conditions of this, realize that the encryption of circuit design is protected
Shield.So, in IC design, test process, retain such antifuse programming point, it is possible to achieve to internal state
Test, after circuit design sizing, function solidification, by burning, the antifuse programs point so that by state machine to internal logic
The test failure of circuit.The structure can be with flexible Application, it is believed that in the case of coming easily to IC design, calibration tape,
Great role is played in protection to circuit itself.
A kind of encipherment protection electricity for programming point containing antifuse and enabling control circuit, state machine input port logic circuit
Road, comprising latch, resistance, PMOS, NMOS and basic gate circuit, such as phase inverter INV, two input nand gates.
Whether is the burning of antifuse programming point, controls to enable the state of control circuit output signal.
State machine input port logic circuit, the logic belongs to circuit interface module, comprising pull-up resistor and basic door electricity
Road, control port 110 is enabled with output, controls the state of the module output end, and the output signal is used as the defeated of state machine
Enter signal.
Output enables signal to be influenceed by antifuse programming dotted state, after antifuse programming point burning, the module output signal
Negate, influence state machine status so that circuit external exception occurs by the test function that state machine is realized, inside is patrolled
Collect and play a protective role.
Antifuse programming point and enable electric operation control circuit figure are shown in Fig. 2.Wherein ANTIFUSE be antifuse programming point, N10,
N11 is nmos device, and P10, P20 are PMOS devices, INV20, INV21, INV22, INV23, INV24, INV25, INV27,
INV28 is reverser, and NAND10 is two input nand gates, and NOR20 is two input nor gates, and LAT16 is reverse output latch.
100 is input signal, and 110 is the enable control signal of circuit output.
Specifically the annexation of device is：The grid connecting to neutral current potential of P10, source connects 1.8v power supplys, and drain terminal connects the leakage of N10
End, the grid of N10 connect 1.8v power supplys, weak pull-up structure are constituted by P10 and N10, and the source of N10 is connected to 100 input signal gauzes
On, the gauze connects the source of N11 simultaneously, and the grid connection 1.8v power supplys of N11, the drain terminal of N11 connects the drain terminal and INV20 of P20
Input, INV20 output signal connection P20 grid and INV21 input.The source of P20 connects 1.8v power supplys,
The input of the output connection INV22 of INV21, the input of the output connection INV23 of INV22, the output of INV23 is used as latch
The data input signal of LAT16, two input signals of NAND10 are CLR and A2, CLR are reset signal, and A2 is from shape
The signal of state machine control, the output signal of NAND10 is connected to the CN ports of LAT all the way, and another road connects INV24, INV24's
The output connection NOR20 of output the connection INV25, INV25 of output connection C, LAT16, two 1 input signal connecting to neutral of NOR20
Current potential, the input of the output connection INV27 of NOR20, the input of the output connection INV28 of INV27, the output connection of INV28
110。
A weak electricity high was provided on 100 lines as do not provided program voltage VPROG, P10 and N10 weak pull-up in circuit
It is flat, by after N11, P20 and INV20 causes that the output of INV20 is stably maintained at low level for keep circuits.CLR signal is in electricity
It is low level in the initialization procedure of road, the cmos transmission gate grid in LAT16 are opened, and input data are transferred in latch ring, electricity
Under the stable state of road, CLR signal is 1.8v high level, and A2 signals are controlled by circuit internal state machine, when its value is low level,
The input signal of LAT16 can reach output end by cmos transmission gate, if A2 high level, then the state that combine CLR is come
Determine the output signal of LAT16 from input or internal latch ring.Summarize, be high level, 110 on 100 lines
It is the low level of zero potential.Conversely, as once provided program voltage VPROG in circuit, then 100 current potentials are maintained at ground potential, 110
It is output as 1.8v high level.
State machine input port logic circuit is illustrated in Fig. 3.Wherein P11, P12, P13, P14, P15, P16, P17, P18,
P19 is PMOS device, and N12, N13, N14, N15, N16 are nmos devices, INV29, INV30, INV31, INV32, INV33,
INV34 is reverser, and R1 is resistance, and GATE1, GATE2 are PMOS and NMOS source and drain cmos transmission gates in parallel.200 is data
Input signal, from chip package external port, 210 is output signal, logic state machine is may be connected to, as the defeated of state machine
Enter signal.And then realize control of the chip external port to state machine.
110 signals connect the input of INV29, the input of the output connection INV30 of INV29, while connecting the grid letter of N13
Number, the gate signal of the output connection N14 of INV30, the source of N13, N14 connects low level zero potential, and the drain terminal of N13 connects the leakage of P14
The grid end of end, P15 grid ends and P13, the source connection 3.3v high potentials of P14, the source connection 3.3v high potentials of P15, the leakage of P15
The drain terminal of end connection N14.
The input connection low level zero potential of INV31, the grid end of output connection P11 and N12, the source and substrate of P11 connect
3.3v high potentials are connect, the drain terminal of P11 connects the drain terminal of N12, while the grid end of P12 is connected, the source connection 3.3v electricity high of P12
Position, drain terminal and substrate and P11, P13 source and substrate of P12 link together, and the drain terminal of P13 connects a 10K Ohmic resistance,
The resistance other end connects 200 holding wires, is TMS (Test Mode Select) port.
200 holding wires connect the grid end of P17, P19 and N16 simultaneously, and the grid end of P16 connects low level zero potential, the source of P16
Connect 3.3v high potentials, the drain terminal of P16 connects the source of P17, and the drain terminal of P17 connects the drain terminal of N15, at the same connect P19 drain terminal and
The drain terminal of N16, source and grid end the connection low level zero potential of N15, the source connection low level zero potential of N16, the source of P18
Connection 3.3v high potentials, the grid end connection low level zero potential of P18, the drain terminal of P18 connects the source of P19, N15, N16, P17
Connect the input of INV32 jointly with the drain terminal of P19, and GATE2 input, the output connection GATE1's of INV32 is defeated
Enter, the output of GATE1 and GATE2 connects together, the two cmos transmission gates realize the forward and reverse output control of input signal, and its is defeated
Go out input signal of the signal as INV33, the output signal of INV33 connects the input of INV34, and the output signal of INV34 connects
210 holding wires are connect, as an input signal of circuit state machine.
When 110 is zero potential low level, the data of TMS test ports can with the TMS_IN that enters into of same-phase, and then
Enter into state machine circuit, the jtag test of circuit can be carried out correctly, when 110 is 1.8v high level, TMS test ports
Data inversion position enter into TMS_IN, and then enter into state machine circuit, cause state machine function disorderly, for circuit
For the user of chip, then can not enter the jtag test of walking along the street, circuit internal state can not be surveyed, circuit function is entered so as to reach
The purpose of row protection treatment.This circuit depends on antifuse to program the presence of point, similar structure using such protection structure
Fuse-wire device etc. is can be also used for, such device has the common feature to be exactly, once using, circuit characteristic where it just really
It is fixed, it is impossible to change.
Reverser INV, two input nand gate NAND2, the power supply of two input nor gate NOR2 are all 1.8v, low electricity in circuit
It is zero potential to put down.
Claims (5)
1. a kind of utilization antifuse realizes the circuit of encipherment protection, it is characterised in that including the antifuse, the enable control that are linked in sequence
Circuit processed and state machine input port logic circuit；
Enable control circuit：For after antifuse is programmed, changing the enable control signal state of a control machine input port of output
Logic circuit；
State machine input port logic circuit, for according to enable control signal output TMS test ports data inversion position extremely
State machine circuit, realizes encryption.
2. a kind of utilization antifuse according to claim 1 realizes the circuit of encipherment protection, it is characterised in that the enable
Control circuit include upper pull-up structure, PMOS P20, NMOS tube N11, phase inverter INV20, INV21, INV22, INV23, INV24,
INV25, INV27, INV28, NAND gate NAND10, nor gate NOR20 and reverse output latch LAT；
The source electrode of N11 is used to be input into program voltage, is also grounded by antifuse, and is connected with pull-up structure, and grid is connected with power supply,
Drain and be connected with the drain electrode of P20, INV20 inputs；The source electrode of P20 is connected with power supply, and grid is connected with INV20 output ends；
The data input pin connection of INV21, INV22, INV23 and the LAT of INV20 output ends through being sequentially connected；
Two inputs of NAND10 are respectively used to be input into reset signal and state machine control signals, output end and CMOS in LAT
The PMOS gate control signals end CN connections of transmission gate circuit, also through the NMOS gate control signals of cmos transmission gate circuit in INV24 and LAT
End C connections；The output end of LAT is connected through INV25 with the first input end of NOR20, second input end grounding of NOR20, output
End enables control signal to state machine input port logic circuit through INV27, INV28 output successively.
3. a kind of utilization antifuse according to claim 1 realizes the circuit of encipherment protection, it is characterised in that the pull-up
Structure includes PMOS P10 and NMOS tube N10；The grounded-grid of P10, source electrode is connected with power supply, and drain electrode connects with the drain electrode of N10
Connect；The grid of N10 is connected with power supply, and source electrode is connected with the source electrode of N11.
4. a kind of utilization antifuse according to claim 1 realizes the circuit of encipherment protection, it is characterised in that the state
Machine input port logic circuit include voltage conversion circuit, PMOS P11, P12, P13, NMOS tube N12, phase inverter INV29,
INV31, INV32, INV33, INV34, transmission gate GATE1, GATE2；
The input of INV29 is used to be input into the enable control signal for enabling control circuit, and output end is defeated with voltage conversion circuit
Enter end connection；The output end of voltage conversion circuit is connected with the grid of P13；
INV31 input end groundings, output end is connected with the grid of N12, the grid of P11；The source ground of N12, drain electrode is with P11's
Drain electrode, the grid connection of P12；The source electrode of P11 is connected with power supply, and the drain electrode of substrate and P12, substrate are connected；The source electrode of P12 and electricity
Source is connected, and drain electrode is connected with the source electrode of P13, substrate, and the drain electrode of P13 is connected by resistance with TMS test ports；
TMS test ports are connected by IOB input modules circuit with the input of INV32, and the output end of INV32 is with GATE1's
Input is connected, the output end of GATE1 successively after INV33, INV34 output data antiphase to state machine circuit；GATE2's
Input is connected with the input of INV32, and GATE2 output ends are connected with the output end of GATE1；
GATE1 and GATE2 are the cmos transmission gates being made up of PMOS and NMOS；The PMOS grid ends of GATE1 and the NMOS of GATE2
The input connection of grid end, INV29, the NMOS grid ends of GATE1 are connected with the PMOS grid ends of GATE2, the output end of INV29, by
GATE1 and GATE2 constitutes an alternative circuit.
5. a kind of utilization antifuse according to claim 4 realizes the circuit of encipherment protection, it is characterised in that the IOB is defeated
Entering modular circuit includes PMOS P16, P17, P18, P19, NMOS tube N15, N16；
The grid of the grid of P17, the grid of P19 and N16 is connected with TMS test ports；The drain electrode of P17 and the drain electrode of N15,
The drain electrode of P19, the drain electrode of N16, the input connection of INV32；The source electrode of P17 is connected with the drain electrode of P16；The source electrode of P16 and electricity
Source connects, grounded-grid；The grid of N15, source ground；The source electrode of P19 is connected with the drain electrode of P18, and source electrode and the power supply of P18 connect
Connect, grounded-grid；The source ground of N16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611101218.1A CN106782659A (en) | 2016-12-05 | 2016-12-05 | A kind of utilization antifuse realizes the circuit of encipherment protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611101218.1A CN106782659A (en) | 2016-12-05 | 2016-12-05 | A kind of utilization antifuse realizes the circuit of encipherment protection |
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| CN106782659A true CN106782659A (en) | 2017-05-31 |
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| CN201611101218.1A Pending CN106782659A (en) | 2016-12-05 | 2016-12-05 | A kind of utilization antifuse realizes the circuit of encipherment protection |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108932408A (en) * | 2018-08-03 | 2018-12-04 | 广东工业大学 | A kind of enable signal control circuit and a kind of chip |
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| US8026746B1 (en) * | 2008-11-11 | 2011-09-27 | Altera Corporation | Power on reset circuitry for manufacturability and security using a fuse |
| CN104851876A (en) * | 2014-02-17 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device reliability testing structure protection circuit and protection method |
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|---|---|---|---|---|
| CN1979686A (en) * | 2005-12-06 | 2007-06-13 | 上海华虹Nec电子有限公司 | Safety detecting method for system integrated chip with built-in non-volatile memory |
| US8026746B1 (en) * | 2008-11-11 | 2011-09-27 | Altera Corporation | Power on reset circuitry for manufacturability and security using a fuse |
| CN104851876A (en) * | 2014-02-17 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device reliability testing structure protection circuit and protection method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108932408A (en) * | 2018-08-03 | 2018-12-04 | 广东工业大学 | A kind of enable signal control circuit and a kind of chip |
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