CN1979686A

CN1979686A - Safety detecting method for system integrated chip with built-in non-volatile memory

Info

Publication number: CN1979686A
Application number: CN 200510111178
Authority: CN
Inventors: 曾志敏
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2005-12-06
Filing date: 2005-12-06
Publication date: 2007-06-13

Abstract

The invention discloses a safe test method for an SOC (system on chip) embedded with nonvolatile memory (NVM), detecting data at embedded NVM specific addresses by a test mode detecting logic so as to implement test mode switching, where the embedded NVM specific addresses can not be accessed in user mode, and when the test is finished, it writes the appointed mode setting data at the embedded NVM specific addresses, and after detecting the data, a test mode logic circuit of the SOC intermediately switches the chip to the user mode to cut off test circuits of internal modules so as to make the chip enter into common user mode, thus implementing access inhibition to the internal modules. For reentering into the chip test mode, the invention also erases the mode setting data in the NVM by a special microprocessing instruction and simultaneously erases all data in the NVM so as to protect data.

Description

The safety detecting method of the system integrated chip of built-in non-volatile memory

Technical field

The present invention relates to a kind of integrated circuit (IC) testing method, particularly a kind of safety detecting method of system integrated chip.

Background technology

Wafer (Wafer) the level test of system integrated chip (SOC) product often relates to the test of internal logic functional module, Simulation with I P module and storer; consideration based on circuit design protection of Intellectual Property Rights and data security; after finishing, test needs test access is cut off; thereby make domestic consumer can only use the function under the user model; and can not directly visit the circuit module of SOC inside and the data message of specific memory section, such test is called safety test.

Realize that by changing physical connection the chip safety test is current designing technique relatively more commonly used, mainly contain two kinds of methods, a kind of is fuse cut, and another kind is that scribe line is cut off.

The fuse cut technology is to realize the switching of test pattern and user model in chip by the break-make of resistance fuse, after chip manufacturing is finished, the connected state of fuse resistor makes circuit enter test pattern, and this state can be realized the test of chip internal module down.After test is finished, make fuse failure by making alive, chip enters user model, and this state can only use the general function of chip down, can not some functions under the test pattern be operated, thus the safety test and the application of realization chip.

Scribe line cut-out technology is to utilize the space of scribe line to place the pad (Pad) that determines test pattern/user model.In the Wafer test, can control signal be added on this Pad by probe, thereby control chip enters the test that test pattern carries out internal module, after test is finished, Wafer is cut when encapsulating, Pad on the scribe line is destroyed, draw on the chip internal/pull down resistor is clamping, makes chip enter user model, forbids test access.

Above-mentionedly realize that by changing physical connection there is following problem in chip safety test scheme: the method that physics changes is a disruptive method, just can't reenter test pattern after changing, and uses dumb; The user may realize entering again of test pattern by the method for physics reparation, and the acquisition cuicuit data message, and security is not high.

Summary of the invention

The technical problem to be solved in the present invention provide a kind of based on electrical method, can guarantee data security and can reenter the safety detecting method of system integrated chip of the built-in non-volatile memory of test pattern.

For solving the problems of the technologies described above, the safety detecting method of the system integrated chip of built-in non-volatile memory of the present invention has utilized a test pattern to detect logic, this logic realizes the switching of test pattern based on the judgement of the data of embedded NVM particular address, and this address is inaccessible under user model.When test is finished, embedded NVM particular address is write data designated information, after the test pattern logical circuit of chip detects these data, then immediately chip is switched under the user model, cut off the test access of internal module, make chip enter user EXEC, thereby the visit that realizes the internal circuit module is forbidden.For realizing reentering of chip testing pattern, the present invention also is provided with data erase by a special-purpose MCU instruction with the pattern in the NVM, wipes the total data of NVM simultaneously, with protected data safety.

The present invention can realize the visit test of chip internal module under test pattern, and under user EXEC, can only use the external function of chip, internal module directly visit is under an embargo, switching between test pattern and the user model has obtained safe and reliable control, can realize the safety test of SOC chip; Realize safety test control by electrical method simultaneously, higher than the physics mode security; Can under test pattern and user model, switch repeatedly neatly safely, and when switching, destroy the sensitive data that chip is preserved, guarantee data security.

Description of drawings

Accompanying drawing is control principle figure of the present invention.

Embodiment

The present invention is further detailed explanation below in conjunction with accompanying drawing.

The NVM that embeds in the SOC chip, as flash memory (Flash), EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) etc., its data have the characteristic that following electricity keeps, and the present invention utilizes this characteristic to carry out switching between test pattern and the user model.

Referring to accompanying drawing, the present invention is provided with test pattern and detects steering logic, and this logic realizes the switching of test pattern based on the judgement of the data of embedded NVM particular address, and this address is inaccessible under user model.Under the initial state that chip manufacturing is finished, because the data of NVM particular address are non-data designated, chip is in the test pattern attitude, can directly realize the test of internal module by chip pin.When test is finished, the NVM specific storage address is write mode designated data message is set, after the test pattern detection steering logic of chip detects these data, immediately chip is switched under the user model, cut off the test access of internal module, make chip enter user EXEC, thereby the visit that realizes the internal circuit module is forbidden.

The present invention also is provided with pattern and enters steering logic again, and this logical circuit can be provided with data erase with the pattern in the NVM by a special-purpose microcontroller (MCU) instruction, at this moment can reenter the chip testing pattern.The MCU instruction can be wiped the total data of NVM in mode switch, the sensitive information that is about to preserve in the SOC is destroyed with protected data safety.

Method provided by the invention has been utilized the nonvolatile characteristics of NVM data, has realized embedded The safety test of the SOC of NVM, the method is simple, and is reliable, uses flexibly.

Claims

1, a kind of safety detecting method of system integrated chip of built-in non-volatile memory, between test pattern and user model, switch, it is characterized in that, adopt test pattern to detect steering logic, carry out switching between described test pattern and the described user model by the judgement of data that built-in non-volatile memory particular address that can not be accessed under user model is preserved.

2, the safety detecting method of the system integrated chip of built-in non-volatile memory according to claim 1 is characterized in that, when test is finished, described built-in non-volatile memory particular address is write specific data information.

3, the safety detecting method of the system integrated chip of built-in non-volatile memory according to claim 2, it is characterized in that, described test pattern detect steering logic described built-in non-volatile memory particular address as detect less than as described in specific data information, then chip is switched to described test pattern; Described test pattern detect steering logic in described built-in non-volatile memory particular address as specific data information as described in detecting, then immediately chip is switched to user model, cut off the test access of internal module.

4, the safety detecting method of the system integrated chip of built-in non-volatile memory according to claim 1 is characterized in that, adopts a pattern to enter steering logic again, sends a little processing instruction and wipes data in the built-in non-volatile memory.