CN110532222A - A kind of FPGA switch unit based on STT-MRAM - Google Patents
A kind of FPGA switch unit based on STT-MRAM Download PDFInfo
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- CN110532222A CN110532222A CN201910815607.8A CN201910815607A CN110532222A CN 110532222 A CN110532222 A CN 110532222A CN 201910815607 A CN201910815607 A CN 201910815607A CN 110532222 A CN110532222 A CN 110532222A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention discloses a kind of FPGA switch unit based on STT-MRAM, belongs to technical field of integrated circuits.The FPGA switch unit based on STT-MRAM includes STT-MRAM element group, control unit, phase inverter and switch unit；Wherein, STT-MRAM element group generates current potential to phase inverter, and the phase inverter will feed back to control unit after the current potential reverse phase, and the current potential that described control unit controls STT-MRAM element group under the action of the phase inverter latches；Switch unit is connected with the inverter output.Data of the configuration in STT-MRAM element group will not lose after the FPGA switch unit can realize FPGA power down.Start fast speed without reading data run from external independent memory when powering on compared to more traditional SRAM type FPGA.Low in energy consumption since the read or write speed of STT-MRAM element group is fast, FPGA switch unit of the invention has higher read-write frequency, higher erasable number with respect to the FPGA of FLASH type, and cost is lower.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of FPGA switch unit based on STT-MRAM.
Background technique
FPGA (Field-Programmable Gate Array) is a kind of field programmable gate battle array of semi-custom
Column, due to the features such as its development cycle is short, cost performance is high, flexibility is good, are widely used in communication, aerospace, automobile, doctor
The fields such as treatment, technology controlling and process.
FPGA technology mainly has three categories at present: SRAM configuration FPGA technology, antifuse configuration FPGA technology and
The FPGA technology of Flash configuration.Wherein the FPGA of SRAM type configuration is fast with speed, programming number is unrestricted, processing compatibility
The advantages that strong is the FPGA configuration technology of current mainstream；The FPGA of antifuse configuration has non-easy with respect to the FPGA that SRAM is configured
The characteristics of property lost, can solve the problems, such as loss of data after the FPGA power down of SRAM configuration, and disadvantage can only exactly program once, limit to
Property is larger；The FPGA of Flash configuration has merged the advantage of both SRAM and antifuse, has non-volatile, repeatable programming etc.
Feature, but complex process, the cost is relatively high.
Summary of the invention
The purpose of the present invention is to provide a kind of FPGA switch unit based on STT-MRAM, to solve traditional SRAM type
FPGA poor reliability, the problem that power failure data is lost and FLASH type FPGA is at high cost, working frequency is low.
In order to solve the above technical problems, the present invention provides a kind of FPGA switch unit based on STT-MRAM, comprising:
STT-MRAM element group, control unit, phase inverter and switch unit；Wherein,
The STT-MRAM element group generates current potential to the phase inverter, and the phase inverter will feed back to described after the current potential reverse phase
Control unit, the current potential that described control unit controls the STT-MRAM element group under the action of phase inverter latch；
The switch unit is connected with the inverter output.
Optionally, described control unit includes NMOS tube T1, T3, T4 and PMOS tube T2；Wherein,
NMOS tube T1 grid meets control signal EN, and drain electrode meets power vd D, and source electrode connects PMOS tube T2 drain electrode；The PMOS tube T2 grid
Pole connects the inverter output, and source electrode meets power vd D, and drain electrode connects the STT-MRAM element group；
NMOS tube T3 grid meets the control signal EN, and source electrode is grounded GND, and drain electrode connects NMOS tube T4 drain electrode；The NMOS tube T4
Grid connects the inverter output, and source electrode is grounded GND, and drain electrode connects the STT-MRAM element group.
Optionally, described control unit includes PMOS tube T1, T2, T3 and NMOS tube T4；Wherein,
PMOS tube T1 grid meets control signal EN, and source electrode meets power vd D, and drain electrode connects PMOS tube T2 drain electrode；The PMOS tube T2 grid
Pole connects the inverter output, and source electrode meets power vd D, and drain electrode connects the STT-MRAM element group；
PMOS tube T3 grid meets the control signal EN, grounded drain GND, and source electrode connects NMOS tube T4 drain electrode；The NMOS tube T4
Grid connects the inverter output, and source electrode is grounded GND, and drain electrode connects the STT-MRAM element group.
Optionally, the phase inverter is CMOS inverter, including metal-oxide-semiconductor T5 and T6, PMOS tube T5 source electrode meet power vd D,
NMOS tube T6 source electrode is grounded GND, PMOS tube T5 drain electrode and the NMOS tube T6 drain interconnection, the PMOS tube T5 grid with
The NMOS tube T6 gate interconnection, and it is connected to the STT-MRAM element group.
Optionally, the STT-MRAM element group includes the STT-MRAM element of several series aiding connections connection.
Optionally, the quantity of the STT-MRAM element is 2.
Optionally, the switch unit is PMOS tube or NMOS tube；Wherein,
When the switch unit is PMOS tube, grid connects the inverter output, and source electrode is as signal input port, drain electrode
As signal output port；
When the switch unit is NMOS tube, grid connects the inverter output, and source electrode is as signal output port, drain electrode
As signal input port.
Optionally, the FPGA switch unit based on STT-MRAM further includes the end CON1 and the end CON2, is connect respectively in institute
State STT-MRAM element group both ends.
A kind of FPGA switch unit based on STT-MRAM, including STT-MRAM element group, control are provided in the present invention
Unit, phase inverter and switch unit processed；Wherein, the STT-MRAM element group generates current potential to the phase inverter, the reverse phase
Device will feed back to described control unit after the current potential reverse phase, described in described control unit controls under the action of the phase inverter
The current potential of STT-MRAM element group latches；The switch unit is connected with the inverter output.
The present invention is using STT-MRAM element group as programming point, it can be achieved that configuration is in STT-MRAM element after FPGA power down
Data in group will not lose.Compared to more traditional SRAM type FPGA, without being read from external independent memory when powering on
Data run is taken, fast speed is started；Since the read or write speed of STT-MRAM element group is fast, low in energy consumption therefore of the invention
FPGA switch unit has higher read-write frequency, higher erasable number with respect to the FPGA of FLASH type, and cost is lower.
Detailed description of the invention
Fig. 1 is the structural schematic diagram for the FPGA switch unit based on STT-MRAM that the embodiment of the present invention one provides；
Fig. 2 is that STT-MRAM element programs principal diagram is intended to；
Fig. 3 is the mode of operation schematic diagram of the FPGA switch unit based on STT-MRAM；
Fig. 4 is the structural schematic diagram of the FPGA switch unit provided by Embodiment 2 of the present invention based on STT-MRAM.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to a kind of FPGA switch unit based on STT-MRAM proposed by the present invention
It is described in further detail.According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted
It is that attached drawing is all made of very simplified form and using non-accurate ratio, only to facilitate, lucidly aid in illustrating this hair
The purpose of bright embodiment.
Embodiment one
The present invention provides a kind of FPGA switch unit based on STT-MRAM, including it is STT-MRAM element group, control unit, anti-
Phase device and switch unit；Wherein, the STT-MRAM element group generates current potential to the phase inverter, and the phase inverter is by the current potential
Described control unit is fed back to after reverse phase, described control unit controls the STT-MRAM element under the action of phase inverter
The current potential of group latches；The switch unit is connected with the inverter output.By the feedback effect of the phase inverter, make
In the operational mode, STT-MRAM element group both ends are in equipotential state to FPGA switch unit always, reduce to STT-
The electrical stress effect of STT-MRAM element in MRAM element group, improves the reliability of device.
Specifically, a kind of implementation structure of the FPGA switch unit based on STT-MRAM is as shown in Figure 1.The STT-
MRAM element group includes the STT-MRAM element of several series aiding connections connection, STT-MRAM element described in the present embodiment one
Quantity is 2.The principle of the STT-MRAM element programs is as shown in Fig. 2, it will be appreciated by those skilled in the art that STT-MRAM
Element is a kind of magnetic memory based on electron spin transfer square, by the direction for changing write current, thus it is possible to vary MTJ
The resistive state of (Magnetic Tunneling Junction, magnetic tunnel-junction) is at "high" or " low " of resistance value.When
Current direction can change the magnetic direction of free layer from fixing layer after separation layer, since the magnetic direction of fixing layer is fixed
Constant, when the direction of magnetization of free layer and fixing layer in the same direction, " low " resistance state is externally presented in MTJ, changes current direction, free layer
The direction of magnetization and fixing layer on the contrary, "high" resistance state is externally presented in MTJ.
It is that two STT-MRAM elements (STT-MRAM element M1 and STT-MRAM element M2) are gone here and there in the same direction in this implementation one
Connection connection, i.e., the fixing layer of STT-MRAM element M1 is connected with the free layer of STT-MRAM element M2, and is connected to programming end PW；
The end CON1 and the end CON2 are connect respectively in STT-MRAM element group both ends, i.e., Jie STT-MRAM member in the end CON1 as shown in Figure 2
The free layer of part M1, the fixing layer of the end CON2 Jie STT-MRAM element M2.
Please continue to refer to Fig. 1, described control unit includes NMOS tube T1, T3, T4 and PMOS tube T2；Wherein, NMOS tube T1
Grid meets control signal EN, and drain electrode meets power vd D, and source electrode connects PMOS tube T2 drain electrode；The PMOS tube T2 grid connects the reverse phase
Device output end, source electrode meet power vd D, and drain electrode connects the STT-MRAM element group, that is, connects the freedom of the STT-MRAM element M1
Layer；NMOS tube T3 grid meets the control signal EN, and source electrode is grounded GND, and drain electrode connects NMOS tube T4 drain electrode；The NMOS tube T4 grid
Pole connects the inverter output, and source electrode is grounded GND, and drain electrode connects the STT-MRAM element group, that is, meets STT-MRAM element M2
Fixing layer.
The phase inverter is CMOS inverter, including metal-oxide-semiconductor T5 and T6, PMOS tube T5 source electrode meet power vd D, NMOS tube T6
Source electrode is grounded GND, the PMOS tube T5 drain electrode and the NMOS tube T6 drain interconnection, and the output end as the phase inverter；
The PMOS tube T5 grid and the NMOS tube T6 gate interconnection, and be connected to the STT-MRAM element group, that is, it connects described
Between STT-MRAM element M1 and the STT-MRAM element M2.
The switch unit T7 is PMOS tube or NMOS tube, and when the switch unit T7 is PMOS tube, grid is connect
The inverter output, source electrode are used as signal output port as signal input port, drain electrode；When the switch unit T7 is
When NMOS tube, grid connects the inverter output, and source electrode is used as signal input port as signal output port, drain electrode.
When controlling signal EN=" 1 ", the FPGA switch unit provided by the invention based on STT-MRAM is in programmable shape
State, it is when EN=" 0 ", then in running order.When programming end PW is passed through program current, A is directed toward by PW in direction, this electric current should be big
In the threshold current of STT-MRAM element, two STT-MRAM element M1 and M2 are flowed through in the opposite direction in A point, respectively from CON1
It is flowed out with CON2 two-port.The resistance of two STT-MRAM elements can change, and the STT-MRAM element M1 is low resistance state,
The STT-MRAM element M2 is high-impedance state；Change program current direction, two STT-MRAM element generating states change, described
STT-MRAM element M1 is high-impedance state, and the STT-MRAM element M2 is low resistance state, to realize two STT-MRAM element resistances
It is worth "high" and " low " conversion.
When the STT-MRAM element M1 resistance value is "high", the STT-MRAM element M2 resistance value must be " low ", at this time A
Point current potential is low level " 0 ", is high level " 1 " after the inverted device reverse phase of B point current potential, and switch unit T7 is in "Off" state at this time,
" 1 " current potential of B point can feed back the grid end of PMOS tube T2, NMOS tube T4 simultaneously, turn off PMOS tube T2, and NMOS tube T4 is kept to be in
ON state makes A point current potential be latched in 0 state.On the contrary, when two STT-MRAM element M1 and M2 resistance states exchange, institute
When stating STT-MRAM element M1 and being in resistance value " low ", the STT-MRAM element M2 is in resistance value "high" state, at switch unit T7
In "ON" state, A point current potential is latched to " 1 ".It in this way can be to avoid the PMOS tube T2, the NMOS tube T4, the STT-
Power consumption penalty caused by MRAM element M1, the circuit STT-MRAM element M2 are in running order, it is particularly possible to avoid working as
When loop current is more than STT-MRAM element threshold, the STT-MRAM element M1 and the STT-MRAM element M2 state occur
Overturning, to improve cell data reliability.Fig. 3 is STT-MRAM type FPGA switch unit operation chart.
FPGA switch unit provided by the invention based on STT-MRAM is working and can be achieved to compile under non-operating mode
Journey, when no matter power vd D is in power down or power-up state, can by programming the end port PW and CON (including the end CON1 and
The end CON) carry out programming to STT-MRAM element.According to the characteristic of STT-MRAM element, it is vertical to program the electric current that end PW is passed through
When by fixing layer, separation layer and free layer, current direction is different, can change the direction of magnetization of free layer parallel or anti-parallel to
Fixing layer, to realize low-resistance and high resistant.When programming terminates, after the FPGA switch unit restores power-up state, need controlling
Signal EN processed applies high level " 1 " pulse, for identification programming state.The resistance of STT-MRAM element M1 after programming
Value is "high", and when the STT-MRAM element M2 resistance value is " low ", " 1 " pulse of control signal EN can be due to the STT-MRAM
A point current potential is set to " 0 " by the partial pressure of element M1 and the STT-MRAM element M2, thus realize that B point current potential is set to " 1 ", it is described
Switch unit T7 shutdown.
FPGA switch unit provided by the invention based on STT-MRAM based on STT-MRAM element low current programming and
High current programming mode, when the end CON1 and the end CON2 as same port in use, programming end PW needs to be passed through high current, with true
Protecting and being further separated into the current minimum of the STT-MRAM element M1 and STT-MRAM element M2 is more than threshold value.When the end CON1
Only need the electric current by being greater than threshold value can be complete respectively in use, programming end PW respectively as before and after two ports with the end CON2
At the programming of the STT-MRAM element M1 and the STT-MRAM element M2.
Program the end end PW and CON1, the end CON2 co- controlling STT-MRAM element two storage Bit read-write.If two
The original state for storing bit is consistent, can be directly written by programming end PW, in this way using the end CON1 and the end CON2 as total end
The size of current that distribution enters two storage Bit is consistent.When the original state that two store bit is inconsistent, can write respectively
Enter or is written simultaneously.When being respectively written into, can take smaller current (be greater than STT-MRAM element threshold) first pass through PW- >
CON1 is then powered off the end CON1, connects the end CON2, electric current flows through PW- > CON2 at this time.When being written simultaneously, the end CON1 and the end CON2
It can hold altogether, but need to consider the shunt effect of two storage bit resistance values, by formula:
It is the program current for flowing through the STT-MRAM element M1 in above-mentioned formula, is the STT-MRAM element M2 programming
Preceding resistance value is the resistance value before the STT-MRAM element M1 programming, is to flow through the total programming electricity of STT-MRAM element M1 and M2
Stream.As can be seen that branch current is inversely proportional with resistance, the big branch of resistance needs to guarantee that write current is more than threshold value, therefore writes
Entering electric current, separately writing mode is much bigger relatively.After write-in, as long as shutdown programming the end end PW and CON1, the end CON2, two MTJ
The resistance value state of storage would not change, until rewriting again.When reading the data of write-in, by programming end PW and CON1
End, the end CON2, the voltage for reading the both ends MTJ can recognize its write state.
After programming after the inverted device of A point current potential, B point current potential can feed back control PMOS tube end T2 and NMOS to two MTJ
The grid end of pipe T4, the STT-MRAM element M1 or the STT-MRAM element M2 and the connection of power supply or ground terminal are turned off, this
When data be in programming after latch mode.In the state of EN=0, MTJ is written and read, the current potential of B point, institute will not be changed
It is constant to state switch unit T7 hold mode.Only at EN=" 1 ", the write state of MTJ can be just read into circuit, A point electricity
Position can just change.EN=" 1 " pulse only requires a very short time, can the new state of read in memory, to realize institute
State the switch of switch unit T7.
FPGA switch unit provided by the invention based on STT-MRAM, by STT-MRAM group after programming in B point current potential
Feedback effect under, make the FPGA switch unit in the operational mode, the STT-MRAM element M1 and the STT-MRAM
The both ends element M2 are in equipotential state always, reduce to its electrical stress effect, improve the reliability of device.
Embodiment two
Second embodiment of the present invention provides the another embodiments of the FPGA switch unit based on STT-MRAM, as shown in Figure 4.
It distinguishes and is compared with embodiment one, described control unit includes PMOS tube T1, T2, T3 and NMOS tube T4；Wherein, PMOS tube T1
Grid meets control signal EN, and source electrode meets power vd D, and drain electrode connects PMOS tube T2 drain electrode；The PMOS tube T2 grid connects the reverse phase
Device output end, source electrode meet power vd D, and drain electrode connects the STT-MRAM element group, i.e., the free layer of the described STT-MRAM element M1；
PMOS tube T3 grid meets the control signal EN, grounded drain GND, and source electrode connects NMOS tube T4 drain electrode；The NMOS tube T4 grid
The inverter output is connect, source electrode is grounded GND, and drain electrode connects the STT-MRAM element group, i.e., the described STT-MRAM element M2
Fixing layer.
The FPGA switch unit based on STT-MRAM of another embodiment provided by Embodiment 2 of the present invention, is controlling
Signal EN is effective when being low level, with embodiment one on the contrary, still finally can be realized the effect being the same as example 1.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (8)
1. a kind of FPGA switch unit based on STT-MRAM characterized by comprising
STT-MRAM element group, control unit, phase inverter and switch unit；Wherein,
The STT-MRAM element group generates current potential to the phase inverter, and the phase inverter will feed back to described after the current potential reverse phase
Control unit, the current potential that described control unit controls the STT-MRAM element group under the action of phase inverter latch；
The switch unit is connected with the inverter output.
2. the FPGA switch unit based on STT-MRAM as described in claim 1, which is characterized in that described control unit includes
NMOS tube T1, T3, T4 and PMOS tube T2；Wherein,
NMOS tube T1 grid meets control signal EN, and drain electrode meets power vd D, and source electrode connects PMOS tube T2 drain electrode；The PMOS tube T2 grid
Pole connects the inverter output, and source electrode meets power vd D, and drain electrode connects the STT-MRAM element group；
NMOS tube T3 grid meets the control signal EN, and source electrode is grounded GND, and drain electrode connects NMOS tube T4 drain electrode；The NMOS tube T4
Grid connects the inverter output, and source electrode is grounded GND, and drain electrode connects the STT-MRAM element group.
3. the FPGA switch unit based on STT-MRAM as described in claim 1, which is characterized in that described control unit includes
PMOS tube T1, T2, T3 and NMOS tube T4；Wherein,
PMOS tube T1 grid meets control signal EN, and source electrode meets power vd D, and drain electrode connects PMOS tube T2 drain electrode；The PMOS tube T2 grid
Pole connects the inverter output, and source electrode meets power vd D, and drain electrode connects the STT-MRAM element group；
PMOS tube T3 grid meets the control signal EN, grounded drain GND, and source electrode connects NMOS tube T4 drain electrode；The NMOS tube T4
Grid connects the inverter output, and source electrode is grounded GND, and drain electrode connects the STT-MRAM element group.
4. the FPGA switch unit based on STT-MRAM as claimed in claim 2 or claim 3, which is characterized in that the phase inverter is
CMOS inverter, including metal-oxide-semiconductor T5 and T6, PMOS tube T5 source electrode meet power vd D, and NMOS tube T6 source electrode is grounded GND, the PMOS
Pipe T5 drain electrode and the NMOS tube T6 drain interconnection, the PMOS tube T5 grid and the NMOS tube T6 gate interconnection, and be connected to
The STT-MRAM element group.
5. the FPGA switch unit a method according to any one of claims 1-3 based on STT-MRAM, which is characterized in that the STT-
MRAM element group includes the STT-MRAM element of several series aiding connections connection.
6. the FPGA switch unit based on STT-MRAM as described in claim 5 is any, which is characterized in that the STT-MRAM
The quantity of element is 2.
7. the FPGA switch unit a method according to any one of claims 1-3 based on STT-MRAM, which is characterized in that the switch is single
Member is PMOS tube or NMOS tube；Wherein,
When the switch unit is PMOS tube, grid connects the inverter output, and source electrode is as signal input port, drain electrode
As signal output port；
When the switch unit is NMOS tube, grid connects the inverter output, and source electrode is as signal output port, drain electrode
As signal input port.
8. the FPGA switch unit a method according to any one of claims 1-3 based on STT-MRAM, which is characterized in that described to be based on
The FPGA switch unit of STT-MRAM further includes the end CON1 and the end CON2, is connect respectively at STT-MRAM element group both ends.
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