CN102194650A - Method for evaluating efficiency of processes for improving negative bias temperature instability effect - Google Patents
Method for evaluating efficiency of processes for improving negative bias temperature instability effect Download PDFInfo
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Abstract
The invention provides a method for evaluating the efficiency of processes for improving the negative bias temperature instability effect, which comprises the following steps of: (1) respectively implementing a plurality of different processes for improving the negative bias temperature instability effect on a plurality of first semiconductor devices with the same parameters; (2) applying same stress to the first semiconductor devices for a period of time; (3) judging whether the first semiconductor devices reach a rejection value, and returning to the step (2) if the first semiconductor devices do not reach the rejection value, stopping applying stress to the first semiconductor devices if the semiconductor devices reach the rejection value, and going to the step (4); and (4) selecting the process for improving the negative bias temperature instability effect, applied to the first semiconductor device which last reaches the rejection value, as the optimal process from the multiple processes.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly be used to estimate the method for improving temperature instability under minus bias pressure effect technological effect.
Background technology
In recent ten years, semi-conductor industry is obtaining huge achievement with unusual speed development aspect the integrated circuit production.At present, can produce high performance SOC (system level chip) product.Along with semiconductor technology enters into the sub-micro level, some key issues have influence on the production of semiconductor circuit, comprising NBTI (temperature instability under minus bias pressure) effect, promptly device is applied a series of phenomenons that taken place under negative grid voltage and the temperature stress condition
The NBTI effect is the key factor that influences the cmos device reliability.The PMOSFET degeneration that is caused by the NBTI effect becomes the principal element that influences device lifetime gradually.It degenerates more serious than the NMOSFET life-span of being caused by hot carrier (HC) effect.The NBTI effect is by (usually greater than 100 degrees centigrade) under the high temperature PMOSFET grid to be applied certain back bias voltage to cause.In the device aging and the course of work, all may run in this case, show as saturation current I
DsatWith constantly reducing of mutual conductance Gm, threshold voltage shift Δ V
ThThe variation of device parameters such as constantly increase, sub-threshold slope constantly reduce.It may increase the signal delay in the sequence circuit, thereby causes timing drift.In analog integrated circuit, particularly in the application of some parameter matching, the circuit working condition can apply asymmetrical bias pressure to the transistor of coupling, thereby causes tangible parameter mismatch.This will cause degenerating of performance of semiconductor device under the reduction of rate of finished products in the ageing process and the condition of work.
In recent years, semi-conductor industry bound pair NBTI effect problem has given the concern of height, and the NBTI effect has become one of the most serious integrity problem of current CMOS technology.Owing to being the increase that is interrupted the electric charge at the interface that causes because of the Si-H key, cause the generation of NBTI effect, therefore can manage to introduce other and can usually replace H with the unit of the higher bond energy of Si formation, as deuterium, the Si-D bond energy height that forms, interrupted than the Si-H key is more difficult, thereby can be reduced the increase of interface charge under bias voltage.The element that also has other same function is such as fluorine.In addition, the NBTI effect is improved.The defective of oxide layer is directly related with the NBTI effect.Mainly can obtain silicon/oxide layer interface state and oxide layer performance preferably on the technology by the technology of before the growth oxide layer, carrying out preliminary treatment and control growing oxide layer.These technologies of improving the NBTI effect are widely used in the industry.
Judge that any technological effect that improves the NBTI effect is more better, need detect corresponding sample.Therefore, carrying out the device accelerated aging tests significant to cmos device.Accelerated test device lifetime is meant under HTHP the test to the every performance of device, with the assessment device method in useful life at normal temperatures and pressures.
At first there is the sample of same parameter to adopt different technology to improve the NBTI effect to some, carry out the life test of sample then, the sample of longest-lived is best sample, and the pairing process conditions of this sample are the process conditions of improving NBTI effect the best.With the PMOS device is example, adopts three samples, and existing the improvement after the NBTI effect technology detects the semiconductor device method of life as shown in Figure 1.
As shown in Figure 1, the method for existing test NBTI effect is chosen the sample that some have same parameter, for example sample 1, sample 2 and sample 3, and these samples all have identical reference parameter, and for example each sample all has identical I
Dsat(saturation current).These samples are implemented different technology to improve its NBTI effect.Sample 1, sample 2 and sample 3 are applied a period of time t
1Stress.What the stress here should refer to that the external world applies can quicken the aging means of sample, for example with the grid voltage V of PMOS device
gBe adjusted into-2V.Then three samples are tested observation Δ I separately
DsatValue, wherein Δ I
DsatBe meant I
DsatDrift value, calculate this moment Δ I
Dsat/ I
DsatWhether reach rejection value, the value that the rejection value is here scrapped for the artificial semiconductor device of setting.The sample that will not reach rejection value afterwards applies a period of time t
2Stress, immediately sample is carried out same test then, promptly test Δ I
Dsat, calculate Δ I at this moment
Dsat/ I
DsatWhether reach rejection value; The sample that will not reach rejection value applies an end time t
3Stress, then immediately to sample test Δ I
DsatSo circulation is t up to the stress application time
sThe time, immediately sample is tested then, all scrap up to all samples.At this moment, observe the longest-lived of which sample, promptly the process conditions of the pairing NBTI of improvement of decidable respective sample are optimum condition.
This conventional detection draws formula P (t)=A * t
-nIn A and the value of n, A representative be the factor relevant with technology, the n representative be the accelerated factor of NBTI effect degeneration, t is the time of stress application, P (t) is the drift degree of reference parameter, Δ I for example described above
Dsat/ I
Dsat, can know life-span of semiconductor device after the technology of implementing to improve the NBTI effect after like this by calculating.For example, judged that this semiconductor device scrapped at known P (t)=10% o'clock, can pass through
Learn the size of t, change the life-span of semiconductor device after can obtaining implementing improving the technology of NBTI effect, and needn't measure it once more.
But, thisly existingly improve that to detect the semiconductor device method of life after the NBTI effect technology accurate inadequately, it is wrong might causing last testing result, correspondingly causes P (t)=A * t
-nThere is certain problem in formula, and the t value that promptly calculates is accurate inadequately.If used the testing result of this mistake, promptly used the technology of the pairing NBTI of the improvement effect of wrong testing result, it is best can not really finding out which kind of process conditions effectively, be unfavorable for the improvement of semiconductor device technology like this, and the technology that adopts the error result correspondence can reduce the overall performance of semiconductor device, reduce yields, make product not have competitiveness.Therefore, need a kind of new method, can accurately estimate the effect of improving NBTI effect technology,, improve the yields of semiconductor device so that improve the performance of device integral body.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order accurately to estimate the effect of improving NBTI effect technology, the present invention proposes a kind of method of improving temperature instability under minus bias pressure effect technological effect that is used to estimate, comprise the following steps: a: a plurality of first semiconductor device with identical parameters are implemented described a plurality of different technology of improving the temperature instability under minus bias pressure effect respectively; B: the big or small identical stress that described first semiconductor device is applied a period of time t; C: judge whether described first semiconductor device arrives rejection value P (t), when the described described rejection value P of the first semiconductor device no show (t), return step b; When arriving described rejection value P (t), described first semiconductor device stops the described first semiconductor device stress application is entered steps d; D: choose the technology of improving the temperature instability under minus bias pressure effect that is applied for first semiconductor device that arrives described rejection value P (t) the latest and be the optimum process in described a plurality of technology; Wherein, described rejection value P (t)=Δ T (t)/T, T is the value of the reference parameter described step a after described first semiconductor device measured immediately, and Δ T (t) be to the value T ' of the reference parameter of described first semiconductor device measurement and the difference of T behind described step b.
Preferably, also comprise,
E: the time set that described first semiconductor device of choosing in the steps d is arrived described rejection value was first life-span, described first life-span is compared with first preset value, if described first life-span is less than first preset value, then reselect the technology of improving the temperature instability under minus bias pressure effect, and return step a.
Preferably, also comprise,
E: with choosing the time set that described first semiconductor device arrives described rejection value in the steps d was first life-span, and described first life-span is compared with first preset value, if described first life-span is not less than first preset value, then entered step f; F: provide with steps d in described first semiconductor device chosen have identical parameters and implemented second semiconductor device of described optimum process; G: the parameter that described second semiconductor device has been drifted about behind described optimum process adjusts back to without the parameter before the optimum process; H: the described second semiconductor device stress application to detect the life-span, was obtained for second life-span; I: described second life-span and second preset value are compared,, and return step a if described second life-span less than second preset value, is reselected the technology of improving the temperature instability under minus bias pressure effect; If described second life-span is not less than described second preset value, then described second semiconductor device is qualified.
Preferably, the method for recalling to described parameter in the wherein said step g adopts ion implantation technology to carry out.
Preferably, wherein said reference parameter is the saturation current I of semiconductor device
Dsat
Preferably, wherein said reference parameter is the threshold voltage V of semiconductor device
Th
Preferably, wherein said rejection value is set at 10%.
The invention allows for and a kind ofly it is characterized in that, adopt following formula to calculate the life-span t of semiconductor device for the life detecting method of having used the semiconductor device that improves temperature instability under minus bias pressure effect technology:
t＝10
D，
Wherein
α=(1-P wherein
0/ P
Tar)
-m, described P (t) is a rejection value, and described A is the factor relevant with technology, and described n is the accelerated factor that the temperature instability under minus bias pressure effect is degenerated, and described t is the time of stress application, m is the factor relevant with concrete technology, 0≤m≤1; P
0Be to implement the described numerical value that improves the parameter of semiconductor device after the temperature instability under minus bias pressure effect technology, P
TarRepresentative implement described improve semiconductor device before the temperature instability under minus bias pressure effect technology the numerical value of parameter.
Preferably, it is characterized in that, work as P
0=P
TarThe time, described m=0.
Preferably, wherein said parameter is the saturation current I of semiconductor device
Dsat
Preferably, wherein said parameter is the threshold voltage V of semiconductor device
Th
Preferably, wherein said rejection value is set at 10%.
The present invention is Promethean to consider the drift value of the reference parameter after the technology of implementing to improve the NBTI effect, make when evaluation improves effect, can judge more exactly which kind of process conditions is to improve the technology optimum condition of NBTI effect, avoid the influence of drift value to estimating of reference parameter; In like manner, during the life-span, also more accurate at calculating device.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 detects semiconductor device method of life schematic diagram after the existing NBTI of the improvement effect technology;
Fig. 2 detects semiconductor device method of life schematic diagram after the embodiment according to one aspect of the invention improves NBTI effect technology;
Fig. 3 shows according to the new method of the employing of the embodiment of the invention and detects the schematic diagram that improves the semiconductor device life-span after the NBTI effect.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention adopts new method to detect to carry out semiconductor device life-span after the NBTI effect improving technology.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
In order to overcome the coarse problem that detects the semiconductor device life-span after the technology that existing enforcement improves the NBTI effect, the present invention proposes will to take into account by the drift value of implementing to improve other parameter that NBTI effect technology causes at initial detection-phase.
An embodiment according to one aspect of the invention is as described below.
At first to three various parameter same sample, promptly sample 4, sample 5, sample 6 are implemented different technology to improve the NBTI effect, and for example ion injection method etc. carries out the life test of sample then.It is pointed out that in actual industrial production is used, is not only to detect three samples, and the quantity of sample is unrestricted during detection, decide according to industrial requirements, and only be three samples here by way of example.
As shown in Figure 2, detect the semiconductor device method of life for embodiment after implementing to improve the technology of NBTI effect according to one aspect of the invention.To having implemented to improve three samples that various parameters are identical of NBTI effect technology, for example sample 4, sample 5 and sample 6 carry out the test of device accelerated aging.For example, sample 4, sample 5 and sample 6 are applied a period of time t
1Identical stress, these samples all have identical reference parameter, for example each sample all has identical I
DsatDetect I separately
Behind the dsat(t
1), and calculate P (t
1)=Δ I (t
1)/I
Behind the dsat, i.e. the first comparison value P (t
1) whether arriving rejection value, rejection value is the parameter value that the semiconductor device of artificial setting is scrapped.It is to be noted the I here
Behind the dsatFor sample being implemented improve the I that measures immediately after the NBTI effect technology
DsatValue, but not the original I that improves before the NBTI effect technology
Before the dsatValue.Wherein, Δ I (t
1) for applying a period of time t
1Identical stress after current I
Behind the dsat(t
1) value and I
Behind the dsatDifference, i.e. Δ I (t
1)
After=I
Behind the dsat-I
Behind the dsat(t
1); The sample that does not arrive rejection value is continued to apply a period of time t
2Identical stress, then immediately to sample test I
Behind the dsat(t
2), calculate P (t
2)=Δ I (t
2)/I
Behind the dsat, i.e. the second comparison value P (t
2) whether arrive rejection value, the Δ I (t here
2) for applying a period of time t
2Identical stress after current I
Behind the dsat(t
2) value and I
Behind the dsatDifference, i.e. Δ I (t
2)=I
Behind the dsat-I
Behind the dsat(t
2); The sample that does not arrive rejection value is continued to apply an end time t
3Identical stress, immediately sample is tested Δ I (t then
3) ... so circulation is t up to the stress application time
sThe time, s is integer and s 〉=1 herein, then immediately to sample test I
Behind the dsat(t
s), calculate P (t
s)=Δ I (t
s)/I
Behind the dsat, i.e. s comparison value P (t
s) whether arrive rejection value, wherein Δ I (t
s) for applying a period of time t
sIdentical stress after current I
Dsat After(t
s) value and I
Behind the dsatDifference, i.e. Δ I (t
s)=I
Behind the dsat-I
Behind the dsat(t
s).When all samples all arrive rejection value, the P (t of promptly all samples
s) all reaching rejection value, rejection value is set at 10% in the present embodiment, observes this three sample t separately
sValue, choose the sample of last arrival rejection value, i.e. the sample of s maximum, this sample has the optimum process condition that improves the NBTI effect.This be in the example for sample 4, i.e. the longest-lived of sample 4, the process conditions of sample 4 are to improve the optimum process condition of NBTI effect.
If adopt existing means that these three samples are detected, as shown in Figure 1, adopt existing means of testing to test earlier, promptly do not consider the drift value of other parameter, to utilize different process that the NBTI effect is improved and behind manufactured samples (for example sample 1, sample 2 and the sample 3) stress application, here sample 1 adopts identical technology with sample 4, and sample 2 adopts identical technology with sample 5, and sample 3 adopts identical technology with sample 6.Test result in this example shows the longest-lived of sample 3, can assert that promptly the technology that sample 3 is adopted is to improve the optimum process condition of NBTI effect.Clearly, the detected result of this existing means is inaccurate.
Result according to present embodiment shows that adopting method of the present invention can more accurately judge which kind of process conditions is to improve the technology optimum condition of NBTI effect.This be because, after implementing to improve the technology of NBTI effect, can impact other parameter, cause these parameters that in various degree drift, for example reference parameter I take place
DsatThe value of departing from objectives, desired value herein are the values of reference parameter when not implementing to improve the technology of NBTI effect.And traditional handicraft is not taken into account the drift of these reference parameters when detecting, and causes the result of detection inaccurate.The present invention all takes into account the drift value of these reference parameters, so just can judge more exactly which kind of process conditions is to improve the technology optimum condition of NBTI effect, thereby can be applied to better in the actual industrial, help the progress of semiconductor technology, improve the overall performance of semiconductor device, improve yields.
According to the present invention, adopt new formula to calculate to implement the life-span improve the semiconductor device after the NBTI effect technology, i.e. formula P (t)=A ' * t
-n=(α * A) * t
-n, α=(1-P wherein
0/ P
Tar)
-m, P
0Representative implements to improve I after the NBTI effect technology
Behind the dsatNumerical value, P
TarRepresentative implements to improve the preceding I of NBTI effect technology
DsatNumerical value, i.e. the I that is reached in the actual industrial
DsatNumerical value.Through the too much measurement of group sample, can obtain empirical A, the n of different process correspondence and the value of m.What A represented is the factor relevant with technology, and what n represented is the accelerated factor that the NBTI effect is degenerated, and t is the time of stress application, and m is the factor relevant with concrete technology, and P especially, is worked as in 0≤m≤1
0=P
TarThe time, m=0.After, just can calculate the life value of the pairing sample of corresponding technology, and not need equally testing described in the foregoing description for another example according to this formula.It is pointed out that the P (t) does not here refer in particular to is Δ I
Dsat/ I
Behind the dsat, in the same way, i.e. P (t)=Δ T (t)/T, wherein, T is for implementing to improve the value of the reference parameter of measuring immediately after the NBTI effect technology to sample, but not the original value of improving the reference parameter before the NBTI effect technology; Δ T (t) is the value T ' that applies current reference parameter behind the identical stress of a period of time t difference with T, i.e. Δ I
Dsat=T-T '.For example, P (t) can also be V
ThThe drift degree of (threshold voltage), i.e. Δ V
Th(t)/V
Behind the thNumerical value, P correspondingly
0Representative be to implement to improve V after the NBTI effect technology
Behind the thNumerical value, P
TarRepresentative implements to improve the preceding V of NBTI effect technology
ThNumerical value, i.e. the V that is reached in the actual industrial
ThNumerical value.The method of utilizing among the embodiment to be adopted can calculate formula P (t)=A ' * t
-n=(α * A) * t
-nIn the value of all parameters except that t, like this when the people when configuring the value of rejection value P (t), can calculate the life-span of corresponding semiconductor device, i.e. t=10
D, wherein
α=(1-P wherein
0/ P
Tar)
-m
The life value that the life value that calculates like this is realistic can more accurately react the life-span of improving the semiconductor device after the NBTI effect.
The flow chart of Fig. 3 shows according to the new method of the employing of the embodiment of the invention and detects the schematic diagram that improves the semiconductor device life-span after the NBTI effect.In step 301, a plurality of first samples with identical parameters are implemented a plurality of different technologies of improving the temperature instability under minus bias pressure effect respectively.In step 302, these first samples are applied the big or small identical stress of a period of time t, what this stress should refer to that the external world applies can quicken the aging means of sample.In step 303, first sample and rejection value are compared, judge whether first sample reaches rejection value.When the first sample no show rejection value, return step 302; When arriving rejection value, first sample stops the first sample device stress application is entered step 304.In step 304, to choose for first sample that arrives rejection value the latest, its life-span was first life-span, first life-span and first preset value was compared the value when first preset value is herein scrapped for the artificial sample of setting.If first life-span was returned step 301 less than first preset value, the first sample first step is defective, reselects the technology of improving the temperature instability under minus bias pressure effect; If first life-span was not less than first preset value, the first sample first step is qualified, proceeds to step 305.In step 305, provide first sample to have identical parameters and implemented second sample of described optimum process with first life-span, the reference parameter that second sample has been drifted about behind described optimum process is as I
DsatOr V
ThDeng, adjusting back to and do not implement to improve NBTI technology parameter before, this process can adopt as technologies such as ion injections carries out.In step 306, second sample is applied the life-span of identical stress test sample.The life-span of setting second sample this moment was second life-span, second life-span and second preset value was compared the value that second preset value herein reaches when scrapping for the artificial sample of setting.If second life-span, second step of second sample was defective, returned step 301, reselected the technology of improving the temperature instability under minus bias pressure effect less than second preset value; If second life-span was not less than second preset value, second step of second sample is qualified, proceeds to step 307.In step 307, second sample is qualified.Promptly in actual industrial, can select for use identical and implemented the semiconductor device of the identical technology of improving the NBTI effect with second sample parameters.
It is to be noted, first sample of choosing or second sample can be a plurality of, at this time can be in step 304 and step 306 used time and preset value be relatively when detecting first sample in a group or second sample and scrap the sample of certain percentage, if less than first preset value or second preset value, then continue to implement to improve the technology of NBTI effect, otherwise, proceed to next step.This is because in actual industrial, has implemented the identical NBTI technology of improving and does not also have the identical life-span even have the semiconductor device of identical parameters.For example, in step 304, choose 100 first samples, simultaneously these 100 first sample stress applications, can choose wherein 50 first times that sample is scrapped, compare with first preset value, if less than first preset value, then the first sample first step is defective; Otherwise, proceed to next step.
Show to detect according to the employing of aforesaid embodiment manufacturing and improve that the semiconductor device of semiconductor device life-span method can be applicable in the multiple integrated circuit (IC) after the NBTI effect according to the new method of the employing of the embodiment of the invention.According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (12)
1. one kind is used to estimate the method for improving temperature instability under minus bias pressure effect technological effect, comprises the following steps:
A: a plurality of first semiconductor device with identical parameters are implemented a plurality of different technologies of improving the temperature instability under minus bias pressure effect respectively;
B: the big or small identical stress that described first semiconductor device is applied a period of time t;
C: judge whether described first semiconductor device arrives rejection value P (t), when the described described rejection value P of the first semiconductor device no show (t), return step b; When arriving described rejection value P (t), described first semiconductor device stops the described first semiconductor device stress application is entered steps d;
D: choose the technology of improving the temperature instability under minus bias pressure effect that is applied for first semiconductor device that arrives described rejection value P (t) the latest and be the optimum process in described a plurality of technology; Wherein, described rejection value P (t)=Δ T (t)/T, T is the value of the reference parameter described step a after described first semiconductor device measured immediately, and Δ T (t) be to the value T ' of the reference parameter of described first semiconductor device measurement and the difference of T behind described step b.
2. the method for claim 1 also comprises,
E: the time set that described first semiconductor device of choosing in the steps d is arrived described rejection value was first life-span, described first life-span is compared with first preset value, if described first life-span is less than described first preset value, then reselect the technology of improving the temperature instability under minus bias pressure effect, and return step a.
3. the method for claim 1 also comprises,
E: with choosing the time set that described first semiconductor device arrives described rejection value in the steps d was first life-span, and described first life-span is compared with first preset value, if described first life-span is not less than described first preset value, then entered step f;
F: provide with steps d in described first semiconductor device chosen have identical parameters and implemented second semiconductor device of described optimum process;
G: the parameter that described second semiconductor device has been drifted about behind described optimum process adjusts back to without the parameter before the optimum process;
H: the described second semiconductor device stress application to detect the life-span, was obtained for second life-span;
I: described second life-span and second preset value are compared,, and return step a if described second life-span less than second preset value, is reselected the technology of improving the temperature instability under minus bias pressure effect; If described second life-span is not less than described second preset value, then described second semiconductor device is qualified.
4. method as claimed in claim 3, the method for recalling to described parameter in the wherein said step g adopts ion implantation technology to carry out.
5. as arbitrary described method among the claim 1-4, wherein said reference parameter is the saturation current I of semiconductor device
Dsat
6. as arbitrary described method among the claim 1-4, wherein said reference parameter is the threshold voltage V of semiconductor device
Th
7. the method for claim 1, wherein said rejection value is set at 10%.
8. one kind for the life detecting method of having used the semiconductor device that improves temperature instability under minus bias pressure effect technology, it is characterized in that, adopts following formula to calculate the life-span t of semiconductor device:
t＝10
D，
Wherein
α=(1-P wherein
0/ P
Tar)
-m, described P (t) is a rejection value, and described A is the factor relevant with technology, and described n is the accelerated factor that the temperature instability under minus bias pressure effect is degenerated, and described t is the time of stress application, m is the factor relevant with concrete technology, 0≤m≤1; P
0Be to implement the described numerical value that improves the parameter of semiconductor device after the temperature instability under minus bias pressure effect technology, P
TarThe described numerical value that improves the parameter of the preceding semiconductor device of temperature instability under minus bias pressure effect technology is implemented in representative.
9. method according to claim 8 is characterized in that, works as P
0=P
TarThe time, described m=0.
10. method as claimed in claim 8, wherein said parameter are the saturation current I of semiconductor device
Dsat
11. method as claimed in claim 8, wherein said parameter are the threshold voltage V of semiconductor device
Th
12. method as claimed in claim 8, wherein said rejection value is set at 10%.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104091770B (en) * | 2014-07-25 | 2017-06-23 | 上海华力微电子有限公司 | Negative Bias Temperature Instability appraisal procedure |
| CN108037438A (en) * | 2017-12-13 | 2018-05-15 | 中国科学院新疆理化技术研究所 | The test method that a kind of total dose irradiation influences PMOSFET Negative Bias Temperature Instabilities |
| CN111649912A (en) * | 2020-06-02 | 2020-09-11 | 兰州空间技术物理研究所 | Accelerated life test method for ion thruster |
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