CN111381139B - Semiconductor device testing method and semiconductor device testing system - Google Patents
Semiconductor device testing method and semiconductor device testing system Download PDFInfo
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- CN111381139B CN111381139B CN201811632523.2A CN201811632523A CN111381139B CN 111381139 B CN111381139 B CN 111381139B CN 201811632523 A CN201811632523 A CN 201811632523A CN 111381139 B CN111381139 B CN 111381139B
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Abstract
The present disclosure provides a semiconductor device testing method and a semiconductor device testing system for predicting NBTI lifetime of PMOS devices. The semiconductor element testing method comprises the following steps: providing a plurality of identical PMOS elements; applying an nth preset negative bias with different time lengths to the grid electrode of the nth PMOS element for multiple times at a preset temperature so as to obtain drain saturation current aging rates of the PMOS elements corresponding to the multiple time lengths of the applied voltage under the multiple preset negative biases; substituting the drain saturation current aging rates into a preset equation to determine a fitting result of the preset equation, and acquiring a drain saturation current aging rate change curve corresponding to a pressure application value and a pressure application duration; and determining the corresponding time when the drain saturation current aging rate of the PMOS element reaches a preset failure value under the standard working voltage according to the drain saturation current aging rate change curve. The semiconductor element testing method provided by the disclosure can improve the efficiency and accuracy of testing the NBTI service life of the PMOS element.
Description
Technical Field
The present disclosure relates to the field of semiconductor inspection technologies, and in particular, to a method and a system for testing a semiconductor device for predicting NBTI lifetime of a PMOS device.
Background
The NBTI (Negative bias temperature instability) effect refers to the degradation of a series of electrical parameters caused by applying a Negative gate voltage to a PMOSFET at a high temperature (the general stress condition is a gate oxide electric field at a constant temperature of 125 ℃, and the source, drain and substrate are grounded). The generation process of the NBTI effect mainly involves generation and passivation of positive charges, i.e., generation of interface trap charges and oxide layer fixed positive charges, and a diffusion process of diffusing substances. The conventional R-D model attributes the reason of NBTI generation to that holes of an inversion layer of a PMOS tube are subjected to thermal excitation under high-temperature negative gate pressure and tunnel to a silicon/silicon dioxide interface, because a large number of Si-H bonds exist on the interface, the thermally excited holes and the Si-H bonds react to generate H atoms, so that dangling bonds are left on the interface, and because of the instability of the H atoms, two H atoms are combined and released in the form of hydrogen molecules and diffuse to the/gate interface far away from the interface, so that negative drift of threshold voltage and drain saturation current aging rate is caused.
The NBTI effect causes negative drift of the aging rate of the threshold voltage and the drain saturation current of the PMOS device, an increase in the gate current, a decrease in the transconductance and the drain current, thereby causing mismatch between transistors in an analog circuit, timing drift, reduction in noise margin in a digital circuit, and even product failure. Therefore, predicting the impact of NBTI effects on device lifetime is an important loop in reliability testing in IC design.
In the related art, the relation between the drain saturation current aging rate and the working time of the PMOS device is often evaluated through a linear model, but in actual operation, the relation between the drain saturation current aging rate and the working time is nonlinear, so that the method cannot provide accurate measurement. If the change of the drain saturation current aging rate along with the time is determined according to the long-time measurement, the problems of low efficiency and huge cost are caused.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a semiconductor device testing method and a semiconductor device testing system for predicting NBTI lifetime of a PMOS device, which overcome, at least to some extent, the problems of low NBTI lifetime testing efficiency and inaccurate testing results due to the limitations and disadvantages of the related art.
According to a first aspect of the embodiments of the present disclosure, there is provided a semiconductor device testing method for predicting NBTI lifetime of a PMOS device, comprising:
providing a plurality of identical PMOS elements;
applying an nth preset negative bias with different time lengths to the grid electrode of the nth PMOS element for multiple times at a preset temperature so as to obtain drain saturation current aging rates of the PMOS elements corresponding to the multiple time lengths of the applied voltage under the multiple preset negative biases;
substituting the drain saturation current aging rates into a preset equation to determine a fitting result of the preset equation, and acquiring a drain saturation current aging rate change curve corresponding to a pressure application value and a pressure application duration;
and determining the corresponding time when the drain saturation current aging rate of the PMOS element reaches a preset failure value under the standard working voltage according to the drain saturation current aging rate change curve.
In an exemplary embodiment of the present disclosure, the applying the nth preset negative bias voltage to the gate of the nth PMOS device a plurality of times includes:
applying a negative bias Vn for a time period Tm to the gate of the PMOS device, and measuring the drain saturation current Idsat of the PMOS devicemnWhere m is [1, x ]]，n∈[1,y]X is a first preset value, and y is a second preset value;
repeating the above steps until x y drain saturation currents Idsat corresponding to the preset negative bias voltages V1-Vy are measured11～Idsatxy。
In an exemplary embodiment of the present disclosure, the preset equation includes:
△Idsat＝C*tλ，λ＝D-△Idsat*A*VBwhere Δ Idsat is the drain saturation current aging rate, A, B, C, D is a fitting constant term, V is the preset negative bias value, λ is a time exponent coefficient, and t is the pressing duration.
In an exemplary embodiment of the present disclosure, the substituting the plurality of drain saturation current aging rates into a preset equation to determine a fitting result of the preset equation includes:
substituting a plurality of preset negative bias values and corresponding drain saturation current aging rates and voltage application time lengths into the preset equation to determine the value of the fitting constant term A, B, C, D in a fitting manner;
determining the drain saturation current aging rate change curve according to the value of the fitting constant termThe expression of the line: Δ Idsat ═ C × tλ，λ＝D-△Idsat*A*VB。
In an exemplary embodiment of the present disclosure, a ratio of each of the preset negative bias voltages to the standard operating voltage is greater than 1.8.
In an exemplary embodiment of the present disclosure, the standard operating voltage includes-1.2V, and the preset negative bias voltage includes-2.0V, -2.2V, -2.4V, -2.6V.
In an exemplary embodiment of the disclosure, the obtaining the drain saturation current aging rate of the PMOS device corresponding to a plurality of pressing time periods under a plurality of preset negative biases includes:
and measuring the drain saturation current aging rate at the same preset time point after the preset negative bias voltage is stopped to be applied each time.
According to a second aspect of the present disclosure, there is provided a semiconductor element testing apparatus comprising:
the test bench is used for fixing the PMOS element;
the electrode is used for applying nth preset negative bias voltage with different time lengths to the grid electrode of the nth PMOS element for multiple times at preset temperature;
the voltage measuring device is used for measuring the drain saturation current aging rate of the PMOS element at a preset time point after the preset negative bias voltage application is finished;
a processor configured to execute the following instructions:
acquiring drain saturation current aging rates corresponding to a plurality of pressing time lengths under a plurality of preset negative biases;
substituting the drain saturation current aging rates into a preset equation to determine a fitting result of the preset equation, and acquiring a drain saturation current aging rate change curve corresponding to a pressure application value and a pressure application duration;
and determining the corresponding time when the drain saturation current aging rate of the PMOS element reaches a preset failure value under the standard working voltage according to the drain saturation current aging rate change curve.
In an exemplary embodiment of the present disclosure, further comprising:
an input device for receiving a data setting signal, wherein the data setting signal is used for setting a plurality of preset negative bias voltages and a plurality of voltage application time lengths;
and the output device is used for outputting the corresponding time when the drain saturation current aging rate of the PMOS element reaches a preset failure value under the standard working voltage.
In an exemplary embodiment of the present disclosure, the applying the nth preset negative bias voltage to the gate of the nth PMOS device a plurality of times includes:
applying a negative bias Vn for a time period Tm to the gate of the PMOS device, and measuring the drain saturation current Idsat of the PMOS devicemnWhere m is [1, x ]]，n∈[1,y]X is a first preset value, and y is a second preset value;
repeating the above steps until x y drain saturation currents Idsat corresponding to the preset negative bias voltages V1-Vy are measured11～Idsatxy。
In an exemplary embodiment of the present disclosure, the preset equation includes:
△Idsat＝C*tλ，λ＝D-△Idsat*A*VBwhere Δ Idsat is the drain saturation current aging rate, A, B, C, D is a fitting constant term, V is the preset negative bias value, and λ is a time exponent coefficient.
In an exemplary embodiment of the present disclosure, the substituting the plurality of drain saturation current aging rates into a preset equation to determine a fitting result of the preset equation includes:
substituting a plurality of preset negative biases and corresponding drain saturation current aging rates and pressing time lengths into the preset equation to determine the value of the fitting constant term A, B, C, D in a fitting manner;
determining an expression of the drain saturation current aging rate change curve according to the value of the fitting constant term: Δ Idsat ═ C × tλ，λ＝D-△Idsat*A*VB。
In an exemplary embodiment of the present disclosure, a ratio of each of the preset negative bias voltages to the standard operating voltage is greater than 1.8.
In an exemplary embodiment of the present disclosure, the standard operating voltage includes-1.2V, and the preset negative bias voltage includes-2.0V, -2.2V, -2.4V, -2.6V.
In an exemplary embodiment of the present disclosure, the voltage measuring device is configured to:
and measuring the drain saturation current aging rate at the same preset time point after the preset negative bias voltage is stopped to be applied each time.
According to the embodiment of the disclosure, the drain saturation current aging rate of the PMOS device corresponding to a plurality of pressing time periods is measured by using a plurality of negative bias voltages which are larger than the actual working voltage of the PMOS device, so that the problem of low measurement efficiency caused by using the actual working voltage for measurement can be avoided. In addition, the fitting result is determined by using drain saturation current aging rates corresponding to different negative bias voltages and different pressing time lengths, and then the relation between the drain saturation current aging rate and the working time is determined, so that the accuracy of predicting the relation can be greatly improved, and a result closer to the actual condition can be obtained when the drain saturation current aging rate of the PMOS device is determined to reach the time (namely the NBTI service life) corresponding to the preset failure value under the actual working voltage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a flowchart of a semiconductor device testing method in an exemplary embodiment of the present disclosure.
Fig. 2 is a sub-flowchart of a semiconductor device testing method in an exemplary embodiment of the present disclosure.
Fig. 3 is a sub-flowchart of a method for testing a semiconductor device in an exemplary embodiment of the present disclosure.
Fig. 4 is a diagram illustrating a variation curve of a drain saturation current aging rate of a semiconductor device testing method according to an exemplary embodiment of the disclosure.
Fig. 5 is a test result diagram of the semiconductor device testing method in an exemplary embodiment of the present disclosure.
Fig. 6 is a block diagram of a semiconductor device test apparatus in an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.
Fig. 1 schematically shows a flowchart of a semiconductor device testing method in an exemplary embodiment of the present disclosure. Referring to fig. 1, a semiconductor device testing method 100 may include:
step S1, providing a plurality of identical PMOS devices;
step S2, applying an nth preset negative bias voltage with different durations to the gate of the nth PMOS element for multiple times at a preset temperature to obtain drain saturation current aging rates of the PMOS element corresponding to multiple application durations under multiple preset negative bias voltages;
step S3, substituting a plurality of drain saturation current aging rates into a preset equation to determine a fitting result of the preset equation, and acquiring a drain saturation current aging rate change curve corresponding to a pressure application value and a pressure application time length;
and step S4, determining the corresponding time when the drain saturation current aging rate of the PMOS element reaches a preset failure value under the standard working voltage according to the drain saturation current aging rate change curve.
In the embodiment of the present disclosure, y preset negative bias voltages V1 to Vy for testing, x pressing time periods T1 to Tx, and parameters such as a preset equation for fitting, a standard operating voltage of such PMOS elements, a preset failure value of the drain saturation current aging rate, and the like may be set first.
To measure the drain saturation current aging rate, the static drain saturation current I0 of the PMOS device can be first tested, and then the dynamic drain saturation current Idsat corresponding to different negative biases and different pressing time periods can be measured, and the difference between the two can be determined as the drain saturation current aging rate Δ Idsat measured this timemn。
In some embodiments, the ratio of each of the predetermined negative bias voltages to the standard operating voltage may be set to be greater than 1.8, so as to increase the speed of the change of the aging rate of the drain saturation current, obtain more measurement data in the same time, and further improve the measurement efficiency. In one embodiment, when the standard operating voltage of the PMOS device is-1.2V, the negative bias voltage can be set to-2.0V, -2.2V, -2.4V, -2.6V, etc. Too little negative bias can possibly result in insufficient calculation data, and too much negative bias can result in prolonged measurement time and influence on test efficiency; too low a set negative bias can result in prolonged measurement time, affect test efficiency, or fail to obtain sufficient measurement data per unit time, and too high a set negative bias can affect device performance and damage the device. Therefore, the person skilled in the art can set the amount and value of the negative bias voltage according to the actual situation to balance the precision and the efficiency.
Further, the range of the pressing time period may be set to 10s to 10000s, for example. The evaluation effect on the normal working time of the device is limited due to the fact that the pressing time is too short; the long pressing time reduces the testing efficiency. Therefore, the length and number of pressing time periods can be set by one skilled in the art.
In measuring the dynamic drain saturation current, the measurement may be performed at the same preset time point after the preset negative bias voltage is stopped being applied, for example, at the 5 th millisecond after the negative bias voltage is stopped being applied, so as to ensure the consistency of the measurement data as much as possible.
In step S2, the measurement procedure is to apply a negative bias Vn with a duration Tm to the gate of the PMOS device, and then measure the drain saturation current Idsat of the PMOS devicemnWhere m is [1, x ]]，n∈[1,y]X is a first preset value, and y is a second preset value; repeating the above steps until x y drain saturation currents Idsat corresponding to the preset negative bias voltages V1-Vy are measured11～Idsatxy。
Fig. 2 is a detailed sub-flowchart of step S2 in the embodiment of the present disclosure.
Referring to fig. 2, in one embodiment, step S2 may include:
step S21, initializing m and n, and setting m-n-0;
step S22, applying a negative bias Vn with a duration Tm;
step S23, measuring the drain saturation current Idsat at a preset time point after the negative bias application is completedmn；
Step S24, judging whether m is equal to a first preset value x, if not, entering step S25 to add 1 to m, and entering step S22 again; if x, go to step S26;
step S26, judging whether n is equal to the second preset value y, if not, entering step S27 to add 1 to n, and entering step S22 again; if y, go to step S28;
step S28, return to the measured drain saturation current Idsat11～Idsatxy。
Obtaining the drain saturation current Idsat11～IdsatxyThereafter, different drain saturation current aging rates Δ Idsat may be determined from the previously measured quiescent drain saturation current I0mn：
ΔIdsatmn＝Idsatmn-I0………………………………………………(1)
In step S3, the drain saturation current aging rates Δ IdsatmnA preset equation is substituted to determine the fit.
In the embodiment of the present disclosure, the preset equation may be, for example:
△Idsat＝C*tλ，λ＝D-△Idsat*A*VB……………………………(2)
where A, B, C, D is the fitting constant term and V is the preset negative bias value.
Fig. 3 is a sub-flowchart of step S3.
Referring to fig. 3, when the preset equation is formula (2), step S3 may include:
step S31, a plurality of negative bias values and corresponding drain saturation current aging rates and pressing time periods are substituted into a preset equation, and the value of a fitting constant term A, B, C, D is determined in a fitting mode;
step S32, determining an expression of the drain saturation current aging rate change curve according to the value of the fitting constant term: Δ Idsat ═ C × tλ，λ＝D-△Idsat*A*VB. In the fitting process, when lambdan is larger than 0.16, the dynamic time power coefficient is analyzed according to the expression, when lambdan is equal to 0.16, the static time power coefficient is obtained, the value of lambdan is not reduced continuously and is a fixed constant, and the expression is not applied any more.
The fitting results for each negative bias are shown in fig. 4.
Referring to fig. 4, it can be seen that the drain saturation current aging rate variation curve Cn corresponds to each negative bias voltage, and the abscissa of Cn is the pressing time period T and the ordinate is the drain saturation current aging rate Δ Idsat. The drain saturation current aging rate change curve Cn is closer to the actual operating state of the PMOS device because of the non-linear change. It can be seen from fig. 4 that each negative bias corresponds to the same type of drain saturation current aging rate variation curve, and the fitting process described above can determine the fitting result according to each measured value.
In step S4, according to the formula (2), a drain saturation current aging rate variation curve corresponding to the normal operating voltage (e.g., -1.2V) of the PMOS device can be determined, and further, the operating time when the drain saturation current aging rate of the PMOS device reaches the preset failure value, which is also referred to as the NBTI lifetime of the PMOS device, is determined according to the abscissa corresponding to the point on the curve whose ordinate is the preset failure value.
FIG. 5 is a graph of NBTI lifetime of PMOS devices estimated using dynamic time exponentiations fitted by the method. Compared with the NBTI lifetime of the PMOS device estimated by the static exponentiation coefficient, it is clear that the NBTI lifetime of the PMOS device estimated by the dynamic time exponentiation coefficient is longer and closer to the actual lifetime of the actual product.
The NBTI service life of the PMOS element estimated by the method provided by the embodiment of the disclosure can effectively reduce estimation errors caused by adopting a linear model in the related technology; meanwhile, the negative bias value higher than the working voltage of the element is used for measurement, so that the test efficiency can be effectively improved, and the double improvement of the test efficiency and the measurement accuracy is realized.
Fig. 6 is a semiconductor device testing apparatus according to an embodiment of the present disclosure.
Referring to fig. 6, the semiconductor element testing apparatus 600 may include:
a test table 61 for fixing the PMOS element 60;
an electrode 62 for applying an nth preset negative bias voltage with different durations to the gate of the nth PMOS element for multiple times at a preset temperature;
a voltage measuring device 63 for measuring the drain saturation current aging rate of the PMOS element at a preset time point after the preset negative bias voltage application is ended;
a processor 64 arranged to execute the following instructions:
acquiring drain saturation current aging rates corresponding to a plurality of pressing time lengths under a plurality of preset negative biases;
substituting the drain saturation current aging rates into a preset equation to determine a fitting result of the preset equation, and acquiring a drain saturation current aging rate change curve corresponding to a pressure application value and a pressure application duration;
and determining the corresponding time when the drain saturation current aging rate of the PMOS element reaches a preset failure value under the standard working voltage according to the drain saturation current aging rate change curve.
In some embodiments, the semiconductor element testing apparatus 600 may further include:
an input device 66 for receiving a data set signal for setting a plurality of said preset negative bias voltages and a plurality of said press duration;
and the output device 66 is used for outputting the corresponding time when the drain saturation current aging rate of the PMOS element under the standard working voltage reaches a preset failure value.
In the embodiment of the present disclosure, y preset negative bias voltages V1 to Vy for testing, x pressing time periods T1 to Tx, and parameters such as a preset equation for fitting, a standard operating voltage of such PMOS elements, a preset failure value of the drain saturation current aging rate, and the like may be first set through the input device 66.
To measure the drain saturation current aging rate, the static drain saturation current I0 of such PMOS elements may be first measured by the voltage measuring device 63, and then the dynamic drain saturation current Idsat corresponding to different negative bias values and different pressing time periods may be measuredmnDetermining the difference between the two as the drain saturation current aging rate delta Idsat measured at this timemn。
In some embodiments, the ratio of each of the predetermined negative bias voltages to the standard operating voltage may be set to be greater than 1.8, so as to increase the speed of the change of the aging rate of the drain saturation current, obtain more measurement data in the same time, and further improve the measurement efficiency. In one embodiment, when the standard operating voltage of the PMOS device is-1.2V, the negative bias voltage can be set to-2.0V, -2.2V, -2.4V, -2.6V, etc. Too little negative bias can possibly result in insufficient calculation data, and too much negative bias can result in prolonged measurement time and influence on test efficiency; too low a set negative bias can result in prolonged measurement time, affect test efficiency, or fail to obtain sufficient measurement data per unit time, and too high a set negative bias can affect device performance and damage the device. Therefore, the person skilled in the art can set the amount and value of the negative bias voltage according to the actual situation to balance the precision and the efficiency.
Further, the range of the pressing time period may be set to 10s to 10000s, for example. The evaluation effect on the normal working time of the device is limited due to the fact that the pressing time is too short; the long pressing time reduces the testing efficiency. Therefore, the length and number of pressing time periods can be set by one skilled in the art.
In measuring the dynamic drain saturation current, the measurement may be performed at the same preset time point after the preset negative bias voltage is stopped being applied, for example, at the 6 th millisecond after the negative bias voltage is stopped being applied, so as to ensure the consistency of the measurement data as much as possible.
The measurement procedure is, for example, to control the electrode 62 to apply a negative bias Vn to the gate of the PMOS device for a time period Tm by the processor 64, and then control the voltage measuring device 63 to measure the drain saturation current Idsat of the PMOS devicemnWhere m is [1, x ]]，n∈[1,y]X is a first preset value, and y is a second preset value; repeating the above steps until x y drain saturation currents Idsat corresponding to the preset negative bias voltages V1-Vy are measured11～Idsatxy。
The detailed flow may include, for example:
step S21, initializing m and n, and setting m-n-0;
step S22, applying a negative bias Vn with a duration Tm;
step S23, measuring the drain saturation current Idsat at a preset time point after the negative bias application is completedmn；
Step S24, judging whether m is equal to a first preset value x, if not, entering step S26 to add 1 to m, and entering step S22 again; if x, go to step S26;
step S26, judging whether n is equal to the second preset value y, if not, entering step S27 to add 1 to n, and entering step S22 again; if y, go to step S28;
step S28, return to the measured drain saturation current Idsat11～Idsatxy。
The processor 64 obtains the drain saturation current Idsat11～IdsatxyThereafter, different drain saturation current aging rates Δ Idsat may be determined from the previously measured quiescent drain saturation current I0mn：
ΔIdsatmn＝Idsatmn-I0………………………………………………(1)
In the embodiment of the present disclosure, the preset equation may be, for example:
△Idsat＝C*tλ，λ＝D-△Idsat*A*VB……………………………(2)
wherein A, B, C, D is a fitting constant term, V is a preset negative bias value, λ is a time exponent coefficient, λ is a dynamic time exponent coefficient when λ is greater than 0.16, λ is a static time exponent coefficient when λ is equal to 0.16, λ value will not be reduced any more, and is a fixed constant, and the expression will not be applied any more.
The detailed calculation flow may include, for example:
step S31, a plurality of preset negative bias values and corresponding drain saturation current aging rates and pressing time periods are substituted into a preset equation, and the value of a fitting constant term A, B, C, D is determined in a fitting mode;
step S32, determining an expression of the drain saturation current aging rate change curve according to the value of the fitting constant term: Δ Idsat ═ C × tλ，λ＝D-△Idsat*A*VB。
The fitting results for each negative bias are shown in fig. 4.
Referring to fig. 4, it can be seen that the drain saturation current aging rate variation curve Cn corresponds to each negative bias voltage, and the abscissa of Cn is the pressing time period T and the ordinate is the drain saturation current aging rate Δ Idsat. The drain saturation current aging rate change curve Cn is closer to the actual operating state of the PMOS device because of the non-linear change. It can be seen from fig. 4 that each negative bias corresponds to the same type of drain saturation current aging rate variation curve, and the fitting process described above can determine the fitting result according to each measured value.
From equation (2), the processor 64 may determine a drain saturation current aging rate variation curve corresponding to a normal operating voltage (e.g., -1.2V) of the PMOS device, and further determine an abscissa corresponding to a point on the curve whose ordinate is a preset failure value, that is, an operating time when the drain saturation current aging rate of the PMOS device reaches the preset failure value, which is also referred to as NBTI lifetime of the PMOS device.
Finally, the processor 64 may control the output device 66 to output the NBTI lifetime value for such PMOS elements.
The NBTI life of the PMOS element tested by the semiconductor element testing equipment provided by the embodiment of the disclosure can effectively reduce estimation errors caused by adopting a linear model in the related technology; meanwhile, the negative bias value higher than the working voltage of the element is used for measurement, so that the test efficiency can be effectively improved, and the double improvement of the test efficiency and the measurement accuracy is realized.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (11)
1. A method for testing a semiconductor device for predicting NBTI lifetime of a PMOS device, comprising:
providing a plurality of identical PMOS elements;
applying an nth preset negative bias with different time lengths to the grid electrode of the nth PMOS element for multiple times at a preset temperature so as to obtain drain saturation current aging rates of the PMOS elements corresponding to the multiple time lengths of the applied voltage under the multiple preset negative biases;
substituting the drain saturation current aging rates into a preset equation to determine a fitting result of the preset equation, and acquiring a drain saturation current aging rate change curve corresponding to a pressure application value and a pressure application duration;
determining the corresponding time when the drain saturation current aging rate of the PMOS element reaches a preset failure value under the standard working voltage according to the drain saturation current aging rate change curve;
wherein the preset equation comprises:
Δ Idsat ═ C × t λ, λ ═ D — Δ Idsat × a × VB, where Δ Idsat is the drain saturation current aging rate, A, B, C, D is a fitting constant term, V is the value of the preset negative bias voltage, λ is a time power coefficient, and t is the pressing time period.
2. The method for testing a semiconductor device according to claim 1, wherein the applying the nth predetermined negative bias voltage to the gate of the nth PMOS device for a plurality of times with different durations comprises:
applying a negative bias Vn for a time period Tm to the gate of the nth PMOS device, and measuring the drain saturation current Idsat of the PMOS devicemnWhere m is [1, x ]]，n∈[1,y]X is a first preset value, and y is a second preset value;
repeating the above steps until x y drain saturation currents Idsat corresponding to the preset negative bias voltages V1-Vy are measured11～Idsatxy。
3. The method for testing a semiconductor device according to claim 1, wherein a ratio of each of the predetermined negative bias voltages to the standard operating voltage is greater than 1.8.
4. The method for testing a semiconductor device according to claim 1 or 3, wherein the standard operating voltage comprises-1.2V, and the predetermined negative bias voltage comprises-2.0V, -2.2V, -2.4V, -2.6V.
5. The method of claim 1, wherein obtaining the drain saturation current degradation rate of the PMOS device for a plurality of pressing time periods under a plurality of predetermined negative bias voltages comprises:
and measuring the drain saturation current aging rate at the same preset time point after the preset negative bias voltage is stopped to be applied each time.
6. A semiconductor element test apparatus, comprising:
the test bench is used for fixing the PMOS element;
the electrode is used for applying nth preset negative bias voltage with different time lengths to the grid electrode of the nth PMOS element for multiple times at preset temperature;
the voltage measuring device is used for measuring the drain saturation current aging rate of the PMOS element at a preset time point after the preset negative bias voltage application is finished;
a processor configured to execute the following instructions:
acquiring drain saturation current aging rates corresponding to a plurality of pressing time lengths under a plurality of preset negative biases;
substituting the drain saturation current aging rates into a preset equation to determine a fitting result of the preset equation, and acquiring a drain saturation current aging rate change curve corresponding to a pressure application value and a pressure application duration;
determining the corresponding time when the drain saturation current aging rate of the PMOS element reaches a preset failure value under the standard working voltage according to the drain saturation current aging rate change curve;
wherein the preset equation comprises:
△Idsat＝C*tλ，λ＝D-△Idsat*A*VBwhere Δ Idsat is the drain saturation current aging rate, A, B, C, D is a fitting constant term, V is the value of the preset negative bias, λ is a time exponent coefficient, and t is the pressing time duration.
7. The semiconductor element test apparatus according to claim 6, further comprising:
an input device for receiving a data setting signal, wherein the data setting signal is used for setting a plurality of preset negative bias voltages and a plurality of voltage application time lengths;
and the output device is used for outputting the corresponding time when the drain saturation current aging rate of the PMOS element reaches the preset failure value under the standard working voltage.
8. The semiconductor device test apparatus of claim 6, wherein the applying the nth predetermined negative bias voltage to the gate of the nth PMOS device a plurality of times, the nth predetermined negative bias voltage having different durations, comprises:
applying a negative bias Vn for a time period Tm to the gate of the nth PMOS device, and measuring the drain saturation current Idsat of the PMOS devicemnWhere m is [1, x ]]，n∈[1，y]X is a first predetermined value, y is the second predetermined valueSecondly, presetting a value;
repeating the above steps until x y drain saturation currents Idsat corresponding to the preset negative bias voltages V1-Vy are measured11～Idsatxy。
9. The semiconductor device test apparatus of claim 6, wherein a ratio of each of the predetermined negative bias voltages to the standard operating voltage is greater than 1.8.
10. The semiconductor device test apparatus of claim 6 or 9, wherein the standard operating voltage comprises-1.2V, and the preset negative bias voltage comprises-2.0V, -2.2V, -2.4V, -2.6V.
11. The semiconductor element test apparatus according to claim 6, wherein the voltage measuring device is configured to:
and measuring the drain saturation current aging rate at the same preset time point after the preset negative bias voltage is stopped to be applied each time.
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| CN112327124B (en) * | 2020-09-30 | 2021-11-12 | 河海大学 | Method for monitoring thermal fatigue aging of IGBT module and method for non-uniform aging |
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