JP2015153884A - Nitride semiconductor device manufacturing method, nitride semiconductor device, diode and field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device capable of inhibiting a decrease in withstand voltage and achieving improvement of manufacturing yield.SOLUTION: In a manufacturing method of a nitride semiconductor device which comprises: a semiconductor laminate including a substrate, a first semiconductor layer on the substrate, a second semiconductor layer having a band gap wider than that of the first semiconductor layer on average, and a third semiconductor layer which is selectively formed in an upper layer of the second semiconductor layer and has a band gap narrower than that of the second semiconductor layer on average; a first electrode provided on at least on some layers of semiconductor layers which compose the semiconductor laminate; and a second electrode provided on at least on some layers of the semiconductor layers which compose the semiconductor laminate, an etching condition of forming the third semiconductor layer into a predetermined shape by etching is set at a condition capable of etching the third semiconductor layer to have a film thickness obtained by adding a value of not less than 50 nm and not more than 300 nm to a design film thickness of the third semiconductor layer.

Description

  The present invention relates to a method for manufacturing a nitride semiconductor device, a nitride semiconductor device, a diode, and a field effect transistor.

  Wide bandgap semiconductors represented by nitride semiconductors have high dielectric breakdown voltage, good electron transport properties, and good thermal conductivity, so they are very attractive as materials for semiconductor devices for high temperature, high power, or high frequency. Is. Further, for example, a field effect transistor (FET) having an AlGaN / GaN heterojunction structure generates two-dimensional electron gas (2DEG) at the heterojunction interface due to piezo polarization and spontaneous polarization. Yes. This 2DEG has high electron mobility and carrier density, and has attracted much attention. Therefore, Schottky barrier diodes (SBD) and heterojunction field effect transistors (HFETs) using such an AlGaN / GaN heterojunction structure have high breakdown voltage, low on-resistance, and high speed. It has switching speed and is very suitable for power switching application.

  Patent Document 1 describes a configuration in which current collapse is suppressed and leakage is reduced by selectively providing a field plate layer (GaN FP layer) made of gallium nitride on an electron supply layer.

JP 2011-54845 A

T. Sasaki et al., "Analysis of two-step-growth conditions for GaN on an AlN buffer layer," J. Appl. Phys. 77, 193 (1995)

  However, when the inventors made a prototype of a nitride semiconductor device as described in Patent Document 1, for example, the inventors found a problem that the breakdown voltage might be lower than the value expected from the design.

  The present invention has been made in view of the above, and an object of the present invention is to provide a nitride semiconductor device manufacturing method, a nitride semiconductor device, a diode, and an electric field that can suppress a decrease in breakdown voltage in the nitride semiconductor device. It is to provide an effect transistor.

  In order to solve the above-described problems and achieve the above object, a method of manufacturing a nitride semiconductor device according to the present invention includes a base, a first semiconductor layer made of a nitride semiconductor provided on the base, and a first semiconductor. A second semiconductor layer formed of a nitride semiconductor having an average wider band gap than that of the first semiconductor layer and an upper layer of the second semiconductor layer selectively provided in a predetermined shape and provided in a predetermined shape A semiconductor stacked body including a third semiconductor layer made of a nitride semiconductor having an average narrower band gap than the layers, and a first electrode provided on at least a part of the semiconductor layers constituting the semiconductor stacked body And a second electrode provided on at least a part of the semiconductor layers constituting the semiconductor stacked body and spaced apart from the first electrode, in a method for manufacturing a nitride semiconductor device, Etching conditions for forming the body layer in a predetermined shape by an etching method are etching conditions that can etch the third semiconductor layer having a thickness obtained by adding a value of 50 nm or more to the design thickness of the third semiconductor layer. It is characterized by.

  In the method for manufacturing a nitride semiconductor device according to the present invention, in the above invention, when the third semiconductor layer is formed into a predetermined shape by an etching method, the nitride semiconductor device has a thickness of 50 nm or more and 300 nm or less with respect to a design film thickness of the third semiconductor layer. Etching conditions for etching the third semiconductor layer having a thickness obtained by adding the values are characterized.

  In the method for manufacturing a nitride semiconductor device according to the present invention, in the above invention, the third semiconductor layer selectively provided on the second semiconductor layer when the third semiconductor layer is formed into a predetermined shape by an etching method. Etching is performed until the surface of the second semiconductor layer is exposed to the entire surface in a region other than the formation region.

  In the method for manufacturing a nitride semiconductor device according to the present invention, in the above invention, the semiconductor stacked body has an Al higher than the average Al composition ratio of the second semiconductor layer between the second semiconductor layer and the third semiconductor layer. It has the 4th semiconductor layer which consists of a nitride semiconductor which has a composition ratio, It is characterized by the above-mentioned.

  In the method for manufacturing a nitride semiconductor device according to the present invention, in the above invention, the third semiconductor layer selectively provided on the second semiconductor layer when the third semiconductor layer is formed into a predetermined shape by an etching method. Etching is performed until the surface of the fourth semiconductor layer is exposed to the entire surface in a region other than the formation region.

  In the method for manufacturing a nitride semiconductor device according to the present invention, in the above invention, the second semiconductor layer includes a plurality of nitride semiconductor layers in which nitride semiconductor layers having at least two different Al composition ratios are stacked a plurality of times. It has the superlattice structure which becomes.

  The method for manufacturing a nitride semiconductor device according to the present invention is characterized in that, in the above invention, the Al composition ratio in at least the surface side region of the second semiconductor layer is 40% or more.

  The method for manufacturing a nitride semiconductor device according to the present invention includes an etching condition in which, in the above-described invention, the etching condition is such that the etching selectivity of the third semiconductor layer to the semiconductor layer below the third semiconductor layer is 25 times or more. It is characterized by that.

  The method for manufacturing a nitride semiconductor device according to the present invention includes a base, a first semiconductor layer made of a nitride semiconductor provided on the base, an upper layer of the first semiconductor layer, and more average than the first semiconductor layer. And a second semiconductor layer made of a nitride semiconductor having a wide band gap, and a nitride semiconductor which is selectively provided in a predetermined shape above the second semiconductor layer and which has an average narrower band gap than the second semiconductor layer. A semiconductor stack including the third semiconductor layer; a first electrode provided on at least a part of the semiconductor layers constituting the semiconductor stack; and at least one of the semiconductor layers constituting the semiconductor stack. In a method for manufacturing a nitride semiconductor device comprising: a second electrode provided on a portion of a layer and spaced apart from a first electrode, before forming the third semiconductor layer into a predetermined shape by an etching method Characterized in that it comprises an etch-back process to planarize the surface of the third semiconductor layer.

  The method for manufacturing a nitride semiconductor device according to the present invention includes a base, a first semiconductor layer made of a nitride semiconductor provided on the base, an upper layer of the first semiconductor layer, and more average than the first semiconductor layer. And a second semiconductor layer made of a nitride semiconductor having a wide band gap, and a nitride semiconductor which is selectively provided in a predetermined shape above the second semiconductor layer and which has an average narrower band gap than the second semiconductor layer. A semiconductor stack including the third semiconductor layer; a first electrode provided on at least a part of the semiconductor layers constituting the semiconductor stack; and at least one of the semiconductor layers constituting the semiconductor stack. In a method for manufacturing a nitride semiconductor device comprising: a second electrode provided apart from a first electrode on a part layer; and a selective growth mass having an opening of a predetermined shape in an upper layer of the second semiconductor layer Forming a layer, after growing the third semiconductor layer within the opening, by removing the selective growth mask layer, and forming a third semiconductor layer into a predetermined shape.

  A nitride semiconductor device according to the present invention is provided on a base, a first semiconductor layer made of a nitride semiconductor provided on the base, an upper layer of the first semiconductor layer, and on an average band gap than the first semiconductor layer. A second semiconductor layer made of a nitride semiconductor having a large width, and a third semiconductor layer made of a nitride semiconductor that is selectively provided above the second semiconductor layer and has an average narrower band gap than the second semiconductor layer A semiconductor stacked body, a first electrode provided on at least a part of the semiconductor layers constituting the semiconductor stacked body, and on at least a part of the semiconductor layers constituting the semiconductor stacked body In a nitride semiconductor device including a second electrode provided apart from the first electrode, a protruding portion having a size of 12 nm or more exists on the surface of the third semiconductor layer, and 12 on the surface of the second semiconductor layer. Wherein the protruding portion is less than m are present.

  A nitride semiconductor device according to the present invention is provided on a base, a first semiconductor layer made of a nitride semiconductor provided on the base, an upper layer of the first semiconductor layer, and on an average band gap than the first semiconductor layer. A second semiconductor layer made of a nitride semiconductor having a large width, a third semiconductor layer made of a nitride semiconductor that is selectively provided above the second semiconductor layer and has an average narrower band gap than the second semiconductor layer, and A semiconductor stack including a fourth semiconductor layer provided between the second semiconductor layer and the third semiconductor layer and made of a nitride semiconductor having an Al composition ratio higher than the average Al composition ratio of the second semiconductor layer; A first electrode provided on at least a part of the semiconductor layers constituting the body, and spaced apart from the first electrode on at least a part of the semiconductor layers constituting the semiconductor laminate. In a nitride semiconductor device provided with the second electrode provided, the protrusions of 12 nm or more exist on the surface of the third semiconductor layer, and the protrusions of less than 12 nm exist on the surface of the fourth semiconductor layer. It is characterized by.

  In the above-described invention, the nitride semiconductor device according to the present invention is a third semiconductor device provided on at least a part of the layers constituting the semiconductor multilayer body and spaced apart from the first electrode and the second electrode. An electrode is further provided.

  A field effect transistor according to the present invention has the structure of the nitride semiconductor device according to the above invention, wherein the first electrode is a gate electrode, the second electrode is a drain electrode, and the third electrode is a source electrode. To do.

  The diode according to the present invention has the structure of the nitride semiconductor device according to the above-described invention, wherein the first electrode is an anode electrode and the second electrode is a cathode electrode.

  According to the method for manufacturing a nitride semiconductor device, the nitride semiconductor device, the diode, and the field effect transistor according to the present invention, it is possible to suppress a decrease in breakdown voltage in the nitride semiconductor device.

FIG. 1 is a schematic cross-sectional view showing the structure of an SBD as a nitride semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a schematic cross-sectional view for illustrating the method for manufacturing the nitride semiconductor device according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional view for illustrating the method for manufacturing the nitride semiconductor device according to the first embodiment of the present invention. FIG. 4 is a schematic cross-sectional view for illustrating the method for manufacturing the nitride semiconductor device according to the first embodiment of the present invention. FIG. 5 is a schematic cross-sectional view for illustrating the method for manufacturing the nitride semiconductor device according to the first embodiment of the present invention. FIG. 6 is a schematic cross-sectional view for explaining a method of manufacturing a nitride semiconductor device according to the prior art as a comparative example. FIG. 7 is a graph showing the dependence of the yield of the nitride semiconductor device according to the first embodiment of the present invention on the thickness of the overetched film. FIG. 8 is a schematic cross-sectional view showing the structure of the HEMT as the nitride semiconductor device according to the second embodiment of the present invention. FIG. 9 is a schematic cross-sectional view for illustrating the method for manufacturing the nitride semiconductor device according to the third embodiment of the present invention. FIG. 10 is a schematic cross-sectional view for illustrating the method for manufacturing the nitride semiconductor device according to the third embodiment of the present invention. FIG. 11 is a schematic cross sectional view for illustrating the method for manufacturing the nitride semiconductor device according to the fourth embodiment of the present invention. FIG. 12 is a schematic cross sectional view for illustrating the method for manufacturing the nitride semiconductor device according to the fourth embodiment of the present invention. FIG. 13 is a schematic cross-sectional view showing the structure of the SBD for explaining the cause of the low yield of the nitride semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, this invention is not limited by the following embodiment. In the drawings, the same or corresponding elements are denoted by the same reference numerals as appropriate, and repeated descriptions are omitted as appropriate. Furthermore, it should be noted that the drawings are schematic, and dimensional relationships between elements may differ from actual ones. Even between the drawings, there are cases in which portions having different dimensional relationships and ratios are included. Further, “upper”, “upper” or “upper” and “lower”, “lower” or “lower” used in the description of the following embodiments are perpendicular to the main surface of the substrate of the semiconductor device, respectively. It should also be noted that the direction of moving away and the direction of approaching the main surface of the substrate are shown and do not necessarily coincide with the vertical direction in the mounting state of the semiconductor device.

  First, in describing embodiments of the present invention, in order to facilitate the understanding of the present invention, an intensive study conducted by the present inventor to solve the above-described problems will be described. First, a description will be given of a conventional nitride semiconductor device that has been the subject of intensive studies by the inventors.

First, the present inventor has made various studies on the conventional causes of low breakdown voltage yield, and in a nitride semiconductor device having a breakdown voltage with respect to a voltage of 600 V or higher, such as SBD or HEMT, the field is formed above the electron supply layer. It was noted that a plate layer (FP layer) was provided. That is, in a high breakdown voltage nitride semiconductor device, a field plate layer made of gallium nitride (GaN) is selectively provided on the electron supply layer made of gallium aluminum nitride (AlGaN) for electric field relaxation. Further, when crystal growth of a GaN layer is performed, for example, if a specific growth condition such as a substrate temperature is changed, it is known that a projecting defect made of GaN is generated on the surface of the GaN layer depending on the growth condition (non-patent) Reference 1). The present inventor similarly applies to nitride semiconductor layers such as In _u Al _v Ga _1-uv N layers (0 ≦ u ≦ 1, 0 ≦ v ≦ 1, 0 <u + v <1) other than the GaN layer. It was confirmed that a projecting defect was generated.

  Therefore, the present inventor has recalled that a protruding defect on the surface of the GaN layer, which may be generated depending on the growth conditions, is the cause of the breakdown voltage reduction. Specifically, the projecting defects generated when the GaN layer is epitaxially grown on the electron supply layer cannot be removed by etching when the GaN layer is formed into a predetermined shape by selective etching and the field plate layer is formed. It was presumed that the protrusion defects remained on the surface of the electron supply layer in the region other than the field plate layer had an effect on the breakdown voltage reduction. From the relationship between etching conditions (overetching amount) and yield, which will be described later, the height of the projecting defect generated during the epitaxial growth of the field plate layer was estimated to be about 50 to 200 nm.

  Therefore, the present inventor conducted various studies on such a projecting defect. FIG. 13 is a schematic cross-sectional view showing a Schottky barrier diode (SBD) as a nitride semiconductor device in which such protruding defects exist.

  As shown in FIG. 13, the SBD 100 having protrusions is formed on a base 101 having a substrate and a buffer layer, an electron transit layer 102 made of undoped GaN (u-GaN), and an electron supply layer 103 made of AlGaN. Are selectively provided with a field plate layer 105 a made of GaN, an anode electrode 106 A and a cathode electrode 106 C, and an insulating film 107. Then, 2DEG layers A and a are generated at the interface between the electron transit layer 102 and the electron supply layer 103. Since the field plate layer 105a is provided, the carrier concentration (2DEG concentration) of the lower 2DEG layer a is lower than that of the 2DEG layer A. In the SBD 100 shown in FIG. 13, a protruding portion 105A exists between the anode electrode 106A and the cathode electrode 106C.

  And this inventor performed the simulation regarding electric field concentration in this SBD100. That is, the 2DEG concentration is locally reduced in the 2DEG layer b of the electron transit layer 102 in the lower layer of the region where the protrusion 105A exists. As a result, it has been found that, when the SBD 100 is in operation, electric field concentration may occur at the cathode electrode 106C side end of the projecting portion 105A (the portion surrounded by P in FIG. 13), which may cause a decrease in breakdown voltage. . This decrease in breakdown voltage is not limited to SBD 100, but is a phenomenon common to various nitride semiconductor devices such as HEMT that use 2DEG for a channel and provide a field plate layer for electric field relaxation.

  Therefore, the present inventor has studied the point where the protruding portion 105A is formed in the upper layer of the electron supply layer 103. The present inventor then supplies electrons when forming the field plate layer 105a when a projecting defect occurs on the surface of the GaN layer epitaxially grown by metal organic chemical vapor deposition (MOCVD). It was estimated that the GaN layer remained on the upper layer 103 to form the protruding portion 105A.

  Then, the present inventor has studied a manufacturing method in which no protruding defects that cause electric field concentration remain in the nitride semiconductor device based on the above-described investigation on the protruding defects. Then, the present inventor etches deeper than the conventional etching conditions with respect to the film thickness of the semiconductor layer to be the field plate layer in the etching performed when forming the field plate layer in a predetermined shape. I recalled using the so-called over-etching conditions. As described above, in the nitride semiconductor device, the protruding portion can be prevented from remaining in the upper layer of the electron supply layer, and the electric field concentration caused by the protruding defect can be suppressed. The production yield of the nitride semiconductor device as a product can be improved. The embodiment described below has been devised based on the above-mentioned diligent study.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing a configuration of an SBD as a nitride semiconductor device according to the first embodiment of the present invention. That is, in the SBD 1 as the semiconductor device in the first embodiment, the electron transit layer 12, the electron supply layer 13, and the etching sacrificial layer 14 are sequentially laminated on the base 11. Further, an anode electrode 16A as a Schottky electrode and a cathode electrode 16C as an ohmic electrode spaced apart from the anode electrode 16A are selectively provided on the etching sacrificial layer. Furthermore, a field plate layer 15a is provided on the etching sacrificial layer 14 on the anode electrode 16A side so as to be separated from the cathode electrode 16C. The field plate layer 15a is composed of a part of the semiconductor layer 15 described later. An insulating film 17 is provided so as to cover at least a part of the etching sacrificial layer 14 and the field plate layer 15a, and the anode electrode 16A and the cathode electrode 16C.

The base 11 is composed of, for example, a substrate and a buffer layer. The substrate is, for example, a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, a GaN substrate, an AlN substrate, a silicon carbide (SiC) substrate, a carbon (C) substrate, or sapphire (Al ₂ O _3). ) It consists of a substrate. The buffer layer is made of, for example, a GaN layer or an AlN layer. Note that the buffer layer may be semi-insulated by adding impurities such as C, Fe, and Mg to the buffer layer. Moreover, you may provide the various layers required for the structure of a nitride semiconductor device as needed. And the base | substrate 11 is comprised by these board | substrates, the buffer layer, and the other layer as needed.

  The electron transit layer 12 as the first semiconductor layer is made of undoped gallium nitride (u-GaN) having a film thickness of 700 nm (0.7 μm), for example. Note that a nitride semiconductor material other than GaN may be used as the material constituting the electron transit layer 12, and when AlGaN is used, the Al composition ratio is preferably 5% or less.

The electron supply layer 13 as the second semiconductor layer has a superlattice structure including a superlattice layer in which a plurality of at least two types of group III nitride semiconductors having different Al composition ratios and different band gaps are stacked. Further, in the first embodiment, the electron supply layer 13 has, for example, an Al _x Ga _1-x N pseudo mixed crystal structure with an average Al composition ratio X, and at least two different maximum Al composition ratios x1 or minimum The AlGaN superlattice layer is formed by laminating a plurality of Al _x Ga _1-x N layers having an Al composition ratio x having various values of the Al composition ratio x2. For the Al composition ratio x, x2 <X <x1. In the first embodiment, the average Al composition ratio X of the electron supply layer 13 is a desired 2DEG concentration in the 2DEG layer A having a high 2DEG concentration at the interface with the electron transit layer 12 on the assumption that 0 <X <1. 10% to 40% (0.1 ≦ X ≦ 0.4) is preferable, 15% to 35% (0.15 ≦ X ≦ 0.35) is more preferable, and 20% More preferably, it is 30% or less (0.2 ≦ X ≦ 0.3). Further, from the viewpoint of sheet resistance in the Al _x Ga _1-x N superlattice layer, and also from the viewpoint of lattice relaxation that can be laminated freely against strain, the average Al composition ratio X of the electron supply layer 13 is preferably in the above range. . Here, the band gap of the electron supply layer 13 is an average band gap, and specifically, is a band gap value weighted (integrated) by the layer thickness ratio of each semiconductor layer constituting the stacked structure. The electron supply layer 13 is configured such that the average band gap is wider than the band gap of the electron transit layer 12.

Of the AlGaN layers constituting the electron supply layer 13, the Al _x1 Ga _1-x1 N layer having the maximum Al composition ratio x1 and the Al _x2 Ga _1-x2 N layer having the minimum Al composition ratio x2 are layered. From the viewpoint that the electron wave function of the 2DEG layer A must be exuded by the desired average Al composition ratio X, more specifically, for example, 0.5 nm or more. 4.0 nm or less, preferably 0.5 nm or more and 3.5 nm or less, more preferably 0.5 nm or more and 3.0 nm or less. In the first embodiment, for example, the thickness is about 1.5 nm. In addition, the thickness of each Al _x Ga _1-x N layer is preferably less than or equal to the critical thickness in order not to cause misfit dislocations. Specifically, the critical film thickness of the Al _x Ga _1-x N layer is about 5 nm when the Al composition ratio x is 0.6 with respect to the lattice constant of the GaN layer, and the Al composition ratio x is 0.1. In some cases, it is about 100 nm. The critical film thickness is not necessarily limited to these film thicknesses because the film thickness differs depending on the adjacent layers in the stacked structure. Based on the above conditions, the film thickness, the number of layers, or the number of layers of each Al _x Ga _1-x N layer are appropriately determined according to the 2DEG concentration set concentration of the 2DEG layer A and the design of the nitride semiconductor device. The optimal value is selected. In the first embodiment, the 2DEG concentration is adjusted to be less than 3 × 10 ¹³ cm ^−2, for example.

The lower limit of the film thickness of the electron supply layer 13, and the Al _x2 Ga _1-x2 N layer of Al _x1 Ga _1-x1 N layer and the minimum Al composition ratio x2 of the maximum Al composition ratio x1 electron supply layer 13 In consideration of the structure composed of a set of Al _x1 Ga _1-x1 N / Al _x2 Ga _1-x2 N superlattice layers, the thickness is preferably 2 nm or more, and the 2DEG concentration of the 2DEG layer A is increased. In consideration, it is preferably 5 nm or more, more preferably 10 nm or more. The upper limit of the film thickness of the electron supply layer 13 is preferably a critical film thickness or less at which no misfit dislocation occurs, and considering the limit of ohmic contact, it is 100 nm or less, preferably 50 nm or less, and more preferably 30 nm or less. Is preferred. And in this Embodiment 1, it is 20 nm, for example.

The etching sacrificial layer 14 as the fourth semiconductor layer shown in FIG. 1 is an Al _Y Ga _1-Y N layer (0 <Y) where, for example, the average Al composition ratio Y is larger than the average Al composition ratio X of the electron supply layer 13. <1, X <Y). This is because, when a semiconductor layer 15 to be described later formed on the Al _Y Ga _1-Y N layer is made of a material having an Al composition ratio of 0 or extremely small, such as a GaN layer, the etching rate of the semiconductor layer 15 is This is because the AlGaN layer is extremely large, approximately 25 times or more than the AlGaN layer, and the AlGaN layer acts extremely effectively as an etching stop for the GaN layer. In order to increase the etching selectivity with respect to the lower semiconductor layer of the semiconductor layer 15 to, for example, 25 times or more, preferably 50 times or more in this way, the Al composition ratio of the etching sacrificial layer 14 which is the lower semiconductor layer It is preferable to set Y to 40% or more.

  The etching sacrificial layer 14 is configured so that the etching rate can be controlled during overetching of the etching sacrificial layer 14 in the etching for forming the field plate layer 15a having a predetermined shape. Therefore, the etching can be stopped with good controllability in the etching sacrificial layer 14 without the etching reaching the electron supply layer 13.

  Here, the thickness of the etching sacrificial layer 14 is preferably set to a thickness that can be precisely controlled by etching for forming the field plate layer 15a by controlling the etching rate during over-etching. For example, it is preferably 1 nm or more, more preferably 2 nm or more. The thickness of the etching sacrificial layer 14 is preferably 12 nm or less in order to suppress deterioration of crystallinity. Therefore, the thickness of the etching sacrificial layer 14 is 1 nm or more and 12 nm or less, and in this first embodiment, for example, about 4 nm. Here, the film thickness of the etching sacrificial layer 14 is the film thickness of the etching sacrificial layer 14 in the region not finally etched in the lower layer of the field plate layer 15a.

  In addition, when the above-described protrusion defect exists on the surface of the semiconductor layer 15 formed on the etching sacrificial layer 14, the shape of the protrusion defect generated on the surface of the semiconductor layer 15 is formed on the surface of the etching sacrifice layer 14. 14A may be formed. In this case, the height h of the projecting portion 14A from the region other than the projecting portion 14A of the etching sacrificial layer 14 can take various values depending on the etching selectivity between the semiconductor layer 15 and the etching sacrificial layer 14. . In the first embodiment, when the etching selectivity between the semiconductor layer 15 and the etching sacrificial layer 14 is 25 times or more, the height h of the protrusion 14A on the surface of the etching sacrificial layer 14 is greater than 0 nm and less than 12 nm. Of about 4 nm. By such over-etching, it is possible to prevent the protrusions made of a part of the semiconductor layer 15 from existing on the etching sacrificial layer 14, and the height h of the protrusions 14A on the surface of the etching sacrifice layer 14 is less than 12 nm. Therefore, a decrease in breakdown voltage due to local electric field concentration can be suppressed.

Further, a field plate layer 15a made of a part of a semiconductor layer 15 described later as a third semiconductor layer is selectively provided on the etching sacrificial layer 14 or the electron supply layer 13 in accordance with the structure of the nitride semiconductor device. . The field plate layer 15a changes the 2DEG concentration of 2DEG generated in the electron transit layer 12 to at least two levels, and specifically reduces the average band gap of the electron supply layer 13 in order to reduce the 2DEG concentration. _Consists of an In _u Al _v Ga _1-uv N layer (0 ≦ u ≦ 1, 0 ≦ v ≦ 1, 0 ≦ u + v <1). Further, the 2DEG concentration of 2DEG generated in the electron transit layer 12 decreases as the film thickness of the field plate layer 15a increases. The film thickness of the field plate layer 15a is 20 nm or more and 200 nm or less, preferably 20 nm or more and 100 nm or less, which makes it easy to control the 2DEG concentration by controlling the film thickness using growth and etching. The thickness is 20 nm or more and 80 nm or less, which is less susceptible to variations in 2DEG concentration due to thickness variations. In the first embodiment, the field plate layer 15a is made of, for example, a GaN layer having a thickness of 30 nm. That is, in this SBD 1, since the field plate layer 15a is provided, the 2DEG concentration of the 2DEG layer a is, for example, 7 × 10 ¹² cm ⁻² or less, and the 2DEG concentration is higher than 7 × 10 ¹² cm ^−2. Compared to the 2DEG layer A, the concentration is reduced to a low level. Thereby, the electric field strength in the portion where the field plate layer 15a is provided can be suppressed.

  Here, in some cases, a protrusion 15A including at least a part of the above-described protrusion defect is formed on the surface of the field plate layer 15a. Although FIG. 1 shows a state in which all the projecting defects remain on the field plate layer 15a as projecting portions 15A, the projecting defects form the field plate layer 15a in a predetermined shape. In some cases, the protrusion 15A may be formed from a part of the protrusion defect, for example, when it exists over the outer peripheral portion of the predetermined shape. When the projecting portion 15A exists on the field plate layer 15a, the height H from the flat surface other than the projecting portion 15A of the field plate layer 15a in the projecting portion 15A is 12 nm or more and the projecting defect is not present. The maximum height or less, specifically, for example, 300 nm or less. In addition, when the inventor measured the withstand voltage with respect to the SBD 1 in which the protruding portion 15A is formed on the surface of the field plate layer 15a, the protruding portion 15A exists on the surface of the field plate layer 15a. It was confirmed that the breakdown voltage of the SBD 1 did not decrease. That is, it was confirmed that the protrusions 15A on the surface of the field plate layer 15a do not cause a decrease in the breakdown voltage of the SBD 1. Further, in the portion of the 2DEG layer a below the projecting portion 15A, the 2DEG concentration is further reduced by partial thickening of the field plate layer 15a due to the presence of the projecting portion 15A, so that electric field concentration can be further reduced. There is also an effect.

  The electron transit layer 12, the electron supply layer 13, the etching sacrificial layer 14, and the field plate layer 15a (semiconductor layer 15) described above constitute the semiconductor stacked body according to the first embodiment. Depending on the configuration of the nitride semiconductor device, the semiconductor stacked body may be composed of an electron transit layer 12, an electron supply layer 13, and a field plate layer 15a (semiconductor layer 15). Further, when the uppermost layer of the electron supply layer 13 is substituted for the etching sacrificial layer without providing the etching sacrificial layer 14, the electron transit layer 12, the electron supply layer 13, and the field plate layer 15a (semiconductor layer 15) are used. A semiconductor laminate is constructed.

  The anode electrode 16A as the first electrode has, for example, a Ni / Au laminated structure in which the lower electrode layer is a Ni layer and the upper electrode layer is an Au layer. As a result, the anode electrode 16A comes into Schottky contact with the 2DEG layer A generated in the electron transit layer 12 via the etching sacrificial layer 14 and the electron supply layer 13. In the anode electrode 16A, the formation region of the anode electrode 16A in the etching sacrificial layer 14 and the electron supply layer 13 is removed by recess etching, and the 2DEG existing under the field plate layer 15a is brought into Schottky contact from the side. Also good.

  The anode electrode 16A rides on the field plate layer 15a to form at least one step, and extends so as to protrude toward the cathode electrode 16C. In the first embodiment, the anode electrode 16A is provided in contact with part of the side surface and the upper surface of the field plate layer 15a. It should be noted that another semiconductor film or dielectric film may be interposed between the anode electrode 16A and the field plate layer 15a so as not to contact each other. Further, in the first embodiment, the field plate portion is provided in a shape having multi-steps, for example, two steps, in the anode electrode 16A.

  The cathode electrode 16C as the second electrode has, for example, a Ti / Al laminated structure in which the lower electrode layer is a Ti layer and the upper electrode layer is an Al layer. Thus, the cathode electrode 16C is in ohmic contact with the 2DEG layer A generated in the electron transit layer 12 via the etching sacrificial layer 14 and the electron supply layer 13.

The insulating film 17 mainly protects the surface of the field plate layer 15a, the anode electrode 16A, the cathode electrode 16C, and the etching sacrificial layer 14. The insulating film 17 is made of, for example, silicon oxide (SiO ₂ ), but may be made of other materials, specifically, silicon nitride (SiN _x ), aluminum oxide (Al ₂ O ₃ : alumina), or the like. Alternatively, a plurality of types of materials may be appropriately combined or sequentially stacked. The SBD 1 according to the first embodiment is configured as described above.

(Nitride semiconductor device manufacturing method)
Next, a method for manufacturing SBD 1 as the nitride semiconductor device in the first embodiment will be described. 2, FIG. 3, FIG. 4 and FIG. 5 are schematic cross-sectional views showing a method for manufacturing a nitride semiconductor device according to the first embodiment.

In the method of manufacturing SBD 1 as the nitride semiconductor device according to the first embodiment, first, as shown in FIG. 2, for example, a group III is placed in a MOCVD reactor (not shown) on which substrate 11 is placed. Trimethylgallium (TMGa) as a gas, ammonia (NH ₃ ) as a group V gas, and hydrogen (H ₂ ) and nitrogen (N ₂ ) as carrier gases are supplied. As a result, GaN is grown on the substrate 11 to form the electron transit layer 12 composed of the u-GaN layer.

Thereafter, the supply of TMGa to the MOCVD reactor is stopped, and in that state, for example, trimethylaluminum (TMAl) as a group III gas is supplied to the MOCVD reactor. As a result, an Al _x Ga _1-x N layer made of an AlGaN modified layer having a relatively high Al composition ratio x is grown on the electron transit layer 12. Subsequently, the supply of TMAl to the MOCVD reactor is stopped, and TMGa is supplied in that state. Thereby, an Al _x Ga _1-x N layer made of an AlGaN metamorphic layer having a relatively low Al composition ratio x is grown. By alternately repeating these crystal growths, an electron supply layer 13 made of an AlGaN superlattice layer having a pseudo mixed crystal structure is formed on the electron transit layer 12. After that, the etching sacrificial layer 14 is formed on the electron supply layer 13 by supplying TMGa and TMAl into the MOCVD reactor.

Next, the semiconductor layer 15 is formed by growing GaN, for example, on the etching sacrificial layer 14. Note that an impurity such as C or Mg or a p-type impurity may be doped when the semiconductor layer 15 is grown. Here, in the growth of the semiconductor layer 15, TMGa and NH ₃ are introduced at a predetermined flow rate (for example, 58 μmol / min, 12 L / min, respectively), for example, by MOCVD. At the same time, TMAl is allowed to flow at a constant flow rate of 0.1% or less of the NH ₃ flow rate, and the semiconductor layer is epitaxially grown at a growth temperature of, for example, 1050 ° C. Since field plate layer 15a is formed from a part of semiconductor layer 15, the film thickness of semiconductor layer 15 is the same as the film thickness of field plate layer 15a described above. In the first embodiment, for example, 30 nm. In addition, as described above, there may be a case where the protruding portion 15A that is a protruding defect is generated on the surface when the semiconductor layer 15 is grown.

  Subsequently, as shown in FIG. 3, a resist pattern 18 corresponding to a predetermined shape of the field plate layer 15 a is selectively formed on the semiconductor layer 15. Thereafter, using the resist pattern 18 as an etching mask, the semiconductor layer 15 is etched to the etching sacrificial layer 14 using an etching gas containing chlorine (Cl) and oxygen (O), for example. As a result, as shown in FIG. 4, the semiconductor layer 15 other than the desired region is removed by etching to form the field plate layer 15a.

  Here, the etching conditions of the semiconductor layer 15 are 50 nm or more, preferably 50 nm or more and 300 nm or less, more preferably 100 nm or more, and further preferably 200 nm or less with respect to the designed film thickness of the semiconductor layer 15. The conditions are such that the semiconductor layer 15 having a thickness obtained by adding can be selectively etched. That is, in the first embodiment, the semiconductor layer 15 having a thickness of (d + 50) nm or more, preferably (d + 50) nm or more and (d + 300) nm or less with respect to the designed film thickness d (nm) of the semiconductor layer 15. The etching conditions are assumed to be etched. Specifically, when the designed film thickness d of the semiconductor layer 15 is, for example, 30 nm, the etching condition is a condition assuming that the semiconductor layer 15 having a film thickness of, for example, 80 nm or more and 330 nm or less is etched. Thereby, the semiconductor layer 15 in the region where the resist pattern 18 is not formed can be almost removed by etching together with the protrusions 15A on the surface, and most regions other than the region where the field plate layer 15a is formed, preferably The etching sacrificial layer 14 is exposed in the entire region other than the formation region of the field plate layer 15a. When the etching sacrificial layer 14 is not provided, the electron supply layer 13 is exposed in almost all regions other than the formation region of the field plate layer 15a, preferably in the entire region other than the formation region of the field plate layer 15a.

  Further, in the region to be removed by etching, the region where the protruding portion 15A is generated (generated region) needs to be etched to have a thicker film thickness than other regions, so that it takes time to remove the etching. For this reason, in the region where the protruding portion 15A is not generated (non-occurrence region), the etching sacrificial layer 14 below is over-etched according to the etching selectivity. Specifically, the etching selection ratio of the semiconductor layer 15 to the etching sacrificial layer 14 is about 25 times, for example. In this case, the etching sacrificial layer 14 in the non-occurrence region of the protrusion 15A is added in the setting of the etching condition when the semiconductor layer 15 in the generation region of the protrusion 15A is removed by etching and the etching sacrificial layer 14 is exposed. The overetching is about 2 to 12 nm which is about 1/25 of 50 to 300 nm. As a result, a protrusion 14A reflecting the shape of the protrusion 15A is formed on the surface of the etching sacrificial layer 14 in the region where the protrusion 15A occurs. The height h from the surface of the etching sacrificial layer 14 other than the region where the protrusion 14A is formed to the apex of the protrusion 14A varies depending on the etching selectivity between the etching sacrificial layer 14 and the semiconductor layer 15. However, it is preferably less than 12 nm, more preferably 4 nm or less. If the etching sacrificial layer 14 is not provided, the outermost surface of the electron supply layer 13 is over-etched in the same manner as described above.

  Thereafter, as shown in FIG. 5, the resist pattern 18 is removed. At this time, the protruding portions 15A remain at a predetermined density (existence probability) on the surface of the field plate layer 15a.

  On the other hand, the etching conditions of the semiconductor layer 15 according to the conventional technique are conditions for selectively etching the semiconductor layer 15 with a film thickness of, for example, about 120% with respect to the designed film thickness d of the semiconductor layer 15. FIG. 6 is a schematic cross-sectional view showing a state after selective etching corresponding to FIG. 4 in the case of this etching condition. That is, in the prior art, the etching conditions are assumed to etch the semiconductor layer 15 having a thickness of about 1.2 × d (nm) with respect to the designed thickness d (nm) of the semiconductor layer 15. . Specifically, when the thickness of the semiconductor layer 15 is 30 nm, the etching conditions according to the prior art are the conditions assuming that the semiconductor layer 15 having a thickness of about 36 nm is etched. In this case, as shown in FIG. 6, a part of the semiconductor layer 15 in which the shape of the protruding defect is substantially reflected remains on the surface of the etching sacrificial layer 14. If the etching sacrificial layer 14 is not provided, a part of the semiconductor layer 15 remains on the electron supply layer 13. Therefore, the 2DEG concentration in the lower layer of the remaining semiconductor layer 15 is reduced to be lower than the 2DEG concentration in the region where the etching sacrificial layer 14 is exposed by etching. In this case, as described above, electric field concentration occurs at the bottom end of the remaining semiconductor layer 15, so that the breakdown voltage is reduced in the nitride semiconductor device as the final product, and the manufacturing yield is reduced.

  Now, in the manufacturing method according to the first embodiment, after the selective etching of the semiconductor layer 15 shown in FIG. 5, for example, the electron beam evaporation method or the sputtering method and the lift-off method are appropriately performed, as shown in FIG. Then, the cathode electrode 16 </ b> C is selectively formed on the etching sacrificial layer 14. Next, the insulating film 17 is formed by using, for example, a plasma enhanced chemical vapor deposition (PECVD) method, a photolithography technique, and etching. Next, an anode electrode having a field plate structure is selectively formed on the etching sacrificial layer 14, the field plate layer 15a, and the insulating film 17 by performing, for example, an electron beam evaporation method or a sputtering method and a lift-off method. 16A is formed. Through the above steps, the SBD 1 according to the first embodiment is manufactured.

  The inventor conducted a withstand voltage test on the nitride semiconductor device such as SBD1 manufactured as described above with a reverse applied voltage of 600 V, and calculated the manufacturing yield of the nitride semiconductor device that passed the test. FIG. 7 is a graph showing the result of the yield. Specifically, FIG. 7 shows a case where the etching conditions for the semiconductor layer 15 are the conditions for etching the semiconductor layer 15 having a thickness 0 to 300 nm larger than the designed film thickness d of the semiconductor layer 15 (overetching amount). It is a graph which shows the manufacture yield of the nitride semiconductor device as a final product.

  From FIG. 7, in the case of the condition according to the prior art in which the overetching amount is 0 nm, that is, the etching condition is the condition for etching the semiconductor layer 15 as designed, the yield is about 30%, It can be seen that the yield improves as the amount is gradually increased from 25 nm to 300 nm. Moreover, it turns out that a yield will be 75% or more by making over-etching amount into 50 nm or more. Furthermore, when the overetching amount is 200 nm and 300 nm, the yield increases to 94% of 90% or more, while the increase in yield accompanying the increase in the overetching amount is slightly increased. From these, it can be seen that a sufficient production yield can be ensured by setting the over-etching amount to 50 nm or more and 300 nm or less as in the etching conditions according to the first embodiment.

  According to the first embodiment of the present invention described above, in the nitride semiconductor device in which the field plate layer 15a for electric field relaxation is provided on the etching sacrificial layer 14 or the electron supply layer 13, the semiconductor layer 15 Is etched away except for the region where the field plate layer 15a is formed, and the etching conditions are set such that the semiconductor layer 15 having a thickness of 50 nm or more larger than the thickness of the field plate layer 15a, that is, the thickness of the semiconductor layer 15. The conditions are such that etching can be performed. As a result, in the case of the etching condition of about the designed film thickness in the conventional etching condition, a part of the semiconductor layer 15 or the protruding portion 15A remains in the region other than the formation region of the field plate layer 15a, and a nitride semiconductor such as SBD Whereas the breakdown voltage of the device decreases, the surface of the etching sacrificial layer 14 and the surface of the electron supply layer 13 in the region other than the region where the field plate layer 15a is formed are not provided. Most preferably, the entire surface can be exposed. As a result, it is possible to suppress the protrusions 15A due to the protrusion defects generated on the surface of the semiconductor layer 15, so that electric field concentration occurs when a voltage is applied to the nitride semiconductor device such as SBD1. It becomes possible to suppress, and a decrease in breakdown voltage can be suppressed.

(Embodiment 2)
Next, a HEMT field effect transistor as a nitride semiconductor device according to the second embodiment of the present invention will be described. FIG. 8 is a schematic cross-sectional view showing HEMT 2 as the nitride semiconductor device according to the second embodiment.

  As shown in FIG. 8, the HEMT 2 according to the second embodiment has a structure including the base 11, the electron transit layer 12, the electron supply layer 13, and the etching sacrificial layer 14 in the first embodiment. Then, on the etching sacrificial layer 14, a field plate layer 15b, a source electrode 21S, a gate electrode 21G, a drain electrode 21D, and an insulating film 22 which are separated from each other are provided.

  Here, in the second embodiment, the thickness of the field plate layer 15b is preferably 20 nm or more and 200 nm or less, preferably 20 nm or more and 100 nm or less, more preferably, for the same reason as in the first embodiment. It is 20 nm or more and 50 nm or less. Similarly to the first embodiment, the field plate layer 15b is formed by selectively etching the semiconductor layer 15 using the etching sacrificial layer 14 as an etching stop layer to be over-etched. Since the etching conditions in this selective etching are the same as those in the first embodiment, description thereof is omitted.

In the second embodiment, the 2DEG concentration inside the electron transit layer 12 is reduced by the field plate layer 15b. That is, the 2DEG layer a having a low 2DEG concentration is generated in the lower region of the field plate layer 15b. Here, from the viewpoint of increasing the breakdown voltage of the HEMT ² , the 2DEG concentration of the 2DEG layer a is preferably 7 × 10 ¹² cm ⁻² or less. From the viewpoint of reducing the on-resistance of the HEMT 2, the 2DEG concentration of the 2DEG layer A having a relatively high 2DEG concentration is preferably higher than 7 × 10 ¹² cm ⁻² . As described above, the 2DEG concentration is set to be less than 3 × 10 ¹³ cm ⁻² by adjusting the average Al composition ratio X and the number of stacked layers in the electron supply layer 13.

  In addition, the drain electrode 21D as the second electrode and the source electrode 21S as the third electrode are provided on the etching sacrificial layer 14, and are composed of, for example, a laminated structure of Ti / Al. As a result, the drain electrode 21D and the source electrode 21S are in ohmic contact with the 2DEG layer A via the etching sacrificial layer 14 and the electron supply layer 13.

  Further, the gate electrode 21G as the first electrode is disposed between the drain electrode 21D and the source electrode 21S, and is provided on the field plate layer 15b and the insulating film 22. The gate electrode 21G is formed of, for example, a Ni / Au laminated structure. As a result, the gate electrode 21G is in Schottky contact with the 2DEG layer A in the electron transit layer 12 via the etching sacrificial layer 14 and the electron supply layer 13. In addition, the gate electrode 21G is provided to extend in such a manner that the field plate portion protrudes in a stepped manner in multiple steps, for example, toward both sides of the source electrode 21S and the drain electrode 21D. In the second embodiment, the gate electrode 21G is formed so as to be in contact with the etching sacrificial layer 14, but the field plate layer 15b is interposed between the etching sacrificial layer 14 and the gate electrode 21G. It is also possible to configure.

The insulating film 22 is made of, for example, SiO ₂ , but may be made of other materials, specifically, for example, SiN _x , Al ₂ O _3, or the like. It may be configured by stacking. The insulating film 22 mainly protects the field plate layer 15b, the gate electrode 21G, the drain electrode 21D, the source electrode 21S, and the surface of the etching sacrificial layer 14. As described above, the HEMT 2 according to the second embodiment is configured.

  According to the second embodiment, the etching conditions in the selective etching of the semiconductor layer 15 for forming the field plate layer 15b are the same as those in the first embodiment, so that the region other than the formation region of the field plate layer 15b is formed. Since the remaining part of the semiconductor layer 15 or the protrusions 15A in the portion can be suppressed, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
Next, a method for manufacturing a nitride semiconductor device according to the third embodiment of the present invention will be described. 9 and 10 are schematic cross-sectional views of a semiconductor laminated substrate for illustrating the method for manufacturing a nitride semiconductor device according to the third embodiment.

  As shown in FIG. 9, in the method of manufacturing a nitride semiconductor device according to the third embodiment, first, in the same manner as in the first embodiment, for example, an electron composed of a u-GaN layer on the substrate 11 by MOCVD. The traveling layer 12 is grown. Thereafter, an electron supply layer 13 made of an AlGaN superlattice layer, an etching sacrificial layer 14 made of an AlGaN layer, and a semiconductor layer 15 made of a GaN layer are sequentially grown on the electron transit layer 12 by, for example, MOCVD. Thereby, the semiconductor laminated substrate 10 is formed. Further, projecting portions 15A that are projecting defects are formed on the surface of the semiconductor layer 15 at a predetermined density. FIG. 9 shows a portion where the protruding portion 15A is formed.

  Next, as shown in FIG. 10, the semiconductor layer 15 is etched back until the thickness of the semiconductor layer 15 is the same as that of the first embodiment, specifically, for example, 30 nm. Remove. In consideration of removing the protrusions 15A having a height of about 50 to 300 nm, this etch back step is preferably performed by an isotropic etching method such as a wet etching method. It is also possible to carry out by an etching method. Here, as described above, the height H of the protruding defect on the semiconductor layer 15 is about 50 to 300 nm. For this reason, considering that no protruding defects remain due to etch back, the thickness of the semiconductor layer 15 is larger than the thickness of the semiconductor layer 15 in the first embodiment, and is 0.5 μm (500 nm) or more. Is desirable. As a result, on the surface of the semiconductor layer 15, the protruding portion 15A is almost removed, and the planarized semiconductor laminated substrate 10 is formed. Thereafter, the field layer layers 15a and 15b are formed on the semiconductor laminated substrate 10 by selectively etching the semiconductor layer 15 by a conventionally known photoresist process and etching process. At this time, since the protruding portion 15A is not formed on the surface of the semiconductor layer 15, the protruding portion 14A is also formed on the surface of the lower etching sacrificial layer 14 in the region where the semiconductor layer 15 is removed by etching. Even when the etching sacrificial layer 14 is not provided, no protruding portion remains on the electron supply layer 13.

  In the subsequent processes, as in the first embodiment, the semiconductor multilayer substrate 10 on which the field plate layer 15a is formed undergoes an electrode manufacturing process and an insulating film manufacturing process. As a result, the SBD 1 having the field plate layer 15a shown in FIG. 1 and having no protrusions 15A and 14A is manufactured. On the other hand, after the semiconductor layer 15 is etched into a predetermined shape with respect to the semiconductor laminated substrate 10 to form the field plate layer 15b, the manufacturing process of electrodes and insulating films is performed as in the second embodiment. As a result, the HEMT 2 shown in FIG. 8 having the field plate layer 15b and not formed with the projecting portions 15A and 14A is manufactured.

  In the third embodiment, after the semiconductor layer 15 is grown thickly, etching back is performed so as to remove the protruding portion 15A which is a protruding defect, whereby the finally formed semiconductor layer 15 is formed. The surface can be planarized. Therefore, it is possible to suppress a part of the semiconductor layer 15 or the protruding portion 15A due to the above-described protruding defects from remaining on the surface of the etching sacrificial layer 14 or the electron supply layer 13, so that the nitride semiconductor as the final product It is possible to suppress a decrease in breakdown voltage in the apparatus, and the same effect as in the first and second embodiments can be obtained.

(Embodiment 4)
Next, a method for manufacturing a nitride semiconductor device according to the fourth embodiment of the present invention will be described. 11 and 12 are schematic cross-sectional views of a semiconductor laminated substrate for illustrating the method for manufacturing a nitride semiconductor device according to the fourth embodiment.

  That is, as shown in FIG. 11, in the fourth embodiment, the electron transit layer 12 and the electron supply layer 13 are sequentially formed on the substrate 11 in the same manner as in the first and second embodiments.

Next, a film made of a material that does not form a semiconductor layer 32 described later, such as a SiO ₂ film, is formed on the electron supply layer 13 by, for example, plasma enhanced chemical vapor deposition (PCVD). An SiN _x film may be formed instead of the SiO ₂ film. Then, an opening in which the planar shape along the surface of the SiO ₂ film becomes a predetermined shape of the field plate layers 15a and 15b is formed in the formed SiO ₂ film by a photolithography process and an etching process. As a result, the selective growth mask layer 31 having openings in the shape of the field plate layers 15 a and 15 b is formed on the etching sacrificial layer 14 or the electron supply layer 13.

  Next, the semiconductor layer 32 made of, for example, GaN is selectively regrown in the opening of the selective growth mask layer 31 by, for example, MOCVD. The semiconductor layer 32 is grown on the opening region where the electron supply layer 13 where the selective growth mask layer 31 is not formed is exposed. At this time, protrusions 32A are formed on the surface of the semiconductor layer 32 with a predetermined density (existence probability). Thereby, the semiconductor laminated substrate 30 is formed. FIG. 11 shows a portion where the protruding portion 32 </ b> A is formed in the semiconductor laminated substrate 30.

  Thereafter, as shown in FIG. 12, the selective growth mask layer 31 is removed by a conventionally known method, whereby a field plate layer made of a semiconductor layer 32 having a predetermined shape is formed on the electron supply layer 13. When the protruding portion 32A is formed on the semiconductor layer 32, the protruding portion 32A remains.

  In the subsequent steps, an electrode and an insulating film are formed on the semiconductor laminated substrate 30 in the same manner as in the first embodiment, thereby having a field plate layer similar to the SBD 1 shown in FIG. 14 and the protrusion 14A are not provided. On the other hand, an electrode and an insulating film are formed on the semiconductor multilayer substrate 30 in the same manner as in the second embodiment, thereby having a field plate layer similar to the HEMT 2 shown in FIG. A HEMT in which 14A is not formed is manufactured.

  According to the fourth embodiment, there is a possibility that the projecting portion 32A composed of at least part of the projecting defect is formed only on the surface of the semiconductor layer 32 serving as the field plate layer. No protruding portion due to the protruding defect is formed on the surface of the electron supply layer 13 other than the region where the semiconductor layer 32 is formed. Thereby, the effect similar to Embodiment 1-3 can be acquired.

(Embodiment 5)
Next, a nitride semiconductor device and a manufacturing method thereof according to Embodiment 5 of the present invention will be described. In the fifth embodiment, unlike the configuration of the first to third embodiments in which the etching sacrificial layer 14 is provided on the electron supply layer 13, the Al composition ratio x in the region on the surface side of the electron supply layer 13 is set as the electron supply. The layer 13 is made of Al _x Ga _1-x N (0.4 ≦ x) which is larger than the average Al composition ratio X of the layer 13 and preferably 40% or more. The electron supply layer 13 is not limited to the superlattice structure, and various structures are adopted according to various designs in the nitride semiconductor device. The region on the surface side of the electron supply layer 13 functions as an etching sacrificial layer for preventing the electron supply layer 13 from being over-etched more than a desired thickness when etching the semiconductor layer 15 or the like formed further thereon. .

  Here, according to the knowledge of the present inventor, the etching selectivity of the GaN layer to the AlGaN layer monotonously increases depending on the Al composition ratio of the AlGaN layer. That is, the etching selectivity of the nitride-based compound semiconductor not containing Al with respect to the Al-containing nitride-based compound semiconductor monotonously increases depending on the Al composition ratio in the nitride-based compound semiconductor containing Al. In order to improve the controllability of etching when the nitride-based compound semiconductor layer containing Al is used as an etching sacrificial layer of the nitride-based compound semiconductor layer not containing Al, from experiments conducted by the present inventors. It is desirable that the selection ratio is 25 times or more. Therefore, in order to use this electron supply layer 13 as an etching sacrificial layer of the semiconductor layer 15 formed thereon, the Al composition ratio of the uppermost surface of the electron supply layer 13 is preferably set to 0.4 or more. However, the Al composition ratio is not necessarily limited depending on the etching conditions. In order to prevent deterioration of contact with the electrode formed on the electron supply layer 13, the Al composition ratio of the uppermost surface of the electron supply layer 134 is more preferably 0.9 or less.

  Further, if the region from the uppermost surface in which the average Al composition ratio of the electron supply layer 13 is 0.4 or more and 0.9 or less is less than 1 nm along the film thickness direction, the etching of the semiconductor layer 15 formed in the upper layer is performed. It becomes difficult to use as a sacrificial layer. Therefore, in the range of at least 1 nm, preferably 2 nm along the film thickness direction from the interface between the electron supply layer 13 and the semiconductor layer 15 constituting the field plate layers 15 a and 15 b toward the electron supply layer 13, the Al composition The ratio is preferably 0.4 or more and 0.9 or less. On the other hand, the average Al composition ratio X of the entire electron supply layer 13 is preferably less than 0.4, which is smaller than the Al composition ratio x of the outermost surface, specifically, for example, 0.25 (X = 0.25). ).

The same applies to the case where the electron supply layer 13 has a superlattice structure, and the Al composition ratio in the electron supply layer 13 is relatively high compared to other portions, and is preferably 0.4 or more (0. The film thickness of the uppermost Al _x Ga _1-x N layer (4 ≦ x) is 1 nm or more, more preferably 2 nm or more. Further, since this Al _x Ga _1-x N layer is a part of the electron supply layer 13 of the AlGaN superlattice layer, the film thickness is preferably 10 nm or less.

  According to the fifth embodiment, the Al composition ratio of the electron supply layer 13 in the range of at least 1 nm along the film thickness direction from the uppermost surface of the electron supply layer 13 is 0.4 or more and 0.9 or less. Thus, the electron supply layer 13 can be used as an etching sacrificial layer in which a desired etching selectivity is ensured with respect to the semiconductor layer 15 formed thereon. Thereby, a desired etching selection ratio can be ensured without lowering the etching rate, and the semiconductor layer 15 can be etched with good controllability without causing the surface of the electron supply layer 13 containing Al to oxidize. Further, the Al composition ratio in the range of at least 1 nm, preferably 2 nm from the uppermost surface of the electron supply layer 13 is set to 0.4 or more and 0.9 or less, and the average Al composition ratio X of the entire electron supply layer 13 is less than 0.4. Thus, the 2DEG concentration at the interface between the electron transit layer 12 and the electron supply layer 13 can be adjusted.

  Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible. For example, the numerical values given in the above embodiment are merely examples, and different numerical values may be used as necessary. Further, the present invention is not limited to the above-described embodiment. What was comprised combining each component mentioned above suitably is also contained in this invention. Further effects and modifications can be easily derived by those skilled in the art.

For example, in the above-described embodiment, the electron supply layer is an AlGaN superlattice layer, but in addition to the AlGaN superlattice layer, a plurality of In _u Al _v Ga _{1 -uv} N layers (0 ≦ u <1, 0 It is also possible to employ an InAlGaN superlattice layer in which <v ≦ 1, 0 <u + v <1) is laminated to form a superlattice layer.

  In addition to those described in the above embodiment, various pseudo-mixed crystal structures belonging to the scope of the present invention are adopted for the electron supply layer 13 in accordance with the structure design based on desired characteristics in the semiconductor device. Is possible.

The electron supply layer 13 includes two different types of Al _x Ga _1-x N layers that are different from each other, and an Al _x1 Ga _1-x1 N layer having a maximum Al composition ratio x1 with a film thickness d1 and a minimum Al composition ratio with a film thickness d2. It is also possible to form a pair of _x2 Al _x2 Ga _1-x2 N layers and to laminate them a plurality of times.

  The anode electrode of the diode and the lower electrode layer of the gate electrode of the transistor are electrodes that are in Schottky contact with the electron supply layer. Therefore, besides nickel (Ni) and titanium (Ti) described above, for example, platinum (Pt), palladium (Pd), tungsten (W), gold (Au), silver (Ag), copper (Cu), tantalum ( Ta), a metal film containing at least one of aluminum (Al), or a metal film made of an alloy containing at least one of Ti, Ni, Pt, Pd, W, Au, Ag, Cu, Ta, and Al Of these, various metal materials satisfying the above conditions, such as a metal film containing at least one or a metal film made of a nitride alloy containing at least one of Ti, W, and Ta may be used. good.

  The upper electrode layer of the anode electrode of the diode and the gate electrode of the transistor is made of a metal having a work function smaller than that of the lower electrode layer, and various materials may be used as long as the metal material satisfies this condition.

  In addition, the cathode electrode of the diode and the source electrode and drain electrode of the transistor are electrodes that are in ohmic contact with the electron supply layer or in contact with a sufficiently small contact resistance. However, the present invention is not limited thereto. For example, a metal film containing at least one of Ti, Al, silicon (Si), lead (Pb), chromium (Cr), In, Ta, Ti, Al, Si, Metal film made of an alloy containing at least one of Pb, Cr, In, Ta, or metal film made of a silicide alloy containing at least one of Ti, Al, Si, Ta, or Ti, W, Ta Any metal material satisfying the above conditions, such as a metal film including at least one of metal films made of a nitride alloy including at least one of them, may be used.

  In the above-described embodiments, SBD, HEMT, MOSFET, and MISFET are given as examples of the semiconductor device according to the present invention. However, the present invention is not limited to this. That is, the present invention can be applied to various semiconductor devices such as MESFET (Metal Semiconductor FET). When the present invention is applied to these FETs, an insulating film such as an oxide film can be provided between the gate electrode and the field plate layer.

  In the above-described embodiment, the electrodes are formed on the surface of the electron supply layer and the etching sacrificial layer. However, the present invention is not limited thereto, and the electron transit layer, the electron supply layer, the etching sacrificial layer, In addition, an electrode can be provided on at least one of the semiconductor laminates including the semiconductor layer and the field plate layer and other layers as necessary. That is, an electrode may be provided on another layer constituting the semiconductor stacked body. Specifically, an anode electrode, a cathode electrode, a gate electrode, a drain electrode, or a source electrode is formed on the surface of the electron supply layer via a nitride-based semiconductor layer such as an insulating layer or a field plate layer, or a laminated film thereof. It is also possible to provide. Further, a part of the electrode formation region of the electron supply layer is removed by etching until reaching the electron transit layer to form a recess portion, and the surface of the recess portion, or the surface of the recess portion via a predetermined film, the anode electrode It is also possible to provide a cathode electrode, a gate electrode, a drain electrode, or a source electrode.

In Embodiment 4 described above, the etching sacrificial layer is not provided on the electron supply layer 13, but if necessary, the average Al composition ratio X of the electron supply layer 13 is larger on the electron supply layer 13. It is also possible to provide an etching sacrificial layer 14 made of Al _Y Ga _1-Y N, preferably having an Al composition ratio Y of 40% or more.

1 Schottky barrier diode (SBD)
2 Field Effect Transistor (HEMT)
DESCRIPTION OF SYMBOLS 10,30 Semiconductor laminated substrate 11 Base | substrate 12 Electron transit layer 13 Electron supply layer 14 Etching sacrificial layer 14A, 15A, 32A Projecting part 15, 32 Semiconductor layer 15a, 15b Field plate layer 16A Anode electrode 16C Cathode electrode 17, 22 Insulating film 18 resist pattern 21D drain electrode 21G gate electrode 21S source electrode 31 selective growth mask layer

Claims (15)

A substrate;
A first semiconductor layer made of a nitride semiconductor provided on the substrate, and a second semiconductor made of a nitride semiconductor provided on the upper layer of the first semiconductor layer and having an average wider band gap than the first semiconductor layer And a semiconductor stacked body including a third semiconductor layer made of a nitride semiconductor that is selectively provided in a predetermined shape on the upper layer of the second semiconductor layer and has an average band gap narrower than that of the second semiconductor layer;
A first electrode provided on at least a part of the semiconductor layers constituting the semiconductor laminate;
A second electrode provided apart from the first electrode on at least a part of the semiconductor layers constituting the semiconductor laminate;
In a method for manufacturing a nitride semiconductor device comprising:
Etching that can etch the third semiconductor layer having a thickness obtained by adding a value of 50 nm or more to the design thickness of the third semiconductor layer as an etching condition for forming the third semiconductor layer into a predetermined shape by an etching method. A method for manufacturing a nitride semiconductor device, characterized in that:   Etching conditions for etching the third semiconductor layer having a thickness obtained by adding a value of 50 nm to 300 nm to the design thickness of the third semiconductor layer when the third semiconductor layer is formed into a predetermined shape by an etching method. The method for manufacturing a nitride semiconductor device according to claim 1, wherein:   When the third semiconductor layer is formed into a predetermined shape by an etching method, the surface of the second semiconductor layer is formed in a region other than the region where the third semiconductor layer is selectively provided on the second semiconductor layer. The method for manufacturing a nitride semiconductor device according to claim 1, wherein etching is performed until the surface is exposed to the entire surface.   A fourth semiconductor layer made of a nitride semiconductor having an Al composition ratio higher than an average Al composition ratio of the second semiconductor layer between the second semiconductor layer and the third semiconductor layer; The method for manufacturing a nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is manufactured.   When the third semiconductor layer is formed into a predetermined shape by an etching method, the surface of the fourth semiconductor layer is formed in a region other than the region where the third semiconductor layer is selectively provided on the second semiconductor layer. The method of manufacturing a nitride semiconductor device according to claim 4, wherein etching is performed until the entire surface is exposed.   The said 2nd semiconductor layer has a superlattice structure which consists of a multiple layer nitride semiconductor layer which laminated | stacked the nitride semiconductor layer which consists of at least 2 different Al composition ratio in multiple times. The manufacturing method of the nitride semiconductor device of any one of Claims 1.   The method for manufacturing a nitride semiconductor device according to claim 1, wherein an Al composition ratio in a region on at least a surface side of the second semiconductor layer is 40% or more.   8. The etching condition according to claim 1, wherein the etching condition includes an etching condition in which an etching selection ratio of the third semiconductor layer to a semiconductor layer below the third semiconductor layer is 25 times or more. A method for manufacturing a nitride semiconductor device according to claim 1. A substrate;
A first semiconductor layer made of a nitride semiconductor provided on the substrate, and a second semiconductor made of a nitride semiconductor provided on the upper layer of the first semiconductor layer and having an average wider band gap than the first semiconductor layer And a semiconductor stacked body including a third semiconductor layer made of a nitride semiconductor that is selectively provided in a predetermined shape on the upper layer of the second semiconductor layer and has an average band gap narrower than that of the second semiconductor layer;
A first electrode provided on at least a part of the semiconductor layers constituting the semiconductor laminate;
A second electrode provided apart from the first electrode on at least a part of the semiconductor layers constituting the semiconductor laminate;
In a method for manufacturing a nitride semiconductor device comprising:
A method for manufacturing a nitride semiconductor device, comprising: an etch-back step of planarizing a surface of the third semiconductor layer before forming the third semiconductor layer into a predetermined shape by an etching method. A substrate;
A first semiconductor layer made of a nitride semiconductor provided on the substrate, and a second semiconductor made of a nitride semiconductor provided on the upper layer of the first semiconductor layer and having an average wider band gap than the first semiconductor layer And a semiconductor stacked body including a third semiconductor layer made of a nitride semiconductor that is selectively provided in a predetermined shape on the upper layer of the second semiconductor layer and has an average band gap narrower than that of the second semiconductor layer;
A first electrode provided on at least a part of the semiconductor layers constituting the semiconductor laminate;
A second electrode provided apart from the first electrode on at least a part of the semiconductor layers constituting the semiconductor laminate;
In a method for manufacturing a nitride semiconductor device comprising:
Forming a selective growth mask layer having the opening of the predetermined shape on the second semiconductor layer;
The third semiconductor layer is formed in the predetermined shape by growing the third semiconductor layer inside the opening and then removing the selective growth mask layer. Method. A substrate;
A first semiconductor layer made of a nitride semiconductor provided on the substrate, and a second semiconductor made of a nitride semiconductor provided on the upper layer of the first semiconductor layer and having an average wider band gap than the first semiconductor layer And a semiconductor stacked body including a third semiconductor layer that is selectively provided on the second semiconductor layer and has a band gap that is narrower on average than the second semiconductor layer.
A first electrode provided on at least a part of the semiconductor layers constituting the semiconductor laminate;
A second electrode provided apart from the first electrode on at least a part of the semiconductor layers constituting the semiconductor laminate;
In a nitride semiconductor device comprising:
A nitride semiconductor device, wherein protrusions of 12 nm or more exist on the surface of the third semiconductor layer, and protrusions of less than 12 nm exist on the surface of the second semiconductor layer. A substrate;
A first semiconductor layer made of a nitride semiconductor provided on the substrate, and a second semiconductor made of a nitride semiconductor provided on the upper layer of the first semiconductor layer and having an average wider band gap than the first semiconductor layer A third semiconductor layer made of a nitride semiconductor which is selectively provided on the second semiconductor layer and has an average band gap narrower than that of the second semiconductor layer; and the second semiconductor layer and the third semiconductor layer A semiconductor multilayer body including a fourth semiconductor layer provided between the semiconductor layer and made of a nitride semiconductor having an Al composition ratio higher than an average Al composition ratio of the second semiconductor layer;
A first electrode provided on at least a part of the semiconductor layers constituting the semiconductor laminate;
A second electrode provided apart from the first electrode on at least a part of the semiconductor layers constituting the semiconductor laminate;
In a nitride semiconductor device comprising:
A nitride semiconductor device, wherein protrusions of 12 nm or more exist on the surface of the third semiconductor layer, and protrusions of less than 12 nm exist on the surface of the fourth semiconductor layer.   The third electrode provided further apart from the first electrode and the second electrode on at least a part of the layers constituting the semiconductor stacked body. Or the nitride semiconductor device of 12. A structure of the nitride semiconductor device according to claim 13,
The field effect transistor, wherein the first electrode is a gate electrode, the second electrode is a drain electrode, and the third electrode is a source electrode. It has the structure of the nitride semiconductor device according to claim 11 or 12,
The diode, wherein the first electrode is an anode electrode and the second electrode is a cathode electrode.

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