JP6642465B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  When manufacturing a semiconductor device (semiconductor device, semiconductor element) using a group III nitride such as gallium nitride (GaN), a technique for forming a group III nitride-based p-type semiconductor by ion implantation is disclosed in Patent Document 1. In the technique disclosed in Patent Document 1, after a through insulating film is formed on a gallium nitride-based n-type semiconductor layer, for example, an ion implantation mask made of an insulating film or a resist is formed, and p-type is implanted into the semiconductor layer by ion implantation. Type impurities are implanted.

JP-A-2006-181580

Incidentally, the ion implantation mask can be formed by the following steps when an insulating film made of silicon oxide (SiO ₂ ) is used.

Step 1: An insulating film made of silicon oxide (SiO ₂ ) is formed on the semiconductor layer.
Step 2: A resist pattern is formed on the insulating film.
Step 3: The insulating film is opened by dry etching or wet etching.

However, when an ion implantation mask is formed using an insulating film made of silicon oxide (SiO ₂ ), the surface of the group III nitride semiconductor layer may be contaminated with silicon (Si) in step 1. there were. In such a case, at the time of ion implantation of the p-type impurity, silicon (Si) in silicon oxide (SiO ₂ ) is implanted into the semiconductor layer together with the p-type impurity, and the conductivity of the semiconductor device is controlled. It could be difficult. Further, in the case where the insulating film made of silicon oxide (SiO ₂ ) is opened by dry etching in step 3, there is a possibility that the surface of the semiconductor layer may be damaged by the dry etching. In step 3, when an insulating film made of silicon oxide (SiO ₂ ) is opened by wet etching using hydrofluoric acid (HF) or the like, a desired opening of the insulating film is formed by isotropy of wet etching. Controlling the size may be difficult. Therefore, when an insulating film made of silicon oxide (SiO ₂ ) is used as a mask for ion implantation, it may be difficult to form a p-type semiconductor region of a desired size in a semiconductor layer.

  When a resist is used as a mask for ion implantation, if the ion implantation is performed at a relatively high temperature such as 500 ° C., the resist may be deformed. Therefore, if a resist is used as a mask for ion implantation, it may be difficult to form a p-type semiconductor region of a desired size in the semiconductor layer.

  Therefore, in the technique of ion-implanting a p-type impurity into a group III nitride-based semiconductor layer using an ion implantation mask, the opening of the ion implantation mask is suppressed while suppressing contamination and damage to the semiconductor layer. There was a need for a technology capable of controlling the size. In addition, in a method of manufacturing a semiconductor device, cost reduction, miniaturization, simplification of manufacturing, and the like have been desired.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following embodiments.

(1) According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method includes: an ion implantation mask forming step of forming an ion implantation mask on a semiconductor layer mainly made of a group III nitride and extending along the first direction; and the ion implantation mask is formed. An ion implantation step of implanting a p-type impurity into the semiconductor layer by ion implantation. The step of forming an ion implantation mask comprises: (a) aluminum oxide (Al ₂ O ₃ ) on the semiconductor layer; A step of sequentially laminating a first layer mainly composed of at least one of aluminum nitride (AlN) and aluminum oxynitride (AlON) and a second layer mainly composed of a metal having alkali resistance; (C) forming a second mask layer by dry-etching the second layer from above the resist pattern; and (d) forming a second mask layer. The position of the end of the first layer in the first direction is the same as the position of the end of the second mask layer or the inside of the position of the end of the second mask layer in the first direction. Forming a first mask layer by wet etching the first layer. According to this embodiment, the first layer is mainly made of at least one of aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and aluminum oxynitride (AlON). The surface can be suppressed from being contaminated by silicon (Si). Further, at the time of dry etching, the first layer functions as a protective layer of the semiconductor layer, so that damage to the semiconductor layer can be suppressed. Further, since the second mask layer is formed by dry etching, the opening of the second mask layer can be controlled to a desired size. Further, since the second mask layer has alkali resistance, it is possible to suppress the shape of the second mask layer from being changed by wet etching. Therefore, a p-type semiconductor region having a desired size can be formed in a semiconductor layer by ion implantation using an ion implantation mask, so that a miniaturized semiconductor device can be manufactured.

(2) In the manufacturing method according to the above aspect, the metal having alkali resistance has a property that an etching rate when immersed in tetramethylammonium hydroxide (TMAH) at 60 ° C. and 22% by mass is less than 5 nm / min. May be. According to this embodiment, the shape of the second mask layer can be suppressed from being changed by wet etching.

(3) In the manufacturing method of the above aspect, the metal having alkali resistance is at least one of titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), chromium (Cr), and manganese (Mn). It may be one. According to this embodiment, the shape of the second mask layer can be suppressed from being changed by wet etching.

(4) In the manufacturing method of the above aspect, in the step (d), a difference between an end position of the first layer and an end position of the second mask layer in the first direction is different. The first mask layer may be formed by wet-etching the first layer so as to have a thickness equal to or less than half the thickness of the second mask layer. According to this embodiment, it is possible to prevent the second mask layer from peeling off from the first mask layer. When the direction of ion implantation is inclined with respect to the direction in which the first mask layer and the second mask layer are stacked, ions are implanted into the semiconductor layer located inside the opening of the second mask layer. Can be suppressed.

(5) In the manufacturing method according to the above aspect, in the step (a), the first layer may be formed on the semiconductor layer to a thickness of 50 nm or more and 500 nm or less. According to this embodiment, since the thickness of the first layer is 50 nm or more, it is possible to further suppress damage to the semiconductor layer due to dry etching. In addition, since the thickness of the first layer is 500 nm or less, it is possible to suppress an increase in time required for formation of the first layer and wet etching of the first layer. In addition, since the thickness of the first layer is 500 nm or less, it is possible to suppress an increase in the difference between the position of the end of the first mask layer and the position of the end of the second mask layer due to wet etching. it can. Therefore, the second mask layer can be prevented from being separated from the first mask layer, and the semiconductor layer positioned inside the opening of the second mask layer when the direction of ion implantation is inclined with respect to the first direction. Can be suppressed from being implanted into the substrate.

(6) In the manufacturing method according to the above aspect, the first layer is formed of aluminum oxide (Al ₂ O ₃ ); after the ion implantation step, the first mask layer and the first mask layer are etched with hydrofluoric acid (HF). A step of removing the second mask layer may be provided. According to this embodiment, the first mask layer and the second mask layer can be removed at once by hydrofluoric acid, so that the manufacturing process of the semiconductor device can be simplified.

  The present invention can be realized in various forms other than the above-described method for manufacturing a semiconductor device. For example, the present invention can be realized as a method for manufacturing an ion implantation mask, a method for manufacturing a p-type semiconductor region, a mask for ion implantation, a p-type semiconductor region, and a semiconductor device.

According to the present invention, the first layer is mainly made of at least one of aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and aluminum oxynitride (AlON). The surface can be suppressed from being contaminated by silicon (Si). Further, at the time of dry etching, the first layer functions as a protective layer of the semiconductor layer, so that damage to the semiconductor layer can be suppressed. Further, since the second mask layer is formed by dry etching, the opening of the second mask layer can be controlled to a desired size. Further, since the second mask layer has alkali resistance, it is possible to suppress the shape of the second mask layer from being changed by wet etching. Therefore, a p-type semiconductor region having a desired size can be formed in a semiconductor layer by ion implantation using an ion implantation mask, so that a miniaturized semiconductor device can be manufactured.

FIG. 2 is a diagram schematically showing a configuration of a semiconductor device manufactured by the manufacturing method of the present invention. 4 is a process chart showing a method for manufacturing a semiconductor device. FIG. 4 is a process chart showing a step of forming a mask for ion implantation. FIG. 4 is a diagram showing a semiconductor device in a manufacturing process in which a first layer is formed. FIG. 5 is a diagram showing a semiconductor device in a manufacturing process in which a second layer is formed. FIG. 4 is a diagram showing a semiconductor device in a manufacturing process in which a resist pattern is formed. FIG. 4 is a diagram showing a semiconductor device in a manufacturing process in which a second mask layer is formed. FIG. 4 is a view showing the semiconductor device in a manufacturing process from which a resist pattern has been removed. FIG. 5 is a diagram illustrating the semiconductor device in a manufacturing process in which a first mask layer is formed. FIG. 4 is a diagram showing a state of an ion implantation step. FIG. 5 is a diagram showing the semiconductor device in a manufacturing process in which an ion implantation mask has been removed. FIG. 5 is a diagram showing a semiconductor device in a manufacturing process in which a p-type semiconductor region is formed. The figure which shows the cross-section SEM image of the mask for ion implantation.

A. Embodiment:
A1. Configuration of semiconductor device:
FIG. 1 is a diagram schematically showing a configuration of a semiconductor device 100 manufactured by the manufacturing method of the present invention. FIG. 1 schematically shows a part of a cross section of a semiconductor device 100 according to the present embodiment. FIG. 1 is a diagram for clearly showing the technical features of the semiconductor device 100, and does not accurately show the dimensions of each part.

  FIG. 1 shows mutually orthogonal XYZ axes for ease of explanation. The XYZ axes in FIG. 1 correspond to the XYZ axes in other figures. In the following description, the + Z-axis direction side is also referred to as “up” or “upper”.

  The semiconductor device 100 is formed using a semiconductor mainly made of a group III nitride. In the present embodiment, the semiconductor device 100 is a GaN-based semiconductor device formed using gallium nitride (GaN). In the present embodiment, the semiconductor device 100 is a vertical trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In the present embodiment, the semiconductor device 100 is used for power control, and is also called a power device.

  The semiconductor device 100 includes a substrate 110, a semiconductor layer 111, a semiconductor layer 113, and a semiconductor layer 114. The semiconductor device 100 further includes a p-type semiconductor region 112 formed by ion implantation of a p-type impurity. The semiconductor device 100 has a trench 122, a recess 124, a step 126, and a termination 129 as a structure formed in these semiconductor layers and semiconductor regions. The semiconductor device 100 further includes an insulating film 130, a gate electrode 142, a source electrode 144, and a drain electrode 148. In the present embodiment, the semiconductor device 100 further includes an insulating film 150 and a wiring electrode 160. FIG. 1 shows a control region C for controlling a current flowing between the source electrode 144 and the drain electrode 148 in addition to these structures.

The substrate 110 is a plate-shaped semiconductor that extends in the first direction (the X-axis direction and the Y-axis direction). In the present embodiment, the substrate 110 is mainly made of gallium nitride (GaN). Note that “mainly composed of gallium nitride (GaN)” means that gallium nitride (GaN) is contained in a molar fraction of 90% or more. In the present embodiment, the substrate 110 is an n-type semiconductor containing silicon (Si) as a donor element. In the present embodiment, the average value of the concentration of silicon (Si) contained in the substrate 110 is about 1 × 10 ¹⁸ cm ⁻³ .

The semiconductor layer 111 is a semiconductor layer located on the substrate 110 (on the + Z axis direction side) and extending along the X axis and the Y axis. In the present embodiment, the semiconductor layer 111 is mainly made of gallium nitride (GaN). In the present embodiment, the semiconductor layer 111 is an n-type semiconductor having n-type characteristics. In the present embodiment, the semiconductor layer 111 contains silicon (Si) as a donor element. In the present embodiment, the average value of the concentration of silicon (Si) included in the semiconductor layer 111 is about 8 × 10 ¹⁵ cm ⁻³ . In the present embodiment, the thickness (length in the Z-axis direction) of the semiconductor layer 111 is a thickness between 5 and 30 μm (micrometer), for example, 10 μm (micrometer). The semiconductor layer 111 is formed, for example, on the substrate 110 by metal organic chemical vapor deposition (MOCVD). The V / III ratio of the source gas forming the semiconductor layer 111 is, for example, 900 or more and 3000 or less. The V / III ratio is the molar ratio of the group V raw material to the group III raw material.

The p-type semiconductor region 112 is a region formed by ion-implanting a part of the semiconductor layer 111 with a p-type impurity. The semiconductor in the p-type semiconductor region 112 has p-type characteristics. In the present embodiment, the p-type semiconductor region 112 is adjacent to the semiconductor layers 111 and 113. The p-type semiconductor region 112 is located apart from a control region C for controlling a current flowing between the source electrode 144 and the drain electrode 148. In the present embodiment, among the plurality of p-type semiconductor regions 112 shown in FIG. 1, the p-type semiconductor region 112 on the −X-axis direction side in FIG. 1 is located in a step 126 described later. In the present embodiment, the p-type semiconductor region 112 is mainly made of gallium nitride (GaN), like the semiconductor layer 111. In the present embodiment, the p-type semiconductor region 112 contains magnesium (Mg) as an acceptor element (p-type impurity). The average concentration of magnesium (Mg) contained in the p-type semiconductor region 112 is, for example, about 1 × 10 ²⁰ cm ⁻³ . The thickness of the p-type semiconductor region 112 in the Z-axis direction is about 0.6 μm (micrometer). A method for forming the p-type semiconductor region 112 will be described later.

The semiconductor layer 113 is a semiconductor layer located on the semiconductor layer 111 and the p-type semiconductor region 112 and extending along the X axis and the Y axis. In the present embodiment, the semiconductor layer 113 is mainly made of gallium nitride (GaN). In the present embodiment, the semiconductor layer 113 is a p-type semiconductor having p-type characteristics. In the present embodiment, the semiconductor layer 113 contains magnesium (Mg) as an acceptor element. In the present embodiment, the average value of the concentration of magnesium (Mg) contained in the semiconductor layer 113 is about 2 × 10 ¹⁸ cm ⁻³ . In the present embodiment, the thickness (length in the Z-axis direction) of the semiconductor layer 113 is a thickness between 0.5 and 1.0 μm (micrometer), for example, 0.7 μm (micrometer). is there. The semiconductor layer 113 is formed by, for example, the MOCVD method on the semiconductor layer 111 on which the p-type semiconductor region 112 is formed. The V / III ratio of the source gas forming the semiconductor layer 113 is, for example, 900 or more and 3000 or less.

The semiconductor layer 114 is a semiconductor layer located on the semiconductor layer 113 and extending along the X axis and the Y axis. In the present embodiment, the semiconductor layer 114 is mainly made of gallium nitride (GaN). In the present embodiment, the semiconductor layer 114 is an n-type semiconductor having n-type characteristics. In the present embodiment, the semiconductor layer 114 contains silicon (Si) as a donor element. In the present embodiment, the average value of the concentration of silicon (Si) included in the semiconductor layer 114 is about 6 × 10 ¹⁸ cm ⁻³ . In the present embodiment, the thickness (length in the Z-axis direction) of the semiconductor layer 114 is a thickness between 0.1 and 0.5 μm (micrometer), for example, 0.2 μm (micrometer). is there. The semiconductor layer 114 is formed, for example, on the semiconductor layer 113 by the MOCVD method. The V / III ratio of the source gas forming the semiconductor layer 114 is, for example, 900 or more and 3000 or less.

  The trench 122 is a groove penetrating from the semiconductor layer 114 to the semiconductor layer 111 through the semiconductor layer 113. The lower surface of trench 122 is located in semiconductor layer 111. In this embodiment, the trench 122 has a structure formed by dry etching of the semiconductor layers 114, 113, and 111.

  The recess 124 is a concave portion that is depressed over the semiconductor layer 113 from above the semiconductor layer 114. In this embodiment, the recess 124 has a structure formed by dry etching of the semiconductor layers 114 and 113.

  The step portion 126 is a portion that penetrates through the semiconductor layer 113 from the upper side of the semiconductor layer 114 and falls into the semiconductor layer 111. In this embodiment, the step portion 126 has a structure formed by dry etching of the semiconductor layers 114, 113, and 111. The terminal part 129 of the semiconductor device 100 is a part adjacent to the step part 126 and constituting the terminal of the semiconductor layers 114, 113, 111. In the present embodiment, the terminal portion 129 has a structure formed by dicing.

The insulating film 130 of the semiconductor device 100 is a film having electrical insulation. In the present embodiment, the insulating film 130 is formed from the inside to the outside of the trench 122. In the present embodiment, the insulating film 130 is mainly made of silicon dioxide (SiO ₂ ).

  The gate electrode 142 is an electrode formed in the trench 122 via the insulating film 130. In the present embodiment, the gate electrode 142 is formed not only inside the trench 122 but also outside the trench 122. In the present embodiment, the gate electrode 142 is mainly made of aluminum (Al). When a voltage is applied to the gate electrode 142, an inversion layer is formed in the p-type semiconductor layer 113, and the inversion layer functions as a channel, so that a conduction path is formed between the source electrode 144 and the drain electrode 148. Is done.

  The source electrode 144 is an electrode formed in the recess 124 and in ohmic contact with the semiconductor layer 114. In this embodiment, the source electrode 144 is an electrode obtained by stacking a layer mainly composed of aluminum (Al) on a layer mainly composed of titanium (Ti) and then performing a heat treatment.

  The drain electrode 148 is an electrode that makes ohmic contact with the surface of the substrate 110 on the −Z axis direction side. In this embodiment, the drain electrode 148 is an electrode obtained by stacking a layer mainly composed of aluminum (Al) on a layer mainly composed of titanium (Ti) and then performing a heat treatment.

  In the present embodiment, the semiconductor device 100 includes a plurality of trench structures in which the insulating film 130 and the gate electrode 142 are formed in the trench 122, and a plurality of recess structures in which the source electrode 144 is formed in the recess 124. In the present embodiment, the trench structure and the recess structure are alternately arranged in the X-axis direction. In this embodiment, the trench structure and the recess structure extend in the Y-axis direction. In the present embodiment, the plurality of gate electrodes 142 are connected in parallel in the plane of the semiconductor device 100. In the present embodiment, the plurality of source electrodes 144 are connected in parallel through the wiring electrode 160.

The insulating film 150 covers the step 126, the insulating film 130, the gate electrode 142, and the source electrode 144. In the present embodiment, the insulating film 150 is mainly made of silicon dioxide (SiO ₂ ).

  The wiring electrode 160 is an electrode formed on the insulating film 150. The wiring electrode 160 has a connection portion penetrating the insulating film 150 and connecting to each of the source electrodes 144. In the present embodiment, the wiring electrode 160 is mainly made of aluminum (Al). In the present embodiment, the wiring electrode 160 forms a field plate structure together with the wiring electrode 160 at the step portion 126.

  According to the semiconductor device 100 of the present embodiment, the p-type semiconductor region 112 is located in the semiconductor layer 111 in which the lower surface of the trench 122 is present. Can be alleviated.

  In addition, the p-type semiconductor region 112 at the step 126 can reduce the electric field concentration at the step 126.

  Further, since the wiring electrode 160 forms a field plate structure together with the wiring electrode 160 in the step portion 126, the electric field concentration at the end of the pn junction interface appearing in the step portion 126 can be reduced.

  Further, in the semiconductor device 100 of the present embodiment, since the p-type semiconductor region 112 is formed by a method described later, contamination and damage on the surface of the semiconductor layer 111 are suppressed. Hereinafter, among the manufacturing methods of the semiconductor device 100, a method of forming the p-type semiconductor region 112 will be particularly described.

A2. Method for manufacturing semiconductor device:
FIG. 2 is a process chart showing a method for manufacturing the semiconductor device 100. FIG. 2 shows a method of forming the p-type semiconductor region 112 among the methods of manufacturing the semiconductor device 100. The p-type semiconductor region 112 is formed by ion implantation of a p-type impurity into the semiconductor layer 111. In the present embodiment, first, an ion implantation mask forming step of forming an ion implantation mask on the semiconductor layer 111 formed on the substrate 110 is performed (S110).

  FIG. 3 is a process chart showing a process of forming a mask for ion implantation. FIGS. 4 to 9 are explanatory views showing the manner in which the ion implantation mask 20 is formed.

In the step of forming the ion implantation mask 20, the first layer 21p mainly made of at least one of aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and aluminum oxynitride (AlON) is formed on the semiconductor layer 111. Is formed (FIG. 3, S111). Note that “mainly composed of at least one of aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and aluminum oxynitride (AlON)” means that the total content of these materials is 90% or more in terms of mole fraction. Means that

FIG. 4 is a diagram illustrating the semiconductor device 100a in a manufacturing process, in which the first layer 21p is formed. In the semiconductor device illustrated in FIG. 4 and subsequent drawings, the substrate 110 located in the −Z-axis direction of the semiconductor layer 111 is omitted. In the present embodiment, the first layer 21p is mainly made of aluminum oxide (Al ₂ O ₃ ). Note that the thickness of the first layer 21p is preferably equal to or greater than 50 nm (nanometers), and is preferably equal to or less than 500 nm (nanometers). In the present embodiment, the thickness of the first layer 21p is 200 nm (nanometer). The first layer 21p is stacked on the semiconductor layer 111 by, for example, atomic layer deposition (ALD). Note that, in order to protect the surface of the semiconductor layer 111 on the −Z-axis direction side of the substrate 110 located in the −Z-axis direction, the surface of the substrate 110 on the −Z-axis direction side is protected from wet etching performed in a later step. It is preferable to form a protective film. For example, silicon oxide (SiO ₂ ) can be used as the protective film. The protective film can be formed, for example, by a plasma CVD method. The thickness of the protective film is, for example, 300 nm (nanometer).

  When the first layer 21p is formed, a second layer 22p mainly made of a metal having alkali resistance is formed on the first layer 21p (FIG. 3, S112). FIG. 5 is a diagram illustrating the semiconductor device 100b in a manufacturing process in which the second layer 22p is formed. In the present embodiment, the metal having alkali resistance has a property that an etching rate when immersed in a 22% by mass aqueous solution of tetramethylammonium hydroxide (TMAH) at 60 ° C. is less than 5 nm / min (nanometer / minute). Have. The metal having alkali resistance is preferably selected from at least one of titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), chromium (Cr), and manganese (Mn). . In the present embodiment, the second layer 22p is titanium (Ti). The thickness of the second layer 22p is, for example, 1 μm (micrometer). The second layer 22p is stacked on the first layer 21p by, for example, electron beam evaporation (EB evaporation). In another embodiment, the second layer 22p may be formed by resistance heating evaporation or may be formed by sputtering. Steps (FIG. 3, S111, S112) in which the first layer 21p and the second layer 22p are sequentially stacked on the semiconductor layer 111 are collectively referred to as “step (a)”.

  When the first layer 21p and the second layer 22p are formed, a resist pattern 23 is formed on the second layer 22p (FIG. 3, S113). FIG. 6 is a diagram showing the semiconductor device 100c in the manufacturing process, on which the resist pattern 23 has been formed. In the present embodiment, after a layer made of a photoresist is formed on the second layer 22p, a resist pattern (resist pattern 23) is formed by a photolithography technique. The resist pattern 23 is formed such that a portion corresponding to a region where the p-type semiconductor region 112 is formed is opened. This step is also referred to as “step (b)”.

  When the resist pattern 23 is formed, the second mask layer 22 is formed by dry-etching the second layer 22p from above the resist pattern 23 (S114 in FIG. 3). FIG. 7 is a diagram illustrating the semiconductor device 100d in the manufacturing process, on which the second mask layer 22 is formed. In this step, the second layer 22p is dry-etched using the resist pattern 23 as a mask. This step is also referred to as “step (c)”. Dry etching is performed using, for example, a chlorine-based gas.

  When the dry etching is performed, the resist pattern 23 is removed from the semiconductor device 100c (FIG. 3, S115). FIG. 8 is a diagram showing the semiconductor device 100e in a manufacturing process, from which the resist pattern 23 has been removed. The resist pattern 23 can be removed, for example, by immersing the semiconductor device 100c in a stripper.

  When the resist pattern 23 is removed, the first layer 21p is wet-etched using an alkaline solution to form the first mask layer 21 (S115 in FIG. 3). FIG. 9 is a diagram illustrating the semiconductor device 100f in a manufacturing process, in which the first mask layer 21 is formed. In this step, the first layer 21p is opened by immersing the semiconductor device 100d in an alkaline solution, and the first mask layer 21 is formed. Since the second mask layer 22 has alkali resistance, changes in the size of the opening of the second mask layer 22 and the shape of the end 22t of the second mask layer 22 before and after this step are suppressed. This step is also referred to as “step (d)”.

  In this step, in the first direction, the position of the end 21t of the first layer 21p is the same as the position of the end 22t of the second mask layer 22 or the position of the end 22t of the second mask layer 22 The wet etching is performed so that the inside is also inside. In the present embodiment, the wet etching is performed such that the position of the end 21t of the first layer 21p is inside the position of the end 22t of the second mask layer 22 in the first direction. FIG. 9 shows the first mask layer 21 whose end portion is located inside the position of the end portion 22t of the second mask layer 22. In the present embodiment, the difference d between the position of the end 21t of the first layer 21p and the position of the end 22t of the second mask layer 22 in the first direction is the film thickness of the second mask layer 22. The wet etching is performed so as to have a thickness of half or more. The wet etching is performed, for example, under the condition that the first layer 21p is etched at an etching rate of 40 nm / min.

  As described above, the ion implantation mask 20 including the first mask layer 21 and the second mask layer 22 is formed.

Returning to FIG. 2, when the ion implantation mask 20 is formed, an ion implantation step of implanting a p-type impurity into the semiconductor layer 111 by ion implantation is performed (FIG. 2, S130). FIG. 10 is a diagram showing a state of the ion implantation step. In the present embodiment, a p-type impurity is implanted into the semiconductor layer 111 from the + Z-axis direction side. By doing so, a p-type implantation region 112p into which a p-type impurity has been implanted is formed in a region corresponding to the opening of the ion implantation mask 20 (second mask layer 22) in the semiconductor layer 111 on the + Z-axis direction side. . In the present embodiment, the p-type impurity to be ion-implanted is magnesium (Mg), and the dose is 3 × 10 ¹⁵ cm ⁻² . The temperature of the ion implantation is 500 ° C., and the energy of the ion implantation is 350 keV. Note that this energy can be changed as appropriate depending on the thickness (depth of ion implantation) of the p-type semiconductor region 112 to be formed. In the present embodiment, the direction of ion implantation is substantially equal to the direction in which the first mask layer 21 and the second mask layer 22 are stacked (Z-axis direction). FIG. 10 shows a semiconductor device 100g in which a p-type implantation region 112p is formed.

After the ion implantation step is performed, an ion implantation mask removal step is performed (FIG. 2, S140). The ion implantation mask 20 is removed from above the semiconductor layer 111 by wet etching. FIG. 11 is a diagram showing the semiconductor device 100h in the manufacturing process, from which the ion implantation mask 20 has been removed. In the present embodiment, in the mask removal step for ion implantation, wet etching using hydrofluoric acid (HF) is performed. Therefore, in this step, both the first mask layer 21 mainly made of aluminum oxide (Al ₂ O ₃ ) and the second mask layer 22 mainly made of titanium (Ti) are removed. Further, the protective film made of silicon oxide (SiO ₂ ) formed on the surface of the substrate 110 on the −Z-axis direction side is also removed together with the first mask layer 21 and the second mask layer 22.

  When the first mask layer 21 is formed of aluminum nitride (AlN) or aluminum oxynitride (AlON), after removing the second mask layer 22 with hydrofluoric acid in the ion implantation mask removing step, The first layer 21p may be removed with an alkaline solution such as tetramethylammonium hydroxide (TMAH).

After the ion implantation mask removing step is performed, an activation step of activating the ion-implanted p-type impurities is performed (S150 in FIG. 2). The activation step is performed, for example, at a temperature of 1150 ° C. in an atmosphere containing ammonia (NH ₃ ) for 2 minutes. The temperature of the heat treatment is preferably 1000 ° C. or higher, more preferably 1050 ° C. or higher, from the viewpoint of more surely activating the impurities. The heat treatment temperature is preferably 1200 ° C. or lower, more preferably 1150 ° C. or lower. The heat treatment time is preferably 1 minute or more, and more preferably 10 minutes or less. The heat treatment may be performed in an atmosphere containing ammonia, an atmosphere containing hydrogen, an atmosphere containing ammonia and hydrogen, or an atmosphere containing nitrogen, and is preferably performed in an atmosphere containing ammonia (NH ₃ ). Note that a protective film may be formed to prevent the upper surface of the semiconductor layer 111 on which the p-type implantation region 112p is formed from being roughened during the heat treatment. As a material of the protective film, for example, aluminum nitride (AlN) can be used. If a protective film is formed, the protective film is removed after the heat treatment. By performing the activation step, the donor element in the p-type implantation region 112p is activated, and the p-type semiconductor region 112 is formed. FIG. 13 is a diagram showing the semiconductor device 100i in the manufacturing process, in which the p-type semiconductor region 112 has been formed.

  As described above, the p-type semiconductor region 112 is formed by ion implantation using the ion implantation mask 20.

  In the present embodiment, a stacked body in which the semiconductor layer 113 and the semiconductor layer 114 are sequentially stacked is formed on the semiconductor layer 111 in which the p-type semiconductor region 112 is formed. Thereafter, dry etching is performed on the stacked body to form the trench 122 and the recess 124, and the respective insulating films and the respective electrodes are formed. Thus, the semiconductor device 100 is manufactured.

  FIG. 13 is a diagram showing a cross-sectional SEM image of the ion implantation mask 20. FIG. 13 shows the ion implantation mask 20 formed by the step of forming the ion implantation mask 20 (FIG. 3, S111 to S116). FIG. 13 shows an angle θ between the X direction which is the first direction and the end 22t of the second mask layer 22. The angle θ shown in FIG. 13 is 86.4 °. Generally, the shape formed by dry etching is clearer than the shape formed by wet etching. In the present embodiment, since the second mask layer 22 is formed by dry etching of the second layer 22p, as shown in FIG. 13, the formed ion implantation mask 20 is provided at the end 22t of the second mask layer 22. Has good verticality. In the ion implantation mask 20 shown in FIG. 13, the position of the end 21t of the first mask layer 21 (the wet-etched first layer 21p) and the position of the end 22t of the second mask layer 22 are different. The difference d is equal to or less than half the thickness D of the second mask layer 22.

A3. effect:
According to the method of manufacturing the semiconductor device 100 of the present embodiment, the first layer 21p mainly includes at least one of aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and aluminum oxynitride (AlON). It is possible to prevent the surface of the semiconductor layer 111 made of group III nitride from being contaminated by silicon (Si). Further, at the time of dry etching, the first layer 21p functions as a protective layer of the semiconductor layer 111, so that damage to the semiconductor layer 111 can be suppressed. Further, since the second mask layer 22 is formed by dry etching, the opening of the second mask layer 22 can be controlled to a desired size. Therefore, a p-type semiconductor region 112 of a desired size can be formed in the semiconductor layer 111 by ion implantation using the ion implantation mask 20. Further, since the second mask layer 22 has alkali resistance, it is possible to prevent the shape of the second mask layer 22 from being changed by wet etching. Therefore, the p-type semiconductor region 112 having a desired size can be formed in the semiconductor layer 111 by ion implantation using the ion implantation mask 20, and the miniaturized semiconductor device 100 can be manufactured.

The first mask layer 21 mainly includes at least one of aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and aluminum oxynitride (AlON), and the second mask layer 22 includes titanium (Ti), By mainly using at least one of zirconium (Zr), hafnium (Hf), vanadium (V), chromium (Cr), and manganese (Mn), a comparison using an ion implantation mask 20 at 500 ° C. Ion implantation can be performed at a relatively high temperature. Therefore, damage to the semiconductor layer 111 due to ion implantation can be suppressed.

  In the present embodiment, the metal having alkali resistance has a property that the etching rate when immersed in a 22% by mass aqueous solution of tetramethylammonium hydroxide (TMAH) at 60 ° C. is less than 5 nm / min. Therefore, it is possible to suppress the shape of the second mask layer 22 from being changed by wet etching.

  In the present embodiment, the difference d between the position of the end 21t of the first layer 21p and the position of the end 22t of the second mask layer 22 in the first direction is the film thickness of the second mask layer 22. Since the first layer 21p is wet-etched so as to have a thickness equal to or less than half of the thickness D, the second mask layer 22 can be prevented from being separated from the first mask layer 21. Further, when the direction of ion implantation is inclined with respect to the direction in which the first mask layer 21 and the second mask layer 22 are stacked, ions are injected into the semiconductor layer 111 located inside the opening of the second mask layer 22. Injection can be suppressed.

  Further, in the present embodiment, since the thickness of the first layer 21p is 50 nm or more, it is possible to further prevent the semiconductor layer 111 from being damaged by dry etching. Further, since the thickness of the first layer 21p is 500 nm or less, the time required for the formation of the first layer 21p and the wet etching of the first layer 21p is shorter than the case where the thickness of the first layer 21p is larger than 500 nm. Can be suppressed from increasing.

  When the thickness of the first layer 21p is relatively large, while the first layer 21p is opened by wet etching, the lower side of the second mask layer 22 (−Z There is a possibility that the wet etching of the first layer 21p located on the (axial side) proceeds too much. In such a case, the difference d between the position of the end of the first layer 21p (the end 21t of the first mask layer 21) wet-etched and the position of the end 22t of the second mask layer 22 is large. Therefore, the second mask layer 22 may be separated from the first mask layer 21. However, in the present embodiment, since the thickness of the first layer 21p is 500 nm or less, the position of the end of the wet-etched first layer 21p (the end 21t of the first mask layer 21) and the position of the second mask An increase in the difference d from the position of the end 22t of the layer 22 can be suppressed.

In the present embodiment, the first layer 21p is formed of aluminum oxide (Al ₂ O ₃ ), and after the ion implantation step, the first mask layer 21 and the second mask layer 22 are formed with hydrofluoric acid (HF). Is removed at a time, so that the manufacturing process of the semiconductor device can be simplified.

B. Modification:
In the above embodiment, the metal having alkali resistance has a property that the etching rate when immersed in a 22% by mass aqueous solution of tetramethylammonium hydroxide (TMAH) at 60 ° C. is less than 5 nm / min. On the other hand, the metal having alkali resistance may have an etching rate of 5 nm / min or more when immersed in a 22% by mass aqueous solution of tetramethylammonium hydroxide (TMAH) at 60 ° C., for example, 6 nm / min. Other values such as min and 10 nm / min may be used.

  In the above embodiment, the difference d between the position of the end 21t of the first layer 21p and the position of the end 22t of the second mask layer 22 in the first direction is the thickness of the second mask layer 22. The first layer 21p is wet-etched so as to be less than half of D. On the other hand, the difference d may be larger than half of the film thickness D.

  In the embodiment described above, the thickness of the first layer 21p is not less than 50 nm and not more than 500 nm. On the other hand, the thickness of the first layer 21p may be smaller than 50 nm, and may be, for example, 40 nm, 35 nm, or the like. The thickness of the first layer may be larger than 500 nm, for example, 550 nm or 600 nm.

In the above-described embodiment, another alkaline etchant such as potassium hydroxide (KOH), ammonium hydroxide (NH ₄ OH), or sodium hydroxide (NaOH) is used as the alkaline solution for wet-etching the first layer 21p. May be used.

  In the above embodiment, each semiconductor layer is formed using gallium nitride (GaN), and the semiconductor device 100 is a GaN-based semiconductor device. On the other hand, the semiconductor layer 111 may be mainly made of a group III nitride, and each semiconductor layer may be made of another material such as aluminum nitride (AlN) or indium nitride (InN).

  The semiconductor layer to which the present invention is applied is not limited to the above-described semiconductor layer 111, and may be another semiconductor layer. Further, the semiconductor device to which the present invention is applied is not limited to the trench MOSFET described in the above embodiment, and may be any semiconductor device in which a p-type semiconductor region is formed by ion implantation. For example, a Schottky barrier diode, It may be a junction type transistor, a bipolar transistor, an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor), a MESFET (metal-semiconductor field effect transistor), a thyristor, or the like.

  The present invention is not limited to the above-described embodiments, examples, and modified examples, and can be realized with various configurations without departing from the spirit thereof. For example, among the technical features in the embodiments, examples, and modifications, those that correspond to the technical features in each mode described in the Summary of the Invention section are for solving some or all of the problems described above. Alternatively, in order to achieve some or all of the effects described above, replacement and combination can be appropriately performed. Further, technical features that are not described as essential in the present specification can be deleted as appropriate.

Reference Signs List 20 ion implantation mask 21 first mask layer 21p first layer 21t end 22 second mask layer 22p second layer 22t end 23 resist pattern 100 semiconductor device 100a, 100b, 100c 100d, 100e, 100f, 100g, 100h, 100i Semiconductor device in manufacturing process 110 Substrate 111 Semiconductor layer 112 P-type semiconductor region 112p P-type injection region 113 Semiconductor layer 114 Semiconductor layer 122 Trench 124 Recess 126 stepped portion 129 terminal portion 130 insulating film 142 gate electrode 144 source electrode 148 drain electrode 150 insulating film 160 wiring electrode C control region D film thickness d difference

Claims (6)

A method for manufacturing a semiconductor device, comprising:
An ion implantation mask forming step of forming an ion implantation mask on a semiconductor layer mainly made of group III nitride and extending along the first direction;
An ion implantation step of implanting a p-type impurity by ion implantation into the semiconductor layer on which the ion implantation mask is formed,
The ion implantation mask forming step,
(A) A first layer mainly composed of at least one of aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and aluminum oxynitride (AlON), and a metal having alkali resistance on the semiconductor layer. A step of sequentially stacking a main second layer,
(B) forming a resist pattern on the second layer;
(C) dry etching the second layer from above the resist pattern to form a second mask layer;
(D) the position of the end of the first layer in the first direction is the same as the position of the end of the second mask layer or the position of the end of the second mask layer in the first direction; Forming the first mask layer by wet etching the first layer so as to be on the inside.
A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 1, wherein
The method for manufacturing a semiconductor device, wherein the metal having alkali resistance has a property that an etching rate when immersed in 22% by mass of tetramethylammonium hydroxide (TMAH) at 60 ° C. is less than 5 nm / min. A method for manufacturing a semiconductor device according to claim 1 or 2, wherein:
The method for manufacturing a semiconductor device, wherein the metal having alkali resistance is at least one of titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), chromium (Cr), and manganese (Mn). 4. The method of manufacturing a semiconductor device according to claim 1, wherein:
In the step (d), the difference between the position of the end of the first layer and the position of the end of the second mask layer in the first direction is the thickness of the second mask layer. A method for manufacturing a semiconductor device, wherein the first mask layer is formed by wet etching the first layer so as to be half or less. A method for manufacturing a semiconductor device according to claim 1, wherein:
The method of manufacturing a semiconductor device, wherein in the step (a), the first layer is formed on the semiconductor layer to have a thickness of 50 nm or more and 500 nm or less. A method for manufacturing a semiconductor device according to claim 1, wherein:
The first layer is formed of aluminum oxide (Al ₂ O ₃ ),
A method for manufacturing a semiconductor device, comprising a step of removing the first mask layer and the second mask layer with hydrofluoric acid (HF) after the ion implantation step.