JP2015204359A - Insulated gate nitride semiconductor transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem of a HEMT including a laminated structure of a nitride semiconductor electron transit layer having a small bandgap, and a nitride semiconductor electron supply layer having a large bandgap, and including a gate electrode penetrating the electron supply layer from the upper surface thereof and reaching the electron transit layer, that the threshold voltage is not stabilized because a nitrogen defect is formed on the bottom face of a recess for the gate electrode when etching the recess.SOLUTION: Etching is stopped in a state where the bottom face 16a of a recess is formed of an n-type nitride semiconductor 8. Nitrogen defect is less likely to occur for the n-type at the time of etching, and the threshold voltage of a HEMT is stabilized. It is also possible to make the nitride semiconductor forming an electron transit layer 8 n-type, and to form an n-type region separately from an i-type electron transit layer, and to form the bottom face of a recess in the n-type region.

Description

  The present specification discloses a technique for stabilizing the threshold voltage of a field-effect transistor using a nitride semiconductor heterojunction. That is, a technique that enables mass production of field-effect transistors with uniform threshold voltages is disclosed.

  When an electron transit layer made of a nitride semiconductor and an electron supply layer made of a nitride semiconductor having a band gap larger than that of the nitride semiconductor forming the electron transit layer are heterojunction, two-dimensional electrons along the heterojunction plane Gas is formed. When a source electrode and a drain electrode are provided on the surface of the electron supply layer, and a gate electrode is formed at a position sandwiched between the source electrode and the drain electrode (that is, a position where the source electrode and the drain electrode are divided), the source electrode is driven by the potential of the gate electrode. And a phenomenon in which the resistance between the drain electrode changes. Transistors that use this phenomenon are known. In this specification, the above transistor is referred to as a HEMT (High Electron Mobility Transistor). In order to keep the electron mobility high, an i-type nitride semiconductor having a low impurity concentration is used for the electron transit layer.

  Under normal conditions, the HEMT threshold voltage is a negative voltage. A technique for raising the threshold voltage toward the positive side has been proposed. In the technique of Patent Document 1, the electron supply layer is etched to form a recess. Etching is continued until the recess penetrates the electron supply layer and the electron transit layer is exposed at the bottom of the recess. When the electron transit layer is exposed on the bottom surface of the recess, the etching is finished, an insulating film is formed on the wall surface of the recess, and a gate electrode is filled inside the insulating film. The gate electrode is formed inside the recess while being covered with an insulating film. By providing the gate electrode in the recess, the threshold voltage is raised to the positive side.

International Publication No. WO2003 / 071607

Although the threshold voltage can be raised to the plus side by the technique of providing the gate electrode in the recess, the raising effect is unstable, and it is difficult to mass-produce HEMTs with uniform threshold voltages.
In this specification, by providing the gate electrode in the recess, not only the threshold voltage is raised to the plus side, but also the raising effect is stabilized, and HEMTs with uniform threshold voltages (small variations in threshold voltage) can be mass-produced. The technology to do is disclosed.

The reason why the effect of raising the threshold voltage by providing the gate electrode in the recess is unstable is studied, and the electron transit layer exposed to the bottom surface of the recess in the process of continuing etching until the electron transit layer is exposed to the bottom surface of the recess. It was found that this was because etching damage was applied to the electron transport layer and nitrogen defects were generated in the electron transit layer exposed on the bottom surface of the recess. It was found that the threshold voltage is not stable because the nitrogen defect becomes a trap for trapping electrons.
Therefore, we studied a technology that does not cause nitrogen defects (or resists nitrogen defects) even after etching. As a result, the following was found. As described above, in order to keep the electron mobility high, an i-type nitride semiconductor having a low impurity concentration is often used for the electron transit layer. In the case of an i-type nitride semiconductor, nitrogen defects are likely to occur due to etching. The same applies to p-type nitride semiconductors, and nitrogen defects are likely to occur due to etching. On the other hand, if an n-type nitride semiconductor is used, nitrogen defects do not occur even if etching is performed (or nitrogen defects are not easily generated).
In the technique described in this specification, a HEMT having a structure in which an n-type nitride semiconductor is exposed on the bottom surface of the recess is created by utilizing the above knowledge. If the n-type nitride semiconductor is exposed on the bottom surface of the recess, the generation of nitrogen defects can be suppressed, and the variation in threshold voltage can be suppressed.

The HEMT disclosed in the present specification includes an electron transit layer formed of a nitride semiconductor and an electron supply layer stacked on the electron transit layer. The electron supply layer is formed of a nitride semiconductor having a larger band gap than the nitride semiconductor forming the electron transit layer, and a heterojunction interface is obtained between the electron transit layer and the electron supply layer.
In the HEMT disclosed in this specification, a recess is formed that penetrates the electron supply layer from the upper surface of the electron supply layer and reaches the electron transit layer. The wall surface of the recess is covered with a gate insulating film. The gate electrode is formed in the recess while being covered with a gate insulating film. The gate electrode does not need to fill the recess, and the gate electrode only needs to be formed along the bottom and side surfaces of the recess.
In the HEMT disclosed in this specification, the bottom surface of the recess is formed of an n-type nitride semiconductor (that is, the n-type nitride semiconductor is exposed on the bottom surface of the recess). The n-type nitride semiconductor that forms the bottom surface of the recess may be a part of the electron transit layer. Alternatively, an n-type nitride semiconductor region may be formed separately from the electron transit layer, and the n-type nitride semiconductor region may be exposed at the bottom surface of the recess.

The electron transit layer may be formed of an n-type nitride semiconductor, and the n-type nitride semiconductor may form a bottom surface of the recess.
Alternatively, an n-type nitride semiconductor region may be formed separately from the electron transit layer, and the n-type nitride semiconductor region may be exposed at the bottom surface of the recess. For example, an n-type nitride semiconductor layer may be formed below the electron transit layer, and the bottom surface of the recess may be formed of an n-type nitride semiconductor layer. Alternatively, an n-type nitride semiconductor region may be formed in a part of the electron transit layer, and the recess bottom may be formed in the n-type nitride semiconductor region. When an n-type nitride semiconductor is provided separately from the electron transit layer, the electron transit layer can be formed of an i-type nitride semiconductor.

  According to the structure in which the n-type nitride semiconductor is exposed on the bottom surface of the recess, the generation of nitrogen defects is suppressed and the threshold voltage is stabilized, while the effect of raising the threshold voltage to the positive side is reduced. If the back barrier layer is formed under the electron transit layer, the threshold voltage can be raised to the plus side. When used in combination with a technique for forming a back barrier layer below the electron transit layer, the threshold voltage can be raised to the plus side, and the raised threshold voltage can be stabilized.

  A GaN layer may be formed above the electron supply layer. The GaN layer becomes a cap layer, and the HEMT characteristics are stabilized.

Sectional drawing which shows the 1st step of the manufacturing process of HEMT of 1st Example. Sectional drawing which shows the 2nd step of the manufacturing process of HEMT of 1st Example. Sectional drawing which shows the 3rd step of the manufacturing process of HEMT of 1st Example. Sectional drawing which shows the 4th step of the manufacturing process of HEMT of 1st Example. Sectional drawing which shows the 5th step of the manufacturing process of HEMT of 1st Example. Sectional drawing which shows the 6th step of the manufacturing process of HEMT of 1st Example. Sectional drawing of HEMT of 1st Example. Sectional drawing of HEMT of 2nd Example. Sectional drawing of HEMT of 3rd Example. Sectional drawing of HEMT of 4th Example. Sectional drawing of HEMT of 5th Example. Sectional drawing of HEMT of 6th Example. Sectional drawing which shows the 1st step of the manufacturing process of HEMT of 7th Example. Sectional drawing which shows the 2nd step of the manufacturing process of HEMT of 7th Example. Sectional drawing which shows the 3rd step of the manufacturing process of HEMT of 7th Example. Sectional drawing which shows the 4th step of the manufacturing process of HEMT of 7th Example. Sectional drawing which shows the 5th step of the manufacturing process of HEMT of 7th Example. Sectional drawing which shows the 6th step of the manufacturing process of HEMT of 7th Example. Sectional drawing of HEMT of 7th Example. The figure which shows the relationship between the Fermi level of GaN, and the production energy of a nitrogen defect. (A) shows the surface potential before and after etching of n-type GaN, and (B) shows the surface potential before and after etching of p-type GaN.

The features of the technology disclosed in this specification will be summarized below. The items described below have technical usefulness independently.
(First Feature) The electron transit layer is formed of GaN, and the electron supply layer is formed of In _1-xy Al _x Ga _y N (0 ≦ x ≦ 1, 0 ≦ y <1, 0 ≦ x + y ≦ 1). Has been.
(Second feature) The distance from the interface between the gate insulating film in contact with the bottom surface of the gate electrode and the n-type nitride semiconductor to the back barrier layer is shorter than the distance at which the threshold voltage is positive and the normally-off characteristic is imparted.
(Third feature) A p-type or i-type nitride semiconductor layer is formed on the lower side (deep side) of the n-type nitride semiconductor layer, which becomes a back barrier layer.
(Fourth feature) A nitride semiconductor layer having a larger band gap is formed below (deep side) of the n-type nitride semiconductor layer, which becomes a back barrier layer.
(Fifth Feature) A nitride semiconductor layer doped with carbon or iron is formed under the n-type nitride semiconductor layer (deep side), which becomes a back barrier layer.
(Sixth feature) When the semiconductor substrate is viewed in plan, an n-type nitride semiconductor layer that forms the bottom surface of the recess extends from the source electrode to the drain electrode.
(Seventh feature) When the semiconductor substrate is viewed in plan, an n-type nitride semiconductor region that forms the bottom surface of the recess is formed only in the recess formation range.

(First embodiment)
FIG. 7 shows a cross section of the HEMT of the first embodiment. Reference numbers indicate the following.
2: Substrate. A sapphire substrate, a Si substrate, or a GaN substrate is used.
4: Buffer layer. A crystal layer capable of growing GaN on a sapphire substrate or Si substrate. This can be omitted if a GaN substrate is used for the substrate 2.
6: Back barrier layer. A layer that raises the threshold voltage to the positive side. The various layers described in the third to fifth features are the back barrier layers. In this embodiment, an i-type GaN layer is used. Alternatively, the back barrier layer may be a p-type GaN layer, a carbon-doped GaN layer, or an iron-doped GaN layer.
8: Electron travel layer. In this embodiment, n-type GaN is used. In this embodiment, the n-type nitride semiconductor layer 8 also serves as a layer for forming the recess bottom surface.
10: Electron supply layer. In this embodiment, AlGaN is used. It has a larger band gap than the nitride semiconductor (GaN in this embodiment) forming the electron transit layer 8.
12: Insulating film.
16: Recess.
16a: bottom surface of the recess.
18: Gate insulating film. The wall surface (bottom surface and side surface) of the recess 16 is covered.
20: Gate electrode. It is made of metal or doped polysilicon. It is formed so as to fill the inside of the recess 16. The gate electrode 20 does not need to fill the recess 16 and may be formed along the bottom and side surfaces of the recess. The gate electrode 20 is formed between a source electrode 28 and a drain electrode 30, which will be described later, at a position where they are divided.
22: Interlayer insulating film 28: Source electrode 30: Drain electrode In the HEMT of the first embodiment, the resistance between the source electrode 28 and the drain electrode 30 varies depending on the potential of the gate electrode 20. Since the depletion layer spreads from the back barrier layer 6 into the electron transit layer 8, the threshold voltage is raised to the positive side and adjusted to a normally-off characteristic. When a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode 20, electrons constituting the two-dimensional electron gas formed along the interface between the electron transit layer 8 and the electron supply layer 10 are converted into the source electrode 28 and the drain electrode 30. To move between. The bottom surface 16a of the recess 16 is formed by a layer formed of an n-type nitride semiconductor (also used as the electron transit layer 8), and the nitride semiconductor that forms the bottom surface 16a of the recess 16 when the recess 16 is formed. Nitrogen defects are less likely to occur. Therefore, the threshold voltage is stabilized. That is, a HEMT with a stable threshold voltage can be mass-produced.

The HEMT of FIG. 7 is manufactured through FIGS.
FIG. 1: A buffer layer 4, an i-type GaN layer 6, an n-type GaN layer 8, an AlGaN layer 10, and an insulating layer 12 are sequentially stacked on the substrate 2. The impurity concentration of the n-type GaN layer 8 is 1 × 10 ¹⁵ cm ⁻³ or more and the thickness is 100 nm or less. The i-type GaN layer 6 becomes the back barrier layer 6, the n-type GaN layer 8 becomes the electron transit layer 8 also serving as the bottom surface of the recess, and the AlGaN layer 10 becomes the electron supply layer 10.
FIG. 2: On the surface of the insulating layer 12, a resist layer 14 is formed in which an opening 14a is formed in a formation range of a recess 16 to be described later.
FIG. 3: The recess 16 is formed by dry etching from the opening 14a. In this step, etching is performed until the intermediate depth of the n-type GaN layer 8 is reached through the insulating layer 12 and the AlGaN layer 10. The distance from the bottom surface 16a of the recess 16 to the upper surface of the i-type GaN layer 6 is 5 nm or more. If the etching is completed with the n-type GaN layer 8 of 5 nm or more remaining, no etching damage is applied to the i-type GaN layer 6.
When the recess 16 is formed by etching, the bottom surface 16a of the recess 16 is damaged. When the recess 16 is completed, etching energy is applied to a part of the GaN layer 8 that becomes the bottom surface 16 a of the recess 16. If p-type or i-type is used for the GaN layer 8, nitrogen defects are generated in the GaN layer 8 that becomes the bottom surface 16 a of the recess 16 by etching. Since nitrogen defects capture electrons, the threshold voltage is not stable when nitrogen defects occur. In the present embodiment, the recess 16 is completed by etching the n-type GaN layer 8.

  The horizontal axis of FIG. 20 shows the Fermi level of GaN doped with impurities, the left side corresponds to GaN heavily doped with p-type impurities, the right side corresponds to GaN heavily doped with n-type impurities, The center of the direction corresponds to i-type GaN. The vertical axis represents the generation energy of nitrogen defects. Obviously, GaN doped with n-type impurities has a higher generation energy of nitrogen defects.

In the present embodiment, the recess bottom surface 16a is etched under the condition that only energy less than the generation energy of the nitrogen defect for GaN doped with n-type impurities is applied. Since GaN doped with n-type impurities has high nitrogen defect generation energy, etching can be performed while satisfying the above conditions.
If GaN doped with an i-type or p-type impurity is used, the GaN layer 8 may be etched under the condition that only energy less than the generation energy of the nitrogen defect is applied to the recess bottom surface because the generation energy of the nitrogen defect is low. Can not.

  FIG. 21 shows the measurement result of the surface potential at the bottom of the etching. Specifically, the result of measurement by XPS (X-ray photoelectron spectroscopy) is shown. (B) shows the result of measuring p-type GaN, curve C2 shows before etching, and curve C3 shows after etching. On the other hand, (A) shows the result of measuring n-type GaN, and there is no change before and after etching. The measurement result before etching is also C1, and the measurement result after etching is also C1. It is confirmed that when the p-type GaN is etched, the recess bottom is altered, whereas when the n-type GaN is etched, the recess bottom is not altered.

FIG. 4 shows a stage in which the resist layer 14 shown in FIG. 3 is removed and a gate insulating film 18 is formed on the wall surface (bottom surface and side surface) of the recess 16 and the surface of the insulating layer 12. As the gate insulating film 18, an SiO ₂ film, an SiN film, an Al ₂ O ₃ film, or the like can be used, and a low pressure CVD method, a plasma CVD method, an atomic layer deposition method, or the like is used as a deposition method. Can do.
FIG. 5 shows a state in which the gate electrode 20 is formed. The gate electrode 20 is formed so as to cover the wall surface (side wall and bottom surface) of the recess 16 while being surrounded by the gate insulating film 18. The gate electrode 20 may reach the upper surface of the insulating film 12. The gate electrode 20 is formed by patterning. For the gate electrode 20, Al, Ni, Ti, W, Cu, TiN, TaN, poly-Si, or the like can be used.
FIG. 6 shows a stage where the interlayer insulating film 22 is formed. Openings 24 and 26 are formed in the interlayer insulating film 22. The opening 24 is formed at the source electrode formation position, and the opening 26 is formed at the drain electrode formation position.
FIG. 7 shows a state in which the source electrode 28 is formed in the opening 24 and the drain electrode 30 is formed in the opening 26. For the source electrode 28 and the drain electrode 30, Al, Ti, W, Cu, TiN, TaN, or the like can be used. As described above, the HEMT is manufactured.

  In the HEMT described above, the bottom surface 16a of the recess 16 is formed of n-type GaN, so that nitrogen defects are not easily generated during the etching of the recess, and the threshold voltage is stabilized. The above structure enables mass production of HEMT with a stable threshold voltage.

Other embodiments will be described below. The same reference numerals are used for the same or equivalent members as those already described, and a duplicate description is omitted.
(Second embodiment)
As shown in FIG. 8, in this embodiment, an n-type GaN layer 8b is added between the electron transit layer 8a and the back barrier layer 6. The bottom surface 16a of the recess 16 is formed by the n-type GaN layer 8b. Since the bottom surface 16a of the recess 16 is formed of the n-type GaN layer 8b, nitrogen defects are unlikely to occur on the bottom surface 16a. The threshold voltage is stabilized.
According to the technique of providing the n-type GaN layer 8b separately from the electron transit layer 8a, the electron transit layer 8a does not need to be n-type. In this embodiment, the electron transit layer 8a is formed of i-type GaN. When the electron transit layer 8a is formed of i-type GaN, the electron mobility in the electron transit layer 8a can be maintained high, and a HEMT with low on-resistance and excellent response can be obtained.

(Third embodiment)
As shown in FIG. 9, the back barrier layer 6a may be formed of AlGaN.

(Fourth embodiment)
As shown in FIG. 10, a GaN layer 11 may be formed on the upper surface of the electron supply layer 10. The GaN layer 11 becomes a cap layer and stabilizes the operation of the HEMT.

(5th Example)
As shown in FIG. 11, the electron supply layer 10a may be formed of InAlN. A band gap larger than that of GaN constituting the electron transit layer 8 is provided.

(Sixth embodiment)
As shown in FIG. 12, the electron supply layer may be formed of a plurality of layers. In the sixth embodiment, the lower layer 10b is formed of an InGaN layer, and the upper layer 10c is formed of an AlGaN layer. The lower layer 10b may be formed of an InAlN layer or an AlN layer. Both have a larger band gap than GaN forming the electron transit layer 8. When the electron supply layer is formed of a plurality of layers, the electron density can be improved and the electron mobility can be improved.

(Seventh embodiment)
As shown in FIG. 19, a layer 7 serving both as a back barrier layer and an electron transit layer can also be used. When p-type GaN, carbon-doped GaN, or iron-doped GaN is used for the layer 7, the threshold voltage is raised to the positive side. In the case of the above GaN, a two-dimensional electron gas is generated at the interface with the AlGaN layer 10 and also serves as an electron transit layer.
In order to stabilize the threshold voltage, the bottom surface 16a of the recess 16 is formed by the locally formed n-type GaN region 8d. The n-type GaN region 8 d is a region that prevents a nitrogen defect from occurring when the recess 16 is formed, and may be in the range where the recess 16 is formed.

13 to 18 show a manufacturing process of the HEMT shown in FIG.
FIG. 13: A buffer layer 4, an i-type GaN layer 7, an AlGaN layer 10, and an insulating layer 12 are sequentially stacked on the substrate 2. In FIG. 1, the existing n-type GaN layer 8 is not formed.
FIG. 2: On the surface of the insulating layer 12, a resist layer 14 is formed in which an opening 14a is formed in a formation range of a recess 16 to be described later.
FIG. 14: Etching from the opening 14a forms a shallow recess 16b. In this step, only the insulating layer 12 is etched until the AlGaN layer 10 is exposed. Alternatively, the i-type GaN layer 7 may be exposed by etching the insulating layer 12 and the AlGaN layer 10. In the former case, the AlGaN layer 10 is etched at the time of the second recess formation etching described later.
FIG. 15: shows a stage after the n-type impurity is implanted using the resist layer 14 or the insulating film 12 as a mask after the shallow recess 16b is formed. At this time, the impurities are implanted with energy reaching the GaN layer 7 through the AlGaN layer 10. However, the impurities remain in the GaN layer 7 and are implanted with energy that does not penetrate the GaN layer 7. As a result, an n-type GaN region 8c is formed.
FIG. 16 shows the stage of etching using the insulating film 12 as a mask. In this step, the bottom surface of the recess that is not covered with the insulating film 12 is etched to complete the deep recess 16c. In this step, etching is performed until the AlGaN layer 10 is removed and the n-type GaN region is exposed on the bottom surface of the recess 16. On the bottom surface 16a of the recess 16, a region 8d in which the n-type GaN region 8c is thin remains.
FIG. 17 shows the stage where the gate insulating film 18 is formed. This corresponds to FIG.
FIG. 18: The gate electrode 20 is formed. This corresponds to FIG.
Thereafter, the process of FIG. 6 is performed. Thereby, the structure of FIG. 19 is manufactured.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: Substrate 4: Buffer layer 6: Back barrier layer 6a: AlGaN layer 7: Doped GaN layer 8: Electron travel layer 8a: i-type GaN layer 8b: n-type GaN layer 8c: n-type GaN layer 8d: local n-type GaN layer 10: electron supply layer 10a: InGaN layer 10b: InGaN, InAlN, AlN
10c: AlGaN
11: cap layer 12: insulating film 14: resist layer 14a: opening 16: recess 16a: bottom 16b: shallow recess 16c: deep recess 18: gate insulating film 20: gate electrode 22: interlayer insulating film 24: opening 26: opening 28 : Source electrode 30: Drain electrode

Claims (7)

An electron transit layer formed of a nitride semiconductor;
An electron supply layer formed of a nitride semiconductor having a larger band gap than the nitride semiconductor forming the electron transit layer, and stacked on the electron transit layer;
A recess penetrating the electron supply layer from the upper surface of the electron supply layer and reaching the electron transit layer;
A gate insulating film covering the wall surface of the recess;
A gate electrode formed in the recess in a state covered with the gate insulating film;
A HEMT in which the bottom surface of the recess is formed of an n-type nitride semiconductor.   The HEMT according to claim 1, wherein a back barrier layer is formed below the electron transit layer.   The HEMT according to claim 1 or 2, wherein the electron transit layer is formed of an n-type nitride semiconductor, and the n-type nitride semiconductor forms a bottom surface of the recess.   The HEMT according to claim 1, wherein an n-type nitride semiconductor layer that forms a bottom surface of the recess is formed below the electron transit layer.   The HEMT according to claim 1, wherein a region of an n-type nitride semiconductor that forms a bottom surface of the recess is formed in a part of the electron transit layer.   6. The HEMT according to claim 4, wherein the electron transit layer is formed of an i-type nitride semiconductor.   The HEMT according to any one of claims 1 to 6, wherein a GaN layer is formed above the electron supply layer.

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