CN114334874A - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN114334874A CN114334874A CN202011056478.8A CN202011056478A CN114334874A CN 114334874 A CN114334874 A CN 114334874A CN 202011056478 A CN202011056478 A CN 202011056478A CN 114334874 A CN114334874 A CN 114334874A
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Abstract
The invention provides a semiconductor device and a forming method thereof, wherein the semiconductor device comprises: a substrate; a conductive layer within the substrate; an oxide layer on a portion of the surface of the substrate; the high-resistance layer is positioned on the oxide layer; the dielectric layer is positioned on the substrate and the high-resistance layer; the first through hole is positioned in the medium layer, and the bottom of the first through hole is exposed out of the top surface of the conducting layer; the second through hole is positioned in the medium layer, and the bottom of the second through hole is exposed out of the top surface of the oxide layer; the connecting layer is positioned in the first through hole; the adhesion layers are positioned on the surface of the dielectric layer, the surface of the connecting layer and the side wall and the bottom of the second through hole; the metal layer is positioned on the adhesion layer and is filled in the second through hole; the formed semiconductor device is ensured to have higher quality.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. The device is widely used as the most basic semiconductor device at present, and the traditional planar device has weak control capability on channel current, short channel effect is generated to cause leakage current, and finally the electrical performance of the semiconductor device is influenced.
In the manufacturing process of a semiconductor device, contact holes need to be formed in a source region, a drain region, a gate structure or the like of a transistor, then conductive materials are filled in the contact holes to form a conductive layer, after the conductive layer is formed, a connecting layer is formed on the conductive layer and the high-resistance layer by using a selective growth process, and the transistor is electrically connected with the outside by using the connecting layer. However, the height of the connecting layer formed on the high-resistance layer and the height of the connecting layer formed on the conductive layer are different, so that various connecting modes of the connecting layer on the high-resistance layer occur, and finally, the connecting line on the high-resistance layer is changed greatly, so that different interface problems and yield problems occur between the metal layer and the connecting layer in the process of forming the metal layer on the connecting layer on the high-resistance layer, and the use of the semiconductor device is limited.
Therefore, how to improve the quality of the metal layer and the connection layer formed on the high resistance layer while realizing the connection layer selectively grown on the conductive layer, thereby improving the performance of the final formed semiconductor device, is a problem which is urgently needed to be solved at present.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which ensure that the formed semiconductor device has higher quality.
To solve the above problems, the present invention provides a semiconductor device comprising: a substrate; a conductive layer within the substrate; an oxide layer on a portion of the surface of the substrate; the high-resistance layer is positioned on the oxide layer; the dielectric layer is positioned on the substrate and the high-resistance layer; the first through hole is positioned in the medium layer, and the bottom of the first through hole is exposed out of the top surface of the conducting layer; the second through hole is positioned in the medium layer, and the bottom of the second through hole is exposed out of the top surface of the oxide layer; the connecting layer is positioned in the first through hole; the adhesion layers are positioned on the surface of the dielectric layer, the surface of the connecting layer and the side wall and the bottom of the second through hole; and the metal layer is positioned on the adhesion layer and is filled in the second through hole.
Optionally, the thickness of the oxide layer is
To
Optionally, an etching selection ratio of the oxide layer to the high-resistance layer is less than 1.
Optionally, the oxide layer is made of silicon oxide or silicon nitride.
Correspondingly, the invention also provides a method for forming the semiconductor device, which comprises the following steps: providing a substrate, and forming an oxide layer and a high-resistance layer on the oxide layer on part of the surface of the substrate; forming dielectric layers on the surface of the high-resistance layer and the surface of the substrate which is not covered by the oxide layer and the high-resistance layer; and etching the dielectric layer, forming a first through hole and a second through hole in the dielectric layer, wherein the bottom of the first through hole is exposed out of the top surface of the conductive layer in the substrate, and the bottom of the second through hole is exposed out of the top surface of the oxide layer.
Optionally, the forming process of the oxide layer is an atomic layer deposition process or a chemical vapor deposition process.
Optionally, the thickness of the oxide layer is
To
Optionally, an etching selection ratio of the oxide layer to the high-resistance layer is less than 1.
Optionally, after the first through hole and the second through hole are formed, a connection layer is formed in the first through hole.
Optionally, after the connection layer is formed, an adhesion layer is formed on the dielectric layer, the connection layer, and the sidewall and the bottom of the second through hole; and forming a metal layer on the adhesion layer, wherein the metal layer is filled in the second through hole.
Optionally, the oxide layer is made of silicon oxide or silicon nitride.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the semiconductor device, the bottom of the first through hole is exposed out of the top surface of the conductive layer, the bottom of the second through hole is exposed out of the top surface of the oxide layer, the connecting layer is arranged in the first through hole, the adhesion layer is positioned on the surface of the dielectric layer, the surface of the connecting layer and the side wall and the bottom of the second through hole, and the metal layer is positioned on the adhesion layer and fully fills the second through hole.
The forming method comprises the steps of forming an oxide layer and a high-resistance layer on the oxide layer on part of the surface of a substrate, forming a dielectric layer on the surface of the high-resistance layer and the surface of the substrate which is not covered by the oxide layer and the high-resistance layer, etching the dielectric layer, and forming a first through hole and a second through hole in the dielectric layer, wherein the bottom of the first through hole is exposed out of the top surface of a conductive layer in the substrate, and the bottom of the second through hole is exposed out of the top surface of the oxide layer; due to the presence of the oxide layer. In the process of forming the connecting layer in the subsequent first through hole, the connecting layer cannot be formed at the bottom of the second through hole, so that the problem of uneven growth height of the connecting layer does not exist in the second through hole, and meanwhile, the problem of interface difference does not exist in the high-resistance layer, so that the subsequent metal layer is directly formed in the second through hole, the quality of an interface formed by the metal layer in the second through hole can be improved, the performance of a finally formed semiconductor device is improved, and the application range of the semiconductor device is expanded.
Drawings
Fig. 1to 3 are schematic structural views of a semiconductor device formation process in one embodiment;
fig. 4 to 8 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
In the process of forming a semiconductor device, after a conductive layer is formed, a connection layer needs to be formed over the conductive layer, and connection is made between the connection layer and the metal layer 1(M1) on the upper layer. In the process of forming the connecting layer on the conducting layer, the connecting layer can be grown on the high-resistance layer at the same time, however, the problem that the connecting layer on the high-resistance layer is uneven in height growth in the growth process or the problem that the high-resistance layer at the bottom can be etched through in the process of growing the connecting layer can occur, so that the problem that a metal layer is formed on the high-resistance layer subsequently is caused, various different connecting modes can occur in the connecting process due to the connection difference between the metal layer and the through hole, the difference of electrical performance is caused finally, the performance of a semiconductor device is influenced, and the application range of the semiconductor device is limited.
Referring to fig. 1, a substrate 100 is provided, an etching stop layer 101 is formed on the substrate 100, a high resistance layer 102 is formed on a part of the surface of the etching stop layer 101, a dielectric layer 103 is formed on the etching stop layer 101 and on the high resistance layer 102, the dielectric layer 103 and the etching stop layer 101 located at the bottom of the dielectric layer 103 are etched to form a first through hole 104 and a second through hole 105, the bottom of the first through hole 104 is exposed to the top surface of a conductive layer 106 in the substrate 100, and the bottom of the second through hole 105 is exposed to the top surface of the high resistance layer 102.
Referring to fig. 2, wherein fig. 2 includes fig. 2a and fig. 2b, a connection layer 107 is formed in the first via 104, and the connection layer 107 is formed in the second via 105 during the process of forming the connection layer 107.
Referring to fig. 3, wherein fig. 3 includes fig. 3a and fig. 3b, an adhesion layer 108 is formed, and a metal layer 109 is formed on the adhesion layer 108.
Fig. 3a is a structural view of the metal layer 109 formed on the basis of fig. 2a, and fig. 3b is a structural view of the metal layer 109 formed on the basis of fig. 2 b.
Referring to fig. 3a, the adhesion layer 108 is formed on the surface of the dielectric layer 103, the surface of the connection layer 107 in the second via hole 105, and the sidewall of the second via hole 105, and the metal layer 109 is formed on the adhesion layer 108.
Referring to fig. 3b, the adhesion layer 108 is formed on the sidewall of the etched high resistance layer 102, the bottom and the sidewall of the second via hole 105, and the metal layer 109 is formed on the adhesion layer 108.
The inventors found that different areas may have different growth conditions during the formation of the connection layer 107 in the second via 105, and that two conditions may occur, namely, as shown in fig. 2a, the connection layer 107 with non-uniform surface height is formed in the second via 105; secondly, as shown in fig. 2b, in the process of forming the connection layer 107, the connection layer 107 etches away the high-resistance layer 102 at the bottom, which causes an inconsistent condition to occur at the interface of the etched high-resistance layer 102, so that in the process of forming the metal layer 109, the difference in the forming quality of the metal layer 109 in the second via hole 105 is large, and thus, during a performance test, a large electrical difference is likely to occur, which affects the performance of a finally formed semiconductor device, and limits the use of the semiconductor device.
The inventor researches and discovers that an oxide layer and a high-resistance layer positioned on the oxide layer are formed on part of the surface of a substrate, a dielectric layer is formed on the surface of the high-resistance layer and the surface of the substrate which is not covered by the oxide layer and the high-resistance layer, the dielectric layer is etched, a first through hole and a second through hole are formed in the dielectric layer, the bottom of the first through hole is exposed out of the top surface of a conductive layer in the substrate, and the bottom of the second through hole is exposed out of the top surface of the oxide layer; due to the presence of the oxide layer. In the process of forming the connecting layer in the subsequent first through hole, the connecting layer cannot be formed at the bottom of the second through hole, so that the problem of uneven growth height of the connecting layer does not exist in the second through hole, and meanwhile, the problem of interface difference does not exist in the high-resistance layer, so that the subsequent metal layer is directly formed in the second through hole, the quality of an interface formed by the metal layer in the second through hole can be improved, the performance of a finally formed semiconductor device is improved, and the application range of the semiconductor device is expanded.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring first to fig. 4, a substrate 200 is provided, and an oxide layer 201 and a high resistance layer 202 on the oxide layer 201 are formed on a portion of the surface of the substrate 200.
In this embodiment, the substrate 200 has a conductive layer 203 therein.
In this embodiment, the base 200 further includes a substrate, and the conductive layer 203 is located on the substrate and includes a memory device, a logic device, and the like on the substrate.
In this embodiment, the conductive layer 203 is a metal layer, and is formed above the source-drain doped layer for electrically connecting the source-drain doped layer with the outside.
In this embodiment, the material of the conductive layer 203 is cobalt (Co); in other embodiments, the material of the conductive layer 203 may also be a metal material such as copper, aluminum, or the like.
In this embodiment, the step of forming an oxide layer 201 and a high resistance layer 202 on the oxide layer 201 on a part of the surface of the substrate 200 includes: forming an initial oxide layer (not shown in the figure) on the surface of the substrate 200, forming an initial high resistance layer (not shown in the figure) on the initial oxide layer, etching to remove the initial oxide layer and the initial high resistance layer above the conductive layer 203, and forming an oxide layer 201 and a high resistance layer 202 on the oxide layer 201 on a part of the surface of the substrate 200.
In this embodiment, before the initial oxide layer is formed, an etch stop layer 204 is formed on the surface of the substrate 200, and the purpose of the etch stop layer 204 is to protect the conductive layer 203 and the top surface of the substrate 200 from being damaged during the process of removing the initial oxide layer and the initial high resistance layer over the conductive layer 203 by etching.
In this embodiment, the material of the etch stop layer 204 is tungsten nitride, aluminum nitride, or silicon nitride.
In this embodiment, the material of the oxide layer 201 is silicon oxide.
In other embodiments, the material of the oxide layer 201 may also be silicon nitride.
In this embodiment, the forming process of the oxide layer 201 is an atomic layer deposition process or a chemical vapor deposition process.
When the oxide layer 201 is made of silicon nitride, the process of forming the oxide layer 201 is an atomic layer deposition process.
When the forming process of the oxide layer 201 adopts an atomic layer deposition process, specific process parameters include: using SAM24 and oxygen as raw materials, wherein the flow rate of the oxygen is 0-10 slm; the reaction temperature is 150-450 ℃.
When the formation process of the oxide layer 201 adopts a chemical vapor deposition process, specific process parameters include: TEOS and oxygen are used as raw materials, wherein the flow rate of the oxygen is 500 sccm-1500 sccm, and the reaction temperature is 150-450 ℃.
In this embodiment, the purpose of forming the oxide layer 201 is to make the connection layer not grow on the oxide layer 201 and the connection layer not etch the oxide layer 201 during the growth process by using the insulation property of the oxide layer 201 during the subsequent formation of the connection layer, so as to ensure the surface property of the oxide layer 201.
In this embodiment, the thickness of the oxide layer 201 is
To
When the thickness of the oxide layer 201 is less than
In the meantime, the thickness of the oxide layer 201 formed is too thin, so that the risk of being etched through is easy to occur; when the thickness of the oxide layer 201 is larger than
If the thickness of the oxide layer 201 formed at this time is too thick, the amount of metal layers that can be formed in the second through hole later is small, and then the risk that the oxide layer 201 is exposed in the planarization process later easily occurs, which affects the performance of the formed semiconductor device.
In this embodiment, after the oxide layer 201 is formed, the high resistance layer 202 is formed.
In this embodiment, the material of the high resistance layer 202 is TiN.
In other embodiments, the material of the high resistance layer 202 may also be TiN or TaN or TiO2Or WN or WSi.
In this embodiment, the etching selectivity of the oxide layer 201 to the high resistance layer 202 is less than 1.
In this embodiment, since the etching selection ratio of the oxide layer 201 to the high-resistance layer 202 is smaller than 1, it is ensured that only the high-resistance layer 202 is etched without damaging the surface of the oxide layer 201 in the subsequent process of etching the high-resistance layer 202.
In this embodiment, no protective layer is formed on the surface of the high resistance layer 202; in other implementations, a protective layer may also be formed on the surface of the high resistance layer 202 to protect the high resistance layer 202.
Referring to fig. 5, a dielectric layer 205 is formed on the surface of the high resistance layer 202 and the surface of the substrate 200 not covered by the oxide layer 201 and the high resistance layer 202.
In this embodiment, the dielectric layer 205 is made of silicon oxide.
In other embodiments, the material of the dielectric layer 205 may also be silicon nitride, silicon nitride boride, silicon oxycarbide, silicon oxynitride, or the like.
In this embodiment, the dielectric layer 205 is formed by chemical vapor deposition, and the process parameters of the chemical vapor deposition process include that the adopted gas includes oxygen and ammonia (NH)3) And N (SiH)3)3The flow rate of oxygen is 20 sccm-10000 sccm, and ammonia (NH)3) The flow rate of the gas is 20sccm to 10000sccm, N (SiH)3)3The flow rate of the gas is 20 sccm-10000 sccm, the pressure of the chamber is 0.01-10 torr, and the temperature is 30-90 ℃.
Referring to fig. 6, the dielectric layer 205 is etched, a first through hole 206 and a second through hole 207 are formed in the dielectric layer 205, the bottom of the first through hole 206 is exposed on the top surface of the conductive layer 203 in the substrate 200, and the bottom of the second through hole 207 is exposed on the top surface of the oxide layer 201.
In this embodiment, the process of forming the first through hole 206 and the second through hole 207 is a dry etching process; in other embodiments, the first via 206 and the second via 207 may be formed by a wet etching process.
In this embodiment, the parameters of the dry etching process include: the gas used comprises CF4And CH3F，CF4The flow rate of (1) is 20sccm to 200sccm, CH3The flow rate of F is 20 sccm-50 sccm, the source radio frequency power is 200W-500W, and the chamber pressure is 1 Torr-10 Torr.
In this embodiment, the reason for using the dry etching process is that, during the dry etching process, the etching rate in the longitudinal direction is greater than that in the lateral direction, so that in the process of forming the first through hole 206 and the second through hole 207, the influence on the lateral cross section of the first through hole 206 and the second through hole 207 can be reduced.
In this embodiment, the first through hole 206 is formed to provide a space for forming a connection layer on the surface of the conductive layer 203.
Referring to fig. 7, after the first via 206 and the second via 207 are formed, a connection layer 208 is formed in the first via 206.
In this embodiment, the connection layer 208 is made of a metal material, and plays a role in connection, so that when power is externally connected, the transistor can be electrically connected to the outside.
In this embodiment, the material of the connection layer 208 is tungsten; in other embodiments, the material of the connection layer 208 may also be other metals, such as copper, aluminum, silver, and the like.
In the present embodiment, the process of forming the connection layer 208 is a selective growth process; in other embodiments, the connection layer 208 may also be formed by a chemical vapor deposition process, an atomic layer deposition process, or the like.
In this embodiment, the reason for forming the connection layer 208 by using the selective growth process is that the selective growth process can make the formed connection layer 208 grow up slowly from the top surface of the conductive layer 203, on one hand, it is ensured that the formed connection layer 208 has good compactness, and on the other hand, because the connection layer 208 grows from the top of the conductive layer 203, no excess connection layer 208 is formed on the dielectric layer 205, so that the excess connection layer 208 is not removed by using a chemical mechanical polishing manner, the process flow is reduced, meanwhile, damage to the conductive layer 203 in the chemical mechanical polishing process is reduced, and the quality of the finally formed semiconductor device is improved.
In this embodiment, due to the existence of the oxide layer 201 at the bottom of the second via hole 207, in the process of forming the connection layer 208, the connection layer 208 cannot be attached to and grown on the oxide layer 201, and meanwhile, the oxide layer 201 is not damaged in the process of forming the connection layer 208, so that the interface consistency in the second via hole 207 is ensured, and after a metal layer is formed in the second via hole 207, the difference in the quality of the interface formed in the second via hole 207 by the metal layer is small, so that in the performance test, the consistent electrical property in the second via hole 207 is easily ensured, the performance of the finally formed semiconductor device is ensured, and the application range of the semiconductor device is expanded.
Referring to fig. 8, after the connection layer 208 is formed, an adhesion layer 209 is formed on the dielectric layer 205, on the connection layer 208, and on the sidewalls and the bottom of the second via 207; a metal layer 210 is formed on the adhesion layer 209, and the metal layer 210 fills the second via 207.
In this embodiment, the material of the adhesion layer 209 is titanium nitride (TiN); in other embodiments, the material of the adhesion layer 209 may also be TaN or the like.
In this embodiment, before forming the adhesion layer 209, the surface of the connection layer 208 is planarized until the plane of the connection layer 208 is flush with the surface of the dielectric layer 205.
In this embodiment, the adhesion layer 209 may serve as a transition layer, which can provide a better formation interface for a metal layer to be formed later, thereby improving the formation quality of the finally formed metal layer.
In the present embodiment, the process of forming the adhesion layer 209 is an atomic layer deposition process; in other embodiments, the adhesion layer 209 may also be formed by chemical vapor deposition, physical vapor deposition process, and the like.
In this embodiment, the reason why the adhesion layer 209 is formed by using the atomic layer deposition process is that the adhesion layer 209 formed by using the atomic layer deposition process has a good step coverage capability, and thus the uniformity and the flatness of the adhesion layer 209 formed in this way are good, so that the difference in the interface property between the material formed in the second through hole 207 and the second through hole 207 is reduced, and thus, in the subsequent testing process, the difference in various performances does not occur, which is beneficial to improving the uniformity of the device performance in the second through hole 207, so that the uniformity of the performance of the finally formed semiconductor device is improved, and the application range of the semiconductor device is expanded.
In the embodiment, the process of forming the metal layer 210 is a chemical vapor deposition process; in other embodiments, one or more combinations of selective growth processes, physical vapor deposition processes, atomic layer deposition processes, or chemical vapor deposition processes may also be employed.
In the present embodiment, the material of the metal layer 210 includes tungsten.
In this embodiment, the process parameters for forming the metal layer 210 include: the reaction gas comprises WF6Gas and H2Wherein the WF6The gas flow rate of the gas is 50-1000 sccm, and the gas flow rate is H2The gas flow rate of (2) is 500-20000 sccm; the reaction temperature is 100-400 ℃; the pressure of the chamber is 2-100 torr.
After the metal layer 210 is formed, it is planarized so that the surface of the metal layer 210 is flush.
Accordingly, the present invention also provides a semiconductor device comprising: a substrate 200; a conductive layer 203 located within the substrate 200; an oxide layer 201 on a portion of the surface of the substrate 200; a high resistance layer 202 on the oxide layer 201; a dielectric layer 205 on the substrate 200 and the high resistance layer 202; a first via 206 located in the dielectric layer 205, the bottom of which exposes the top surface of the conductive layer 203; a second via 207 located in the dielectric layer 205, the bottom of which is exposed out of the top surface of the oxide layer 201; a connection layer 208 located within the first via 206; an adhesion layer 209 on the surface of the dielectric layer 205, on the surface of the connection layer 208, and on the sidewalls and bottom of the second via 207; and a metal layer 210 located on the adhesion layer 209 and filling the second through hole 207.
In this embodiment, the bottom of the first via 206 exposes the top surface of the conductive layer 203, the bottom of the second via 207 exposes the top surface of the oxide layer 201, the first via 206 has a connection layer 208 therein, the adhesion layer 209 is located on the surface of the dielectric layer 205, the surface of the connection layer 208, and the sidewall and the bottom of the second via 207, the metal layer 210 is located on the adhesion layer 209 and fills up the second via 207, so that since there is no connection layer in the second via 207, the problem that the growth heights of the connecting layers are different in the second through hole is avoided, the problem that the interface between the connecting layer 208 and the metal layer 210 is uneven or defective in the second through hole 207 is thoroughly solved, the quality of the metal layer 210 formed in the second through hole 207 is improved, thereby improving the performance of the finally formed semiconductor device and expanding the application range of the semiconductor device.
The thickness of the oxide layer 201 is
To
In this embodiment, the thickness of the oxide layer 201 is
To
When the thickness of the oxide layer 201 is less than
When the thickness of the oxide layer 201 is too thin, the risk that the oxide layer 201 is etched through is increased; when the thickness of the oxide layer 201 is larger than
If the thickness of the oxide layer 201 formed at this time is too thick, the amount of metal layer that can be formed in the second via hole later is small, and the risk that the high-resistance layer 202 is exposed in the planarization process later increases, which affects the performance of the formed semiconductor device.
And the etching selection ratio of the oxide layer to the high-resistance layer is less than 1.
In this embodiment, since the etching selection ratio of the oxide layer 201 to the high-resistance layer 202 is smaller than 1, it is ensured that only the high-resistance layer 202 is etched without damaging the surface of the oxide layer 201 in the subsequent process of etching the high-resistance layer 202.
In this embodiment, the material of the oxide layer is silicon oxide or silicon nitride.
In this embodiment, the forming process of the oxide layer 201 is an atomic layer deposition process or a chemical vapor deposition process.
When the forming process of the oxide layer 201 adopts an atomic layer deposition process, specific process parameters include: using SAM24 and oxygen as raw materials, wherein the flow rate of the oxygen is 0-10 slm; the reaction temperature is 150-450 ℃.
When the formation process of the oxide layer 201 adopts a chemical vapor deposition process, specific process parameters include: TEOS and oxygen are used as raw materials, wherein the flow rate of the oxygen is 500 sccm-1500 sccm, and the reaction temperature is 150-450 ℃.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. A semiconductor device, comprising:
a substrate;
a conductive layer within the substrate;
an oxide layer on a portion of the surface of the substrate;
the high-resistance layer is positioned on the oxide layer;
the dielectric layer is positioned on the substrate and the high-resistance layer;
the first through hole is positioned in the medium layer, and the bottom of the first through hole is exposed out of the top surface of the conducting layer;
the second through hole is positioned in the medium layer, and the bottom of the second through hole is exposed out of the top surface of the oxide layer;
the connecting layer is positioned in the first through hole;
the adhesion layers are positioned on the surface of the dielectric layer, the surface of the connecting layer and the side wall and the bottom of the second through hole;
and the metal layer is positioned on the adhesion layer and is filled in the second through hole.
2. The semiconductor device according to claim 1, wherein the oxide layer has a thickness of
To
3. The semiconductor device according to claim 1, wherein an etching selection ratio of the oxide layer to the high-resistance layer is less than 1.
4. The semiconductor device according to claim 1, wherein a material of the oxide layer is silicon oxide or silicon nitride.
5. A method of forming a semiconductor device, comprising:
providing a substrate, and forming an oxide layer and a high-resistance layer on the oxide layer on part of the surface of the substrate;
forming dielectric layers on the surface of the high-resistance layer and the surface of the substrate which is not covered by the oxide layer and the high-resistance layer;
and etching the dielectric layer, forming a first through hole and a second through hole in the dielectric layer, wherein the bottom of the first through hole is exposed out of the top surface of the conductive layer in the substrate, and the bottom of the second through hole is exposed out of the top surface of the oxide layer.
6. The formation method according to claim 5, wherein the formation process of the oxide layer is an atomic layer deposition process or a chemical vapor deposition process.
7. Such asThe method of claim 5, wherein the oxide layer has a thickness of
To
8. The method of claim 5, wherein an etch selectivity ratio of the oxide layer to the high resistance layer is less than 1.
9. The forming method according to claim 5, wherein after the first via hole and the second via hole are formed, a connection layer is formed within the first via hole.
10. The forming method of claim 9, wherein after forming the connection layer, forming an adhesion layer on the dielectric layer, on the connection layer, and on sidewalls and a bottom of the second via; and forming a metal layer on the adhesion layer, wherein the metal layer is filled in the second through hole.
11. The method according to claim 5, wherein a material of the oxide layer is silicon oxide or silicon nitride.
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| CN202011056478.8A CN114334874A (en) | 2020-09-30 | 2020-09-30 | Semiconductor device and method of forming the same |
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| CN202011056478.8A CN114334874A (en) | 2020-09-30 | 2020-09-30 | Semiconductor device and method of forming the same |
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